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sh: Update cache control.

D-Cache control support.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>

--- a/arch/sh/cpu/sh4/cache.c

+++ b/arch/sh/cpu/sh4/cache.c

		@@ -68,11 +68,12 @@ static inline void cache_wback_all(void)
68	68	back_to_P1();
69	69	}
70	70
	71	+static unsigned long ccr_bit[] = {
	72	+ 0x00000900, /* ICE */
	73	+ 0x0000000b, /* OCE,WT */
	74	+};
71	75
72		-#define CACHE_ENABLE 0
73		-#define CACHE_DISABLE 1
74		-
75		-int cache_control(unsigned int cmd)
	76	+int cache_control(unsigned int io, unsigned int cmd)
76	77	{
77	78	unsigned long ccr;
78	79

		@@ -82,23 +83,38 @@ int cache_control(unsigned int cmd)
82	83	if (ccr & CCR_CACHE_ENABLE)
83	84	cache_wback_all();
84	85
85		- if (cmd == CACHE_DISABLE)
86		- outl(CCR_CACHE_STOP, CCR);
	86	+#ifdef CONFIG_CPU_TYPE_R
	87	+ if (!ccr)
	88	+ ccr \|= 0x80000000;
	89	+#endif
	90	+ if (cmd == ON)
	91	+ ccr \|= ccr_bit[io];
87	92	else
88		- outl(CCR_CACHE_INIT, CCR);
	93	+ ccr &= ~ccr_bit[io];
	94	+ outl(ccr, CCR);
	95	+
89	96	back_to_P1();
90	97
91	98	return 0;
92	99	}
93	100
	101	+int cache_status(unsigned int io)
	102	+{
	103	+ unsigned long ccr;
	104	+
	105	+ ccr = inl(CCR);
	106	+ return ccr & ccr_bit[io];
	107	+}
	108	+
94	109	void flush_dcache_range(unsigned long start, unsigned long end)
95	110	{
96	111	u32 v;
97	112
	113	+ printf("%s\n", __func__);
98	114	start &= ~(L1_CACHE_BYTES - 1);
99	115	for (v = start; v < end; v += L1_CACHE_BYTES) {
100	116	asm volatile ("ocbwb %0" : /* no output */
101		- : "m" (__m(v)));
	117	+ : "m" ((unsigned long )v));
102	118	}
103	119	}
104	120

		@@ -109,6 +125,6 @@ void invalidate_dcache_range(unsigned long start, unsigned long end)
109	125	start &= ~(L1_CACHE_BYTES - 1);
110	126	for (v = start; v < end; v += L1_CACHE_BYTES) {
111	127	asm volatile ("ocbi %0" : /* no output */
112		- : "m" (__m(v)));
	128	+ : "m" ((unsigned long )v));
113	129	}
114	130	}

--- a/arch/sh/cpu/sh4/cpu.c

+++ b/arch/sh/cpu/sh4/cpu.c

		@@ -46,30 +46,32 @@ void flush_cache (unsigned long addr, unsigned long size)
46	46
47	47	void icache_enable (void)
48	48	{
49		- cache_control(0);
	49	+ cache_control(ICACHE, ON);
50	50	}
51	51
52	52	void icache_disable (void)
53	53	{
54		- cache_control(1);
	54	+ cache_control(ICACHE, OFF);
55	55	}
56	56
57	57	int icache_status (void)
58	58	{
59		- return 0;
	59	+ return cache_status(ICACHE);
60	60	}
61	61
62	62	void dcache_enable (void)
63	63	{
	64	+ cache_control(OCACHE, ON);
64	65	}
65	66
66	67	void dcache_disable (void)
67	68	{
	69	+ cache_control(OCACHE, OFF);
68	70	}
69	71
70	72	int dcache_status (void)
71	73	{
72		- return 0;
	74	+ return cache_status(OCACHE);
73	75	}
74	76
75	77	int cpu_eth_init(bd_t *bis)

--- a/arch/sh/include/asm/cache.h

+++ b/arch/sh/include/asm/cache.h

		@@ -3,10 +3,16 @@
3	3
4	4	#if defined(CONFIG_CPU_SH4)
5	5
6		-int cache_control(unsigned int cmd);
	6	+int cache_control(unsigned int io, unsigned int cmd);
	7	+int cache_status(unsigned int io);
7	8
8	9	#define L1_CACHE_BYTES 32
9	10
	11	+#define ICACHE 0
	12	+#define OCACHE 1
	13	+#define ON 0
	14	+#define OFF 1
	15	+
10	16	struct __large_struct { unsigned long buf[100]; };
11	17	#define __m(x) ((struct __large_struct )(x))
12	18