Commit: 1076e7d3d755766f9dfec6a0fbe67de7d7da08f8 - uboot (git)

Commit MetaInfo

• Revision: 1076e7d3d755766f9dfec6a0fbe67de7d7da08f8 (tree)
• Zeit: 2016-05-22 15:02:07
• Autor: Yoshinori Sato <ysato@user...>
• Commiter: Yoshinori Sato

Log Message

pci: Add SH7751 DM driver.

Signed-off-by: Yoshinori Sato <[e-mail]>

Ändern Zusammenfassung

• modified: drivers/pci/Makefile
• add: drivers/pci/pci_sh7751_dm.c

Diff

--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -12,8 +12,11 @@ obj-$(CONFIG_DM_PCI_COMPAT) += pci_compat.o
 obj-$(CONFIG_PCI_SANDBOX) += pci_sandbox.o
 obj-$(CONFIG_SANDBOX) += pci-emul-uclass.o
 obj-$(CONFIG_X86) += pci_x86.o
+obj-$(CONFIG_SH7751_PCI) +=pci_sh7751_dm.o
 else
 obj-$(CONFIG_PCI) += pci.o pci_auto_old.o
+obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o
+obj-$(CONFIG_SH4_PCI) += pci_sh4.o
 endif
 obj-$(CONFIG_PCI) += pci_auto_common.o pci_common.o
 
@@ -24,8 +27,6 @@ obj-$(CONFIG_PCI_MSC01) += pci_msc01.o
 obj-$(CONFIG_PCIE_IMX) += pcie_imx.o
 obj-$(CONFIG_FTPCI100) += pci_ftpci100.o
 obj-$(CONFIG_PCI_MVEBU) += pci_mvebu.o
-obj-$(CONFIG_SH4_PCI) += pci_sh4.o
-obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o
 obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
 obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o
 obj-$(CONFIG_TSI108_PCI) += tsi108_pci.o

--- /dev/null
+++ b/drivers/pci/pci_sh7751_dm.c
@@ -0,0 +1,233 @@
+/*
+ * SH7751 PCI Controller (PCIC) for U-Boot.
+ * (C) Dustin McIntire ([e-mail])
+ * (C) 2007,2008 Nobuhiro Iwamatsu <[e-mail]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+/* Register addresses and such */
+#define PCICONF0 0x0000
+#define PCICONF1 0x0004
+#define PCICONF2 0x0008
+#define PCICONF3 0x000C
+#define PCICONF4 0x0010
+#define PCICONF5 0x0014
+#define PCICONF6 0x0018
+#define PCICR    0x0100
+#define PCILSR0  0x0104
+#define PCILSR1  0x0108
+#define PCILAR0  0x010C
+#define PCILAR1  0x0110
+#define PCIMBR   0x01C4
+#define PCIIOBR  0x01C8
+#define PCIPINT  0x01CC
+#define PCIPINTM 0x01D0
+#define PCICLKR  0x01D4
+#define PCIBCR1  0x01E0
+#define PCIBCR2  0x01E4
+#define PCIWCR1  0x01E8
+#define PCIWCR2  0x01EC
+#define PCIWCR3  0x01F0
+#define PCIMCR   0x01F4
+#define PCIBCR3  0x01F8
+#define PCIPAR   0x01C0
+#define PCIPDR   0x0220
+
+#define BCR1_BREQEN				0x00080000
+#define PCI_SH7751_ID			0x35051054
+#define PCI_SH7751R_ID			0x350E1054
+#define SH7751_PCICONF1_WCC		0x00000080
+#define SH7751_PCICONF1_PER		0x00000040
+#define SH7751_PCICONF1_BUM		0x00000004
+#define SH7751_PCICONF1_MES		0x00000002
+#define SH7751_PCICONF1_CMDS	0x000000C6
+#define SH7751_PCI_HOST_BRIDGE	0x6
+#define SH7751_PCICR_PREFIX		0xa5000000
+#define SH7751_PCICR_PRST		0x00000002
+#define SH7751_PCICR_CFIN		0x00000001
+#define SH7751_PCIPINT_D3		0x00000002
+#define SH7751_PCIPINT_D0		0x00000001
+#define SH7751_PCICLKR_PREFIX   0xa5000000
+
+#define SH7751_PCI_MEM_BASE		0xFD000000
+#define SH7751_PCI_MEM_SIZE		0x01000000
+#define SH7751_PCI_IO_BASE		0xFE240000
+#define SH7751_PCI_IO_SIZE		0x00040000
+
+#define SH7751_CS3_BASE_ADDR    0x0C000000
+#define SH7751_P2CS3_BASE_ADDR  0xAC000000
+
+#define p4_in(addr)	(*(volatile u32 *)(addr))
+#define p4_out(data, addr) (*(volatile u32 *)(addr)) = (data)
+
+DECLARE_GLOBAL_DATA_PTR;
+static fdt_addr_t addr;
+
+static int sh4_pci_read_config(struct udevice *bus, pci_dev_t dev,
+			       uint offset, ulong *valuep, enum pci_size_t size)
+{
+	u32 par_data = 0x80000000 | dev;
+	u32 val;
+
+	p4_out(par_data | (offset & 0xfc), addr + PCIPAR);
+	val = p4_in(addr + PCIPDR);
+	switch (size) {
+	case PCI_SIZE_8:
+		val >>= 8 * (offset & 3);
+		*valuep = val & 0xff;
+		break;
+	case PCI_SIZE_16:
+		val >>= 16 * ((offset & 3) >> 1);
+		*valuep = val & 0xffff;
+		break;
+	case PCI_SIZE_32:
+		*valuep = val;
+		break;
+	}
+	return 0;
+}
+
+static int sh4_pci_write_config(struct udevice *bus, pci_dev_t dev,
+			       uint offset, ulong valuep, enum pci_size_t size)
+{
+	u32 par_data = 0x80000000 | dev;
+	u32 val;
+	
+	p4_out(par_data | (offset & 0xfc), addr + PCIPAR);
+	val = p4_in(addr + PCIPDR);
+	switch (size) {
+	case PCI_SIZE_8:
+		val &= ~(0xff << (8 * (offset & 3)));
+		val |= (valuep & 0xff) << (8 * (offset & 3));
+		break;
+	case PCI_SIZE_16:
+		val &= ~(0xffff <<(16 *  ((offset & 3) >> 1)));
+		val |= (valuep & 0xffff) << (16 *((offset & 3) >> 1));
+		break;
+	case PCI_SIZE_32:
+		val = valuep;
+		break;
+	}
+	p4_out(val, addr + PCIPDR);
+
+	return 0;
+}
+
+static int pci_sh7751_init_dm(struct udevice *dev)
+{
+	addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	/* Double-check that we're a 7751 or 7751R chip */
+	if (p4_in(addr + PCICONF0) != PCI_SH7751_ID
+	    && p4_in(addr + PCICONF0) != PCI_SH7751R_ID) {
+		printf("PCI: Unknown PCI host bridge.\n");
+		return 1;
+	}
+	printf("PCI: SH7751 PCI host bridge found.\n");
+
+	/* Double-check some BSC config settings */
+	/* (Area 3 non-MPX 32-bit, PCI bus pins) */
+	if ((inl(BCR1) & 0x20008) == 0x20000) {
+		printf("SH7751_BCR1 value is wrong(0x%08X)\n",
+			inl(BCR1));
+		return 2;
+	}
+	if ((inw(BCR2) & 0xC0) != 0xC0) {
+		printf("SH7751_BCR2 value is wrong(0x%04X)\n",
+			inw(BCR2));
+		return 3;
+	}
+	if (inw(BCR2) & 0x01) {
+		printf("SH7751_BCR2 value is wrong(0x%04X)\n",
+			inw(BCR2));
+		return 4;
+	}
+
+	/* Force BREQEN in BCR1 to allow PCIC access */
+	outl((inl(BCR1) | BCR1_BREQEN), BCR1);
+
+	/* Toggle PCI reset pin */
+	p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_PRST), addr + PCICR);
+	udelay(32);
+	p4_out(SH7751_PCICR_PREFIX, addr + PCICR);
+
+	/* Set cmd bits: WCC, PER, BUM, MES */
+	/* (Addr/Data stepping, Parity enabled, Bus Master, Memory enabled) */
+	p4_out(0xfb900047, addr + PCICONF1);	/* K.Kino */
+
+	/* Define this host as the host bridge */
+	p4_out((SH7751_PCI_HOST_BRIDGE << 24), addr + PCICONF2);
+
+	/* Force PCI clock(s) on */
+	p4_out(0x00, addr + PCICLKR);
+	p4_out(0x03, addr + PCICLKR);
+
+	/* Clear powerdown IRQs, also mask them (unused) */
+	p4_out((SH7751_PCIPINT_D0 | SH7751_PCIPINT_D3), addr + PCIPINT);
+	p4_out(0, addr + PCIPINTM);
+
+	p4_out(0xab000001, addr + PCICONF4);
+
+	/* Set up target memory mappings (for external DMA access) */
+	/* Map both P0 and P2 range to Area 3 RAM for ease of use */
+	p4_out((64 - 1) << 20, addr + PCILSR0);
+	p4_out(SH7751_CS3_BASE_ADDR, addr + PCILAR0);
+	p4_out(0, addr + PCILSR1);
+	p4_out(0, addr + PCILAR1);
+	p4_out(SH7751_CS3_BASE_ADDR, addr + PCICONF5);
+	p4_out(0xd0000000, addr + PCICONF6);
+
+	/* Map memory window to same address on PCI bus */
+	p4_out(fdtdec_get_int(gd->fdt_blob, dev->of_offset, "renesas,pcimem", 0),
+	       addr + PCIMBR);
+
+	/* Map IO window to same address on PCI bus */
+	p4_out(fdtdec_get_int(gd->fdt_blob, dev->of_offset, "renesas,pciio", 0),
+	       addr + PCIIOBR);
+
+	/* set BREQEN */
+	outl(inl(BCR1) | 0x00080000, BCR1);
+
+	/* Copy BSC registers into PCI BSC */
+	p4_out(inl(BCR1), addr + PCIBCR1);
+	p4_out(inw(BCR2), addr + PCIBCR2);
+	p4_out(inw(BCR3), addr + PCIBCR3);
+	p4_out(inl(WCR1), addr + PCIWCR1);
+	p4_out(inl(WCR2), addr + PCIWCR2);
+	p4_out(inl(WCR3), addr + PCIWCR3);
+	p4_out(inl(MCR), addr + PCIMCR);
+
+	/* Finally, set central function init complete */
+	p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_CFIN), addr + PCICR);
+
+	return 0;
+}
+
+static const struct dm_pci_ops sh7751_pci_ops = {
+	.read_config = sh4_pci_read_config,
+	.write_config = sh4_pci_write_config,
+};
+
+static const struct udevice_id sh7751_pci_ids[] = {
+	{ .compatible = "renesas,sh7751-pci" },
+	{ }
+};
+
+U_BOOT_DRIVER(pci_sh7751) = {
+	.name	= "pci_sh7751",
+	.id	= UCLASS_PCI,
+	.of_match = sh7751_pci_ids,
+	.ops	= &sh7751_pci_ops,
+	.bind	= pci_sh7751_init_dm,
+	.per_child_platdata_auto_alloc_size =
+			sizeof(struct pci_child_platdata),
+};