| Revision | da61f1256f55a5e9fc03f7c88e3caa425d6bf8cf (tree) |
|---|---|
| Zeit | 2022-01-21 14:52:56 |
| Autor | Frank Chang <frank.chang@sifi...> |
| Commiter | Alistair Francis |
target/riscv: rvv-1.0: Add Zve32f support for configuration insns
All Zve* extensions support the vector configuration instructions.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-13-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/insn_trans/trans_rvv.c.inc (diff)| @@ -152,7 +152,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2) | ||
| 152 | 152 | TCGv s1, dst; |
| 153 | 153 | |
| 154 | 154 | if (!require_rvv(s) || |
| 155 | - !(has_ext(s, RVV) || s->ext_zve64f)) { | |
| 155 | + !(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) { | |
| 156 | 156 | return false; |
| 157 | 157 | } |
| 158 | 158 |
| @@ -188,7 +188,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2) | ||
| 188 | 188 | TCGv dst; |
| 189 | 189 | |
| 190 | 190 | if (!require_rvv(s) || |
| 191 | - !(has_ext(s, RVV) || s->ext_zve64f)) { | |
| 191 | + !(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) { | |
| 192 | 192 | return false; |
| 193 | 193 | } |
| 194 | 194 |
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