OSDN > Entwickler > ysato > Kammer > qemu > Commit

qemu RX
Fork

(Original-Repository, kein Fork Herkunft)

R/O
HTTP
SSH
HTTPS

Commit

Commit MetaInfo

Revision	b4a99d40276eb5bdfa849cc04344d9a2c4c820ef (tree)
Zeit	2022-01-21 14:52:56
Autor	Frank Chang <frank.chang@sifi...>
Commiter	Alistair Francis

Log Message

target/riscv: rvv-1.0: Add Zve64f extension into RISC-V

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-2-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Ändern Zusammenfassung

modified: target/riscv/cpu.c (diff)
modified: target/riscv/cpu.h (diff)
modified: target/riscv/cpu_helper.c (diff)
modified: target/riscv/csr.c (diff)
modified: target/riscv/translate.c (diff)

Diff

--- a/target/riscv/cpu.c

+++ b/target/riscv/cpu.c

		@@ -609,6 +609,10 @@ static void riscv_cpu_realize(DeviceState dev, Error *errp)
609	609	}
610	610	set_vext_version(env, vext_version);
611	611	}
	612	+ if (cpu->cfg.ext_zve64f && !cpu->cfg.ext_f) {
	613	+ error_setg(errp, "Zve64f extension depends upon RVF.");
	614	+ return;
	615	+ }
612	616	if (cpu->cfg.ext_j) {
613	617	ext \|= RVJ;
614	618	}

--- a/target/riscv/cpu.h

+++ b/target/riscv/cpu.h

		@@ -340,6 +340,7 @@ struct RISCVCPU {
340	340	bool ext_icsr;
341	341	bool ext_zfh;
342	342	bool ext_zfhmin;
	343	+ bool ext_zve64f;
343	344
344	345	char *priv_spec;
345	346	char *user_spec;

--- a/target/riscv/cpu_helper.c

+++ b/target/riscv/cpu_helper.c

		@@ -69,12 +69,15 @@ static RISCVMXL cpu_get_xl(CPURISCVState *env)
69	69	void cpu_get_tb_cpu_state(CPURISCVState env, target_ulong pc,
70	70	target_ulong cs_base, uint32_t pflags)
71	71	{
	72	+ CPUState *cs = env_cpu(env);
	73	+ RISCVCPU *cpu = RISCV_CPU(cs);
	74	+
72	75	uint32_t flags = 0;
73	76
74	77	*pc = env->pc;
75	78	*cs_base = 0;
76	79
77		- if (riscv_has_ext(env, RVV)) {
	80	+ if (riscv_has_ext(env, RVV) \|\| cpu->cfg.ext_zve64f) {
78	81	/*
79	82	* If env->vl equals to VLMAX, we can use generic vector operation
80	83	* expanders (GVEC) to accerlate the vector operations.

--- a/target/riscv/csr.c

+++ b/target/riscv/csr.c

		@@ -47,7 +47,11 @@ static RISCVException fs(CPURISCVState *env, int csrno)
47	47
48	48	static RISCVException vs(CPURISCVState *env, int csrno)
49	49	{
50		- if (env->misa_ext & RVV) {
	50	+ CPUState *cs = env_cpu(env);
	51	+ RISCVCPU *cpu = RISCV_CPU(cs);
	52	+
	53	+ if (env->misa_ext & RVV \|\|
	54	+ cpu->cfg.ext_zve64f) {
51	55	#if !defined(CONFIG_USER_ONLY)
52	56	if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
53	57	return RISCV_EXCP_ILLEGAL_INST;

--- a/target/riscv/translate.c

+++ b/target/riscv/translate.c

		@@ -79,6 +79,7 @@ typedef struct DisasContext {
79	79	bool ext_ifencei;
80	80	bool ext_zfh;
81	81	bool ext_zfhmin;
	82	+ bool ext_zve64f;
82	83	bool hlsx;
83	84	/* vector extension */
84	85	bool vill;

		@@ -894,6 +895,7 @@ static void riscv_tr_init_disas_context(DisasContextBase dcbase, CPUState cs)
894	895	ctx->ext_ifencei = cpu->cfg.ext_ifencei;
895	896	ctx->ext_zfh = cpu->cfg.ext_zfh;
896	897	ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;
	898	+ ctx->ext_zve64f = cpu->cfg.ext_zve64f;
897	899	ctx->vlen = cpu->cfg.vlen;
898	900	ctx->elen = cpu->cfg.elen;
899	901	ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);

qemu RX Fork