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target/rx: gdbstub add acc register operation.

I added it because the operation of the acc register was not implemented.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>

target/rx: Fix helper definiton.

Due to an incorrect definition of helper,
TCG optimization could sometimes behave unexpectedly.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>

MIPS patches queue

- minor simplifications in PREF / JR opcodes
- merge 32-bit/64-bit Release6 decodetree definitions
- converted NEC Vr54xx extension opcodes to decodetree
- housekeeping in gen_helper() macros
- replace TARGET_WORDS_BIGENDIAN #ifdef'ry by cpu_is_bigendian()
- allow Loongson 3A1000 to use up to 48-bit VAddr
-----BEGIN PGP SIGNATURE-----

iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmEmI78ACgkQ4+MsLN6t
wN4RLw/+PIBVfaDvASnFa2f9b4SGQ2WiM0LuLh/sN6ieMiFccqJZPq2Dz5GCQsR7
7v2+MZ9gcAoWH/NCft+vbXGwiP9exoChb8c65Gm0GdpQ3sKPYXJJAi/D0vjuPMGe
Yk8DrfERavu4bcpXPaC+B3p8krii88W+vEYvmvWfirD+gWxjF/HviLzHQK/62YMK
N695BYVav5Fd3fjqn3p7Kw/WdP++NS757G53dSF/r5l1wFEGFZAuYW7R2rWDQsz+
yWvPUkIFoJ9OXitKw01FVaDNXF3a1efMhZjFvCr0EU0eF4qsxAywXomC4CDpAo+Y
s15aNZoxWM4D0eEoNLm874QAgNu9txPJPg5kuZVpBDwdTKWMrShj5+m/QlWqVRcA
mj7Ff2/B50mmB8aGfkQm82DpnqNXk9Vr1Y4hGzKrSOc1NGZItnpX2XJfqymEF7M9
9SW73jF6X2871FyiRvd5cO9TGlBieMNMlkenuxiyQNvIgocw1FX606EDji/aFp2e
KehjWw/2JCmBC1uUhaYqks4db7B8MSeVl8G3Dwx3lxnuz4xson/yscAxengZBR2r
clubyAoEa7+6sc2DhflLGlWfQpiOBDW4FFCW37H7KhVnJXFTomuiMBSSBc+njLMi
NDT7wAMCyMXtmZtx3zeWZpppqdc3doaGm3Bq6HDWEkiYaOe6TxA=
=ceCP
-----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/philmd/tags/mips-20210825' into staging

MIPS patches queue

- minor simplifications in PREF / JR opcodes
- merge 32-bit/64-bit Release6 decodetree definitions
- converted NEC Vr54xx extension opcodes to decodetree
- housekeeping in gen_helper() macros
- replace TARGET_WORDS_BIGENDIAN #ifdef'ry by cpu_is_bigendian()
- allow Loongson 3A1000 to use up to 48-bit VAddr

# gpg: Signature made Wed 25 Aug 2021 12:04:31 BST
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE

* remotes/philmd/tags/mips-20210825: (28 commits)
target/mips: Replace TARGET_WORDS_BIGENDIAN by cpu_is_bigendian()
target/mips: Store CP0_Config0 in DisasContext
target/mips: Replace GET_LMASK64() macro by get_lmask(64) function
target/mips: Replace GET_LMASK() macro by get_lmask(32) function
target/mips: Call cpu_is_bigendian & inline GET_OFFSET in ld/st helpers
target/mips: Define gen_helper() macros in translate.h
target/mips: Use tcg_constant_i32() in generate_exception_err()
target/mips: Inline gen_helper_0e0i()
target/mips: Inline gen_helper_1e1i() call in op_ld_INSN() macros
target/mips: Simplify gen_helper() macros by using tcg_constant_i32()
target/mips: Use tcg_constant_i32() in gen_helper_0e2i()
target/mips: Remove gen_helper_1e2i()
target/mips: Remove gen_helper_0e3i()
target/mips: Remove duplicated check_cp1_enabled() calls in Loongson EXT
target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr
target/mips: Document Loongson-3A CPU definitions
target/mips: Convert Vr54xx MSA* opcodes to decodetree
target/mips: Convert Vr54xx MUL* opcodes to decodetree
target/mips: Convert Vr54xx MACC* opcodes to decodetree
target/mips: Introduce decodetree structure for NEC Vr54xx extension
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

* Various updates for the documentation
-----BEGIN PGP SIGNATURE-----

iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmEmGw8RHHRodXRoQHJl
ZGhhdC5jb20ACgkQLtnXdP5wLbX3sA//dRQQdBdc+ZAPTdtG3I9qzOT2sgWe9Se/
dlrw9cvUkHzHxXr/U2/hf1TOo3UfwYhGBVy9E003CBYSCyi7Xv0bIpqaOqcU6yg5
9gtwDNOENMX5qC/EOua/8secbXTXCWs1d0hrzjeqNIL1/9ZeC6IUPkP23U9yIg2M
khEbdClX+/dim6h/+hrFv4ONVG0IVpYh3uip3sSNtZXCg1nl4QPZdbkCQax/Bqih
MM8Q9z0BuIngp7d9NE949pAIZ6P/QuZGsAcDTZa1utNZk3wGSV4aB85dC6wM/kGp
N2h4xapCl5aK8brw1Q2dNiPsAjYRQn0w8N1qbMRqXYLxq9ULxdpDHQdenhdlLP8+
TIiaDkIZld+MZW5RdHnGlo0MYd6YSg40Zx5E31nsx3HO9uv251/n5BGcRlA29+Rr
smAb7GOtqJnVzCeaSmjltZJmxksp+Q0YuwXuiqj6j5ZawMhU6T5/+cSY26V1cdsh
FYwrAM0Q8ohwiIzeFcaCJBEC7/SqU9bydT7D8ys68sQ2zyRVKFnvHIZrQeUdDLl2
zvyO4TGLde3iSdnzEVltToQCQET34QjVI5YyGlvAW6D4ygA/T8SZ6JOTUOLtUl8S
z6DUEwRBRJ4xIa3FJrsezjcbVSOTu6QBsSCRs73x22Z7OCeemy7ErrFyFQhUQMjb
0DuG0KBbiSo=
=P0bZ
-----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/thuth-gitlab/tags/pull-request-2021-08-25' into staging

* Various updates for the documentation

# gpg: Signature made Wed 25 Aug 2021 11:27:27 BST
# gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg: aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full]
# gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5

* remotes/thuth-gitlab/tags/pull-request-2021-08-25:
docs: make sphinx-build be quiet by default
docs: split the CI docs into two files
docs/about/removed-features: Move some CLI options to the right location
docs/about: Add the missing release record in the subject
docs/about: Unify the subject format
docs/about: Remove the duplicated doc

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

target/mips: Replace TARGET_WORDS_BIGENDIAN by cpu_is_bigendian()

Add the inlined cpu_is_bigendian() function in "translate.h".

Replace the TARGET_WORDS_BIGENDIAN #ifdef'ry by calls to
cpu_is_bigendian().

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210818164321.2474534-6-f4bug@amsat.org>

target/mips: Store CP0_Config0 in DisasContext

Most TCG helpers only have access to a DisasContext pointer,
not CPUMIPSState. Store a copy of CPUMIPSState::CP0_Config0
in DisasContext so we can access it from TCG helpers.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210818164321.2474534-5-f4bug@amsat.org>

target/mips: Replace GET_LMASK64() macro by get_lmask(64) function

The target endianess information is stored in the BigEndian
bit of the Config0 register in CP0.

Replace the GET_LMASK() macro by an inlined get_lmask() function,
passing CPUMIPSState and the word size as argument.

We can remove another use of the TARGET_WORDS_BIGENDIAN definition.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210818215517.2560994-4-f4bug@amsat.org>

target/mips: Replace GET_LMASK() macro by get_lmask(32) function

The target endianess information is stored in the BigEndian
bit of the Config0 register in CP0.

Replace the GET_LMASK() macro by an inlined get_lmask() function,
passing CPUMIPSState and the word size as argument.

We can remove one use of the TARGET_WORDS_BIGENDIAN definition.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210818215517.2560994-3-f4bug@amsat.org>

target/mips: Call cpu_is_bigendian & inline GET_OFFSET in ld/st helpers

The target endianess information is stored in the BigEndian
bit of the Config0 register in CP0.

As a first step, inline the GET_OFFSET() macro, calling
cpu_is_bigendian() to get the 'direction' of the offset.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210818215517.2560994-2-f4bug@amsat.org>

target/mips: Define gen_helper() macros in translate.h

To be able to split some code calling the gen_helper() macros
out of the huge translate.c, we need to define them in the
'translate.h' local header.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210816205107.2051495-9-f4bug@amsat.org>

target/mips: Use tcg_constant_i32() in generate_exception_err()

excp/err are temporaries input, so we can replace tcg_const_i32()
calls by tcg_constant_i32() equivalent.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210816205107.2051495-8-f4bug@amsat.org>

target/mips: Inline gen_helper_0e0i()

gen_helper_0e0i() is one-line long and is only used twice:
simply inline it.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210816205107.2051495-7-f4bug@amsat.org>

target/mips: Inline gen_helper_1e1i() call in op_ld_INSN() macros

gen_helper_1e1i() is one-line long and is used in one place:
simply inline it.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210816205107.2051495-6-f4bug@amsat.org>

target/mips: Simplify gen_helper() macros by using tcg_constant_i32()

In all call sites the last argument is always used as a
read-only value, so we can replace tcg_const_i32() temporary
by tcg_constant_i32().

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210816205107.2051495-5-f4bug@amsat.org>

target/mips: Use tcg_constant_i32() in gen_helper_0e2i()

$rt register is used read-only, so we can replace tcg_const_i32()
temporary by tcg_constant_i32().

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210816205107.2051495-4-f4bug@amsat.org>

target/mips: Remove gen_helper_1e2i()

gen_helper_1e2i() is unused since commit 33a07fa2db6
("target/mips: reimplement SC instruction emulation
and use cmpxchg"), remove it.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210816205107.2051495-3-f4bug@amsat.org>

target/mips: Remove gen_helper_0e3i()

gen_helper_0e3i() is unused since commit 895c2d04359
("target-mips: switch to AREG0 free mode"), remove it.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210816205107.2051495-2-f4bug@amsat.org>

target/mips: Remove duplicated check_cp1_enabled() calls in Loongson EXT

We already call check_cp1_enabled() earlier in the "pre-conditions"
checks for GSLWXC1 and GSLDXC1 in gen_loongson_lsdc2() prologue.
Remove the duplicated calls.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Huacai Chen <chenhuacai@loongson.cn>
Message-Id: <20210816001031.1720432-1-f4bug@amsat.org>

target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr

Per the manual '龙芯 GS264 处理器核用户手册' v1.0, chapter
1.1.5 SEGBITS: the 3A1000 (based on GS464 core) implements
48 virtual address bits in each 64-bit segment, not 40.

Fixes: af868995e1b ("target/mips: Add Loongson-3 CPU definition")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Huacai Chen <chenhuacai@loongson.cn>
Message-Id: <20210813110149.1432692-3-f4bug@amsat.org>

target/mips: Document Loongson-3A CPU definitions

Document the cores on which each Loongson-3A CPU is based (see
commit af868995e1b, "target/mips: Add Loongson-3 CPU definition").

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Huacai Chen <chenhuacai@loongson.cn>
Message-Id: <20210813110149.1432692-2-f4bug@amsat.org>

target/mips: Convert Vr54xx MSA* opcodes to decodetree

Convert the following Integer Multiply-Accumulate opcodes:

* MSAC Multiply, negate, accumulate, and move LO
* MSACHI Multiply, negate, accumulate, and move HI
* MSACHIU Unsigned multiply, negate, accumulate, and move HI
* MSACU Unsigned multiply, negate, accumulate, and move LO

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210808173018.90960-8-f4bug@amsat.org>

target/mips: Convert Vr54xx MUL* opcodes to decodetree

Convert the following Integer Multiply-Accumulate opcodes:

* MULHI Multiply and move HI
* MULHIU Unsigned multiply and move HI
* MULS Multiply, negate, and move LO
* MULSHI Multiply, negate, and move HI
* MULSHIU Unsigned multiply, negate, and move HI
* MULSU Unsigned multiply, negate, and move LO

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210808173018.90960-7-f4bug@amsat.org>

target/mips: Convert Vr54xx MACC* opcodes to decodetree

Convert the following Integer Multiply-Accumulate opcodes:

* MACC Multiply, accumulate, and move LO
* MACCHI Multiply, accumulate, and move HI
* MACCHIU Unsigned multiply, accumulate, and move HI
* MACCU Unsigned multiply, accumulate, and move LO

Since all opcodes are generated using the same pattern, we
add the gen_helper_mult_acc_t typedef and MULT_ACC() macro
to remove boilerplate code.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210808173018.90960-6-f4bug@amsat.org>

target/mips: Introduce decodetree structure for NEC Vr54xx extension

The decoder is called but doesn't decode anything. This will
ease reviewing the next commit.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210801235926.3178085-3-f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

target/mips: Extract NEC Vr54xx helpers to vr54xx_helper.c

Extract NEC Vr54xx helpers from op_helper.c to a new file:
'vr54xx_helper.c'.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201120210844.2625602-14-f4bug@amsat.org>

target/mips: Extract NEC Vr54xx helper definitions

Extract the NEC Vr54xx helper definitions to
'vendor-vr54xx_helper.h'.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201120210844.2625602-15-f4bug@amsat.org>

target/mips: Introduce generic TRANS() macro for decodetree helpers

Plain copy/paste of the TRANS() macro introduced in the PPC
commit f2aabda8ac9 ("target/ppc: Move D/DS/X-form integer
loads to decodetree") to the MIPS target.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210808173018.90960-2-f4bug@amsat.org>

target/mips: Rename 'rtype' as 'r'

We'll soon have more opcode and decoded arguments, and 'rtype'
is not very helpful. Naming it simply 'r' ease reviewing the
.decode files when we have many opcodes.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210801234202.3167676-5-f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

target/mips: Merge 32-bit/64-bit Release6 decodetree definitions

We don't need to maintain 2 sets of decodetree definitions.
Merge them into a single file.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210801234202.3167676-4-f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

target/mips: Decode vendor extensions before MIPS ISAs

In commit ffc672aa977 ("target/mips/tx79: Move MFHI1 / MFLO1
opcodes to decodetree") we misplaced the decoder call. Move
it to the correct place.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210801234202.3167676-3-f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>