Revision | 4eb471258bd0e331678bece4c894c477928b3b0b (tree) |
---|---|
Zeit | 2022-01-21 14:52:56 |
Autor | Yifei Jiang <jiangyifei@huaw...> |
Commiter | Alistair Francis |
target/riscv: Handle KVM_EXIT_RISCV_SBI exit
Use char-fe to handle console sbi call, which implement early
console io while apply 'earlycon=sbi' into kernel parameters.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220112081329.1835-9-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
@@ -38,6 +38,8 @@ | ||
38 | 38 | #include "qemu/log.h" |
39 | 39 | #include "hw/loader.h" |
40 | 40 | #include "kvm_riscv.h" |
41 | +#include "sbi_ecall_interface.h" | |
42 | +#include "chardev/char-fe.h" | |
41 | 43 | |
42 | 44 | static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, |
43 | 45 | uint64_t idx) |
@@ -367,9 +369,47 @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs) | ||
367 | 369 | return true; |
368 | 370 | } |
369 | 371 | |
372 | +static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run) | |
373 | +{ | |
374 | + int ret = 0; | |
375 | + unsigned char ch; | |
376 | + switch (run->riscv_sbi.extension_id) { | |
377 | + case SBI_EXT_0_1_CONSOLE_PUTCHAR: | |
378 | + ch = run->riscv_sbi.args[0]; | |
379 | + qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); | |
380 | + break; | |
381 | + case SBI_EXT_0_1_CONSOLE_GETCHAR: | |
382 | + ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch)); | |
383 | + if (ret == sizeof(ch)) { | |
384 | + run->riscv_sbi.args[0] = ch; | |
385 | + } else { | |
386 | + run->riscv_sbi.args[0] = -1; | |
387 | + } | |
388 | + break; | |
389 | + default: | |
390 | + qemu_log_mask(LOG_UNIMP, | |
391 | + "%s: un-handled SBI EXIT, specific reasons is %lu\n", | |
392 | + __func__, run->riscv_sbi.extension_id); | |
393 | + ret = -1; | |
394 | + break; | |
395 | + } | |
396 | + return ret; | |
397 | +} | |
398 | + | |
370 | 399 | int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) |
371 | 400 | { |
372 | - return 0; | |
401 | + int ret = 0; | |
402 | + switch (run->exit_reason) { | |
403 | + case KVM_EXIT_RISCV_SBI: | |
404 | + ret = kvm_riscv_handle_sbi(cs, run); | |
405 | + break; | |
406 | + default: | |
407 | + qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", | |
408 | + __func__, run->exit_reason); | |
409 | + ret = -1; | |
410 | + break; | |
411 | + } | |
412 | + return ret; | |
373 | 413 | } |
374 | 414 | |
375 | 415 | void kvm_riscv_reset_vcpu(RISCVCPU *cpu) |
@@ -0,0 +1,72 @@ | ||
1 | +/* | |
2 | + * SPDX-License-Identifier: BSD-2-Clause | |
3 | + * | |
4 | + * Copyright (c) 2019 Western Digital Corporation or its affiliates. | |
5 | + * | |
6 | + * Authors: | |
7 | + * Anup Patel <anup.patel@wdc.com> | |
8 | + */ | |
9 | + | |
10 | +#ifndef __SBI_ECALL_INTERFACE_H__ | |
11 | +#define __SBI_ECALL_INTERFACE_H__ | |
12 | + | |
13 | +/* clang-format off */ | |
14 | + | |
15 | +/* SBI Extension IDs */ | |
16 | +#define SBI_EXT_0_1_SET_TIMER 0x0 | |
17 | +#define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1 | |
18 | +#define SBI_EXT_0_1_CONSOLE_GETCHAR 0x2 | |
19 | +#define SBI_EXT_0_1_CLEAR_IPI 0x3 | |
20 | +#define SBI_EXT_0_1_SEND_IPI 0x4 | |
21 | +#define SBI_EXT_0_1_REMOTE_FENCE_I 0x5 | |
22 | +#define SBI_EXT_0_1_REMOTE_SFENCE_VMA 0x6 | |
23 | +#define SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID 0x7 | |
24 | +#define SBI_EXT_0_1_SHUTDOWN 0x8 | |
25 | +#define SBI_EXT_BASE 0x10 | |
26 | +#define SBI_EXT_TIME 0x54494D45 | |
27 | +#define SBI_EXT_IPI 0x735049 | |
28 | +#define SBI_EXT_RFENCE 0x52464E43 | |
29 | +#define SBI_EXT_HSM 0x48534D | |
30 | + | |
31 | +/* SBI function IDs for BASE extension*/ | |
32 | +#define SBI_EXT_BASE_GET_SPEC_VERSION 0x0 | |
33 | +#define SBI_EXT_BASE_GET_IMP_ID 0x1 | |
34 | +#define SBI_EXT_BASE_GET_IMP_VERSION 0x2 | |
35 | +#define SBI_EXT_BASE_PROBE_EXT 0x3 | |
36 | +#define SBI_EXT_BASE_GET_MVENDORID 0x4 | |
37 | +#define SBI_EXT_BASE_GET_MARCHID 0x5 | |
38 | +#define SBI_EXT_BASE_GET_MIMPID 0x6 | |
39 | + | |
40 | +/* SBI function IDs for TIME extension*/ | |
41 | +#define SBI_EXT_TIME_SET_TIMER 0x0 | |
42 | + | |
43 | +/* SBI function IDs for IPI extension*/ | |
44 | +#define SBI_EXT_IPI_SEND_IPI 0x0 | |
45 | + | |
46 | +/* SBI function IDs for RFENCE extension*/ | |
47 | +#define SBI_EXT_RFENCE_REMOTE_FENCE_I 0x0 | |
48 | +#define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA 0x1 | |
49 | +#define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID 0x2 | |
50 | +#define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA 0x3 | |
51 | +#define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID 0x4 | |
52 | +#define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA 0x5 | |
53 | +#define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID 0x6 | |
54 | + | |
55 | +/* SBI function IDs for HSM extension */ | |
56 | +#define SBI_EXT_HSM_HART_START 0x0 | |
57 | +#define SBI_EXT_HSM_HART_STOP 0x1 | |
58 | +#define SBI_EXT_HSM_HART_GET_STATUS 0x2 | |
59 | + | |
60 | +#define SBI_HSM_HART_STATUS_STARTED 0x0 | |
61 | +#define SBI_HSM_HART_STATUS_STOPPED 0x1 | |
62 | +#define SBI_HSM_HART_STATUS_START_PENDING 0x2 | |
63 | +#define SBI_HSM_HART_STATUS_STOP_PENDING 0x3 | |
64 | + | |
65 | +#define SBI_SPEC_VERSION_MAJOR_OFFSET 24 | |
66 | +#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f | |
67 | +#define SBI_SPEC_VERSION_MINOR_MASK 0xffffff | |
68 | +#define SBI_EXT_VENDOR_START 0x09000000 | |
69 | +#define SBI_EXT_VENDOR_END 0x09FFFFFF | |
70 | +/* clang-format on */ | |
71 | + | |
72 | +#endif |