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Motorola M6800 (6800) Exorciser / SWTPC emulator plus 6801 instruction set emulation


Commit MetaInfo

Revisionb083fd00ec7a7c29194c04145ada1fff893513eb (tree)
Zeit2020-11-22 22:37:11
AutorJoel Matthew Rees <joel.rees@gmai...>
CommiterJoel Matthew Rees

Log Message

6801 additions and command-line switch for asm6800.c -- not well tested,

Ändern Zusammenfassung

Diff

--- a/asm6800.c
+++ b/asm6800.c
@@ -193,205 +193,184 @@ enum {
193193 ACC1, /* Accumulator optional */
194194 ACCB, /* we need an A or a B: add 0x01 for B */
195195 /* #ifdef SIM6801 */
196- ACCD, /* LDD,STD,ADDD,SUBD */
196+ ACCD, /* LDD,STD,ADDD,SUBD JMR20201117 */
197197 /* #endif / * def SIM6801 */
198198 NONE /* No operand */
199199 };
200200
201-struct { char *insn; int opcode; int type; } table[] =
201+/* Include these in enum? */
202+#define STO 0x80 /* STore Only, no immediate, must be single bit JMR20201122 */
203+#define STunMASK( type ) ( (type) & 0x1F ) /* breathing room for more than 16 enums JMR20201122 */
204+
205+struct { char *insn; int opcode; int type; unsigned cpu; } table[] =
202206 {
203- { "lda", 0x86, ACC1 },
204- { "sta", 0x87, ACC1 },
205- { "ora", 0x8a, ACC1 },
206-
207- { "sub", 0x80, ACC },
208- { "cmp", 0x81, ACC },
209- { "sbc", 0x82, ACC },
210- { "and", 0x84, ACC },
211- { "bit", 0x85, ACC },
212- { "eor", 0x88, ACC },
213- { "adc", 0x89, ACC },
214- { "add", 0x8b, ACC },
215-
216- { "suba", 0x80, RM },
217- { "cmpa", 0x81, RM },
218- { "sbca", 0x82, RM },
219- { "anda", 0x84, RM },
220- { "bita", 0x85, RM },
221- { "ldaa", 0x86, RM },
222- { "staa", 0x87, RM },
223- { "eora", 0x88, RM },
224- { "adca", 0x89, RM },
225- { "oraa", 0x8a, RM },
226- { "adda", 0x8b, RM },
227-
228- { "subb", 0xc0, RM },
229- { "cmpb", 0xc1, RM },
230- { "sbcb", 0xc2, RM },
231- { "andb", 0xc4, RM },
232- { "bitb", 0xc5, RM },
233- { "ldb", 0xc6, RM },
234- { "stb", 0xc7, RM },
235- { "ldab", 0xc6, RM },
236- { "stab", 0xc7, RM },
237- { "eorb", 0xc8, RM },
238- { "adcb", 0xc9, RM },
239- { "orb", 0xca, RM },
240- { "orab", 0xca, RM },
241- { "addb", 0xcb, RM },
242-
243-#ifdef SIM6801
244- { "subd", 0x83, ACCD },
245- { "addd", 0xc3, ACCD },
246- { "ldd", 0xcc, ACCD },
247- { "std", 0xcd, ACCD },
248-#endif /* def SIM6801 */
249-
250- { "cpx", 0x8c, IDX },
251- { "bsr", 0x8d, REL },
252- { "lds", 0x8e, IDX },
253- { "sts", 0x8f, IDX },
254-#ifndef SIM6801
255- { "jsr", 0x8d, RMW },
256-#else /* def SIM6801 */
257- { "jsr", 0x8d, IDX },
258-#endif /* ndef SIM6801 */
259- { "ldx", 0xce, IDX },
260- { "stx", 0xcf, IDX },
261-
262- { "neg", 0x40, RMW },
263- { "com", 0x43, RMW },
264- { "lsr", 0x44, RMW },
265- { "ror", 0x46, RMW },
266- { "asr", 0x47, RMW },
267- { "asl", 0x48, RMW },
268-#ifdef SIM6801
269-/* { "lsl", 0x48, NONE }, / * alias */
270-#endif /* def SIM6801 */
271- { "rol", 0x49, RMW },
272- { "dec", 0x4a, RMW },
273- { "inc", 0x4c, RMW },
274- { "tst", 0x4d, RMW },
275- { "jmp", 0x4e, RMW },
276- { "clr", 0x4f, RMW },
277-
278- { "nega", 0x40, NONE },
279- { "coma", 0x43, NONE },
280- { "lsra", 0x44, NONE },
281- { "rora", 0x46, NONE },
282- { "asra", 0x47, NONE },
283- { "asla", 0x48, NONE },
284-#ifdef SIM6801
285-/* { "lsla", 0x48, NONE }, / * alias */
286-#endif /* def SIM6801 */
287- { "rola", 0x49, NONE },
288- { "deca", 0x4a, NONE },
289- { "inca", 0x4c, NONE },
290- { "tsta", 0x4d, NONE },
291- { "clra", 0x4f, NONE },
292-
293- { "negb", 0x50, NONE },
294- { "comb", 0x53, NONE },
295- { "lsrb", 0x54, NONE },
296- { "rorb", 0x56, NONE },
297- { "asrb", 0x57, NONE },
298- { "aslb", 0x58, NONE },
299-#ifdef SIM6801
300-/* { "lslb", 0x58, NONE }, / * alias */
301-#endif /* def SIM6801 */
302- { "rolb", 0x59, NONE },
303- { "decb", 0x5a, NONE },
304- { "incb", 0x5c, NONE },
305- { "tstb", 0x5d, NONE },
306- { "clrb", 0x5f, NONE },
307-
308- { "nop", 0x01, NONE },
309-#ifdef SIM6801
310- { "lsrd", 0x04, NONE },
311- { "asld", 0x05, NONE },
312-/* { "lsld", 0x05, NONE }, / * alias */
313-#endif /* def SIM6801 */
314- { "tap", 0x06, NONE },
315- { "tpa", 0x07, NONE },
316- { "inx", 0x08, NONE },
317- { "dex", 0x09, NONE },
318- { "clv", 0x0a, NONE },
319- { "sev", 0x0b, NONE },
320- { "clc", 0x0c, NONE },
321- { "sec", 0x0d, NONE },
322- { "cli", 0x0e, NONE },
323- { "sei", 0x0f, NONE },
324- { "sba", 0x10, NONE },
325- { "cba", 0x11, NONE },
326- { "tab", 0x16, NONE },
327- { "tba", 0x17, NONE },
328- { "daa", 0x19, NONE },
329- { "aba", 0x1b, NONE },
330-
331- { "bra", 0x20, REL },
332-#ifdef SIM6801
333- { "brn", 0x21, REL },
334-#endif /* def SIM6801 */
335- { "bhi", 0x22, REL },
336- { "bls", 0x23, REL },
337- { "bcc", 0x24, REL },
338-#ifdef SIM6801
339-/* { "bhs", 0x24, REL }, / * alias */
340-#endif /* def SIM6801 */
341- { "bcs", 0x25, REL },
342-#ifdef SIM6801
343-/* { "blo", 0x25, REL }, / * alias */
344-#endif /* def SIM6801 */
345- { "bne", 0x26, REL },
346- { "beq", 0x27, REL },
347- { "bvc", 0x28, REL },
348- { "bvs", 0x29, REL },
349- { "bpl", 0x2a, REL },
350- { "bmi", 0x2b, REL },
351- { "bge", 0x2c, REL },
352- { "blt", 0x2d, REL },
353- { "bgt", 0x2e, REL },
354- { "ble", 0x2f, REL },
355-
356- { "tsx", 0x30, NONE },
357- { "ins", 0x31, NONE },
358- { "pul", 0x32, ACCB },
359- { "pula", 0x32, NONE },
360- { "pulb", 0x33, NONE },
361- { "des", 0x34, NONE },
362- { "txs", 0x35, NONE },
363- { "psh", 0x36, ACCB },
364- { "psha", 0x36, NONE },
365- { "pshb", 0x37, NONE },
366-#ifdef SIM6801
367- { "pulx", 0x38, NONE },
368-#endif /* def SIM6801 */
369- { "rts", 0x39, NONE },
370-#ifdef SIM6801
371- { "abx", 0x3a, NONE },
372-#endif /* defSIM6801 */
373- { "rti", 0x3b, NONE },
374-#ifdef SIM6801
375- { "pshx", 0x3c, NONE },
376- { "mul", 0x3d, NONE },
377-#endif /* def SIM6801 */
378- { "wai", 0x3e, NONE },
379- { "swi", 0x3f, NONE },
380-
381- { "fcb", 0, FCB },
382- { "fcc", 0, FCB },
383- { "fdb", 0, FDB },
384- { "equ", 0, EQU },
385- { "rmb", 0, RMB },
386- { "org", 0, ORG },
387-
388- { "end", 0, IGN },
389- { "mon", 0, IGN },
390- { "opt", 0, IGN },
391- { "nam", 0, IGN },
392- { "ttl", 0, IGN },
393- { "spc", 0, IGN },
394- { "page", 0, IGN },
207+ { "lda", 0x86, ACC1, 0x6800 },
208+ { "sta", 0x87, ACC1|STO, 0x6800 },
209+ { "ora", 0x8a, ACC1, 0x6800 },
210+
211+ { "sub", 0x80, ACC, 0x6800 },
212+ { "cmp", 0x81, ACC, 0x6800 },
213+ { "sbc", 0x82, ACC, 0x6800 },
214+ { "and", 0x84, ACC, 0x6800 },
215+ { "bit", 0x85, ACC, 0x6800 },
216+ { "eor", 0x88, ACC, 0x6800 },
217+ { "adc", 0x89, ACC, 0x6800 },
218+ { "add", 0x8b, ACC, 0x6800 },
219+
220+ { "suba", 0x80, RM, 0x6800 },
221+ { "cmpa", 0x81, RM, 0x6800 },
222+ { "sbca", 0x82, RM, 0x6800 },
223+ { "anda", 0x84, RM, 0x6800 },
224+ { "bita", 0x85, RM, 0x6800 },
225+ { "ldaa", 0x86, RM, 0x6800 },
226+ { "staa", 0x87, RM|STO, 0x6800 },
227+ { "eora", 0x88, RM, 0x6800 },
228+ { "adca", 0x89, RM, 0x6800 },
229+ { "oraa", 0x8a, RM, 0x6800 },
230+ { "adda", 0x8b, RM, 0x6800 },
231+
232+ { "subb", 0xc0, RM, 0x6800 },
233+ { "cmpb", 0xc1, RM, 0x6800 },
234+ { "sbcb", 0xc2, RM, 0x6800 },
235+ { "andb", 0xc4, RM, 0x6800 },
236+ { "bitb", 0xc5, RM, 0x6800 },
237+ { "ldb", 0xc6, RM, 0x6800 },
238+ { "stb", 0xc7, RM|STO, 0x6800 },
239+ { "ldab", 0xc6, RM, 0x6800 },
240+ { "stab", 0xc7, RM|STO, 0x6800 },
241+ { "eorb", 0xc8, RM, 0x6800 },
242+ { "adcb", 0xc9, RM, 0x6800 },
243+ { "orb", 0xca, RM, 0x6800 },
244+ { "orab", 0xca, RM, 0x6800 },
245+ { "addb", 0xcb, RM, 0x6800 },
246+
247+ { "subd", 0x83, ACCD, 0x6801 },
248+ { "addd", 0xc3, ACCD, 0x6801 },
249+ { "ldd", 0xcc, ACCD, 0x6801 },
250+ { "std", 0xcd, ACCD|STO, 0x6801 },
251+
252+ { "cpx", 0x8c, IDX, 0x6800 },
253+ { "bsr", 0x8d, REL, 0x6800 },
254+ { "lds", 0x8e, IDX, 0x6800 },
255+ { "sts", 0x8f, IDX|STO, 0x6800 },
256+ { "jsr", 0x8d, RMW, 0x6800 },
257+ { "jsr", 0x8d, IDX|STO, 0x6801 }, /* Must come after 6800 jsr! */
258+ { "ldx", 0xce, IDX, 0x6800 },
259+ { "stx", 0xcf, IDX|STO, 0x6800 },
260+
261+ { "neg", 0x40, RMW, 0x6800 },
262+ { "com", 0x43, RMW, 0x6800 },
263+ { "lsr", 0x44, RMW, 0x6800 },
264+ { "ror", 0x46, RMW, 0x6800 },
265+ { "asr", 0x47, RMW, 0x6800 },
266+ { "asl", 0x48, RMW, 0x6800 },
267+ { "lsl", 0x48, RMW, 0x6800 }, /* alias */
268+ { "rol", 0x49, RMW, 0x6800 },
269+ { "dec", 0x4a, RMW, 0x6800 },
270+ { "inc", 0x4c, RMW, 0x6800 },
271+ { "tst", 0x4d, RMW, 0x6800 },
272+ { "jmp", 0x4e, RMW, 0x6800 },
273+ { "clr", 0x4f, RMW, 0x6800 },
274+
275+ { "nega", 0x40, NONE, 0x6800 },
276+ { "coma", 0x43, NONE, 0x6800 },
277+ { "lsra", 0x44, NONE, 0x6800 },
278+ { "rora", 0x46, NONE, 0x6800 },
279+ { "asra", 0x47, NONE, 0x6800 },
280+ { "asla", 0x48, NONE, 0x6800 },
281+ { "lsla", 0x48, NONE, 0x6800 }, /* alias */
282+ { "rola", 0x49, NONE, 0x6800 },
283+ { "deca", 0x4a, NONE, 0x6800 },
284+ { "inca", 0x4c, NONE, 0x6800 },
285+ { "tsta", 0x4d, NONE, 0x6800 },
286+ { "clra", 0x4f, NONE, 0x6800 },
287+
288+ { "negb", 0x50, NONE, 0x6800 },
289+ { "comb", 0x53, NONE, 0x6800 },
290+ { "lsrb", 0x54, NONE, 0x6800 },
291+ { "rorb", 0x56, NONE, 0x6800 },
292+ { "asrb", 0x57, NONE, 0x6800 },
293+ { "aslb", 0x58, NONE, 0x6800 },
294+ { "lslb", 0x58, NONE, 0x6800 }, /* alias */
295+ { "rolb", 0x59, NONE, 0x6800 },
296+ { "decb", 0x5a, NONE, 0x6800 },
297+ { "incb", 0x5c, NONE, 0x6800 },
298+ { "tstb", 0x5d, NONE, 0x6800 },
299+ { "clrb", 0x5f, NONE, 0x6800 },
300+
301+ { "nop", 0x01, NONE, 0x6800 },
302+ { "lsrd", 0x04, NONE, 0x6801 },
303+ { "asld", 0x05, NONE, 0x6801 },
304+ { "lsld", 0x05, NONE, 0x6801 }, /* alias */
305+ { "tap", 0x06, NONE, 0x6800 },
306+ { "tpa", 0x07, NONE, 0x6800 },
307+ { "inx", 0x08, NONE, 0x6800 },
308+ { "dex", 0x09, NONE, 0x6800 },
309+ { "clv", 0x0a, NONE, 0x6800 },
310+ { "sev", 0x0b, NONE, 0x6800 },
311+ { "clc", 0x0c, NONE, 0x6800 },
312+ { "sec", 0x0d, NONE, 0x6800 },
313+ { "cli", 0x0e, NONE, 0x6800 },
314+ { "sei", 0x0f, NONE, 0x6800 },
315+ { "sba", 0x10, NONE, 0x6800 },
316+ { "cba", 0x11, NONE, 0x6800 },
317+ { "tab", 0x16, NONE, 0x6800 },
318+ { "tba", 0x17, NONE, 0x6800 },
319+ { "daa", 0x19, NONE, 0x6800 },
320+ { "aba", 0x1b, NONE, 0x6800 },
321+
322+ { "bra", 0x20, REL, 0x6800 },
323+ { "brn", 0x21, REL, 0x6801 },
324+ { "bhi", 0x22, REL, 0x6800 },
325+ { "bls", 0x23, REL, 0x6800 },
326+ { "bcc", 0x24, REL, 0x6800 },
327+ { "bhs", 0x24, REL, 0x6800 }, /* alias */
328+ { "bcs", 0x25, REL, 0x6800 },
329+ { "blo", 0x25, REL, 0x6800 }, /* alias */
330+ { "bne", 0x26, REL, 0x6800 },
331+ { "beq", 0x27, REL, 0x6800 },
332+ { "bvc", 0x28, REL, 0x6800 },
333+ { "bvs", 0x29, REL, 0x6800 },
334+ { "bpl", 0x2a, REL, 0x6800 },
335+ { "bmi", 0x2b, REL, 0x6800 },
336+ { "bge", 0x2c, REL, 0x6800 },
337+ { "blt", 0x2d, REL, 0x6800 },
338+ { "bgt", 0x2e, REL, 0x6800 },
339+ { "ble", 0x2f, REL, 0x6800 },
340+
341+ { "tsx", 0x30, NONE, 0x6800 },
342+ { "ins", 0x31, NONE, 0x6800 },
343+ { "pul", 0x32, ACCB, 0x6800 },
344+ { "pula", 0x32, NONE, 0x6800 },
345+ { "pulb", 0x33, NONE, 0x6800 },
346+ { "des", 0x34, NONE, 0x6800 },
347+ { "txs", 0x35, NONE, 0x6800 },
348+ { "psh", 0x36, ACCB, 0x6800 },
349+ { "psha", 0x36, NONE, 0x6800 },
350+ { "pshb", 0x37, NONE, 0x6800 },
351+ { "pulx", 0x38, NONE, 0x6801 },
352+ { "rts", 0x39, NONE, 0x6800 },
353+ { "abx", 0x3a, NONE, 0x6801 },
354+ { "rti", 0x3b, NONE, 0x6800 },
355+ { "pshx", 0x3c, NONE, 0x6801 },
356+ { "mul", 0x3d, NONE, 0x6801 },
357+ { "wai", 0x3e, NONE, 0x6800 },
358+ { "swi", 0x3f, NONE, 0x6800 },
359+
360+ { "fcb", 0, FCB, 0x6800 },
361+ { "fcc", 0, FCB, 0x6800 },
362+ { "fdb", 0, FDB, 0x6800 },
363+ { "equ", 0, EQU, 0x6800 },
364+ { "rmb", 0, RMB, 0x6800 },
365+ { "org", 0, ORG, 0x6800 },
366+
367+ { "end", 0, IGN, 0x6800 },
368+ { "mon", 0, IGN, 0x6800 },
369+ { "opt", 0, IGN, 0x6800 },
370+ { "nam", 0, IGN, 0x6800 },
371+ { "ttl", 0, IGN, 0x6800 },
372+ { "spc", 0, IGN, 0x6800 },
373+ { "page", 0, IGN, 0x6800 },
395374
396375 { 0, 0, 0 }
397376 };
@@ -443,6 +422,7 @@ unsigned assemble(unsigned char *mem, unsigned addr, char *buf)
443422 int opcode = -1;
444423 int operand;
445424 int type;
425+ int store_only = 0; /* JMR 20201122 */
446426 char *p;
447427 int c;
448428 int x;
@@ -474,9 +454,10 @@ unsigned assemble(unsigned char *mem, unsigned addr, char *buf)
474454
475455 /* Lookup instruction */
476456 for (x = 0; table[x].insn; ++x)
477- if (!jstricmp(table[x].insn, str)) {
457+ if (!jstricmp(table[x].insn, str) && table[x].cpu <= cputype) { /* JMR20201122 */
478458 opcode = table[x].opcode;
479- type = table[x].type;
459+ type = STunMASK( table[x].type );
460+ store_only = table[x].type & STO;
480461 break;
481462 }
482463
@@ -572,7 +553,7 @@ unsigned assemble(unsigned char *mem, unsigned addr, char *buf)
572553 goto done;
573554 } else {
574555 norm:
575- if (*buf == '#') {
556+ if (*buf == '#' && type != RMW && !store_only) { /* JMR20201122 */
576557 ++buf;
577558 if (!parse_val(&buf, &operand, &sy, addr)) {
578559 printf("Missing number or label after #\n");
@@ -585,11 +566,7 @@ unsigned assemble(unsigned char *mem, unsigned addr, char *buf)
585566 add_fixup(sy, addr, FIXUP_DIR, operand);
586567 mem[addr++] = operand;
587568 goto done;
588-#ifndef SIM6801
589- } else if (type == IDX) {
590-#else /* def SIM6801 */
591- } else if (type == IDX || type == ACCD) {
592-#endif /* ndef SIM6801 */
569+ } else if (type == IDX || (cputype >= SIM6801 && type == ACCD)) {
593570 /* 16-bit immediate */
594571 mem[addr++] = opcode;
595572 if (sy)
@@ -612,11 +589,8 @@ unsigned assemble(unsigned char *mem, unsigned addr, char *buf)
612589 if (buf[0] == ',' && (buf[1] == 'x' || buf[1] == 'X')) {
613590 ndx:
614591 /* We have an indexed operand */
615-#ifndef SIM6801
616- if (type == RM || type == IDX || type == RMW) {
617-#else /* def SIM6801 */
618- if (type == RM || type == IDX || type == ACCD || type == RMW) {
619-#endif /* ndef SIM6801 */
592+ if (type == RM || type == IDX || type == RMW
593+ || (cputype >= 0x6801 && type == ACCD)) {
620594 mem[addr++] = opcode + 0x20;;
621595 if (sy)
622596 add_fixup(sy, addr, FIXUP_DIR, operand);
@@ -628,19 +602,13 @@ unsigned assemble(unsigned char *mem, unsigned addr, char *buf)
628602 }
629603 } else {
630604 /* We have a direct address operand */
631-#ifndef SIM6801
632- if ((type == RM || type == IDX) && !sy && operand < 256) {
633-#else /* def SIM6801 */
634- if ((type == RM || type == IDX || type == ACCD) && !sy && operand < 256) {
635-#endif /* ndef SIM6801 */
605+ if ((type == RM || type == IDX || (cputype >= 0x6801 && type == ACCD))
606+ && !sy && operand < 256) {
636607 mem[addr++] = opcode + 0x10;
637608 mem[addr++] = operand;
638609 goto done;
639-#ifndef SIM6801
640- } else if (type == RM || type == IDX || type == RMW) {
641-#else /* def SIM6801 */
642- } else if (type == RM || type == IDX || type == ACCD || type == RMW) {
643-#endif /* ndef SIM6801 */
610+ } else if (type == RM || type == IDX || type == RMW
611+ || (cputype >= 0x6801 && type == ACCD)) {
644612 mem[addr++] = opcode + 0x30;
645613 if (sy)
646614 add_fixup(sy, addr, FIXUP_EXT, operand);
--- a/exorsim.c
+++ b/exorsim.c
@@ -21,7 +21,7 @@
2121
2222 #include "exorsim.h"
2323
24-unsigned cputype = SIM6801;
24+unsigned cputype = 0x6800; /* Set 0x6801 by command-line flags. */
2525
2626
2727