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hardware/intel/intel-driver


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Revision9540f1e194e0f18f72a9496899bf7d1323b923af (tree)
Zeit2016-01-15 10:21:52
AutorXiang, Haihao <haihao.xiang@inte...>
CommiterXiang, Haihao

Log Message

Merge remote-tracking branch 'fdo/master' into v1.6-branch

Conflicts:
configure.ac
src/gen9_mfd.c
src/gen9_mfd.h
src/i965_device_info.c
src/i965_drv_video.c
src/i965_drv_video.h
src/intel_media_common.c

Ändern Zusammenfassung

Diff

--- a/configure.ac
+++ b/configure.ac
@@ -1,8 +1,8 @@
11 # intel-driver package version number
22 m4_define([intel_driver_major_version], [1])
33 m4_define([intel_driver_minor_version], [6])
4-m4_define([intel_driver_micro_version], [2])
5-m4_define([intel_driver_pre_version], [0])
4+m4_define([intel_driver_micro_version], [3])
5+m4_define([intel_driver_pre_version], [1])
66 m4_define([intel_driver_version],
77 [intel_driver_major_version.intel_driver_minor_version.intel_driver_micro_version])
88 m4_if(intel_driver_pre_version, [0], [], [
--- a/src/gen75_picture_process.c
+++ b/src/gen75_picture_process.c
@@ -28,6 +28,7 @@
2828 #include <stdio.h>
2929 #include <stdlib.h>
3030 #include <assert.h>
31+#include <string.h>
3132
3233 #include "intel_batchbuffer.h"
3334 #include "intel_driver.h"
@@ -123,6 +124,15 @@ gen75_proc_picture(VADriverContextP ctx,
123124 (VAProcPipelineParameterBuffer *)proc_st->pipeline_param->buffer;
124125 struct object_surface *obj_dst_surf = NULL;
125126 struct object_surface *obj_src_surf = NULL;
127+
128+ VAProcPipelineParameterBuffer pipeline_param2;
129+ struct object_surface *stage1_dst_surf = NULL;
130+ struct object_surface *stage2_dst_surf = NULL;
131+ VARectangle src_rect, dst_rect;
132+ VASurfaceID tmp_surfaces[2];
133+ VASurfaceID out_surface_id1 = VA_INVALID_ID, out_surface_id2 = VA_INVALID_ID;
134+ int num_tmp_surfaces = 0;
135+
126136 VAStatus status;
127137
128138 proc_ctx->pipeline_param = pipeline_param;
@@ -168,69 +178,221 @@ gen75_proc_picture(VADriverContextP ctx,
168178 proc_ctx->surface_pipeline_input_object = obj_src_surf;
169179 assert(pipeline_param->num_filters <= 4);
170180
181+ int vpp_stage1 = 0, vpp_stage2 = 1, vpp_stage3 = 0;
182+
183+ if (pipeline_param->surface_region) {
184+ src_rect.x = pipeline_param->surface_region->x;
185+ src_rect.y = pipeline_param->surface_region->y;
186+ src_rect.width = pipeline_param->surface_region->width;
187+ src_rect.height = pipeline_param->surface_region->height;
188+ } else {
189+ src_rect.x = 0;
190+ src_rect.y = 0;
191+ src_rect.width = obj_src_surf->orig_width;
192+ src_rect.height = obj_src_surf->orig_height;
193+ }
194+
195+ if (pipeline_param->output_region) {
196+ dst_rect.x = pipeline_param->output_region->x;
197+ dst_rect.y = pipeline_param->output_region->y;
198+ dst_rect.width = pipeline_param->output_region->width;
199+ dst_rect.height = pipeline_param->output_region->height;
200+ } else {
201+ dst_rect.x = 0;
202+ dst_rect.y = 0;
203+ dst_rect.width = obj_dst_surf->orig_width;
204+ dst_rect.height = obj_dst_surf->orig_height;
205+ }
206+
207+ if(obj_src_surf->fourcc == VA_FOURCC_P010) {
208+ vpp_stage1 = 1;
209+ vpp_stage2 = 0;
210+ vpp_stage3 = 0;
211+ if(pipeline_param->num_filters == 0 || pipeline_param->filters == NULL) {
212+ if(src_rect.x != dst_rect.x ||
213+ src_rect.y != dst_rect.y ||
214+ src_rect.width != dst_rect.width ||
215+ src_rect.height != dst_rect.height)
216+ vpp_stage2 = 1;
217+
218+ if(obj_dst_surf->fourcc != VA_FOURCC_NV12 &&
219+ obj_dst_surf->fourcc != VA_FOURCC_P010)
220+ vpp_stage2 = 1;
221+ }
222+ else
223+ vpp_stage2 = 1;
224+
225+ if(vpp_stage2 == 1) {
226+ if(obj_dst_surf->fourcc == VA_FOURCC_P010)
227+ vpp_stage3 = 1;
228+ }
229+ }
230+ else if(obj_dst_surf->fourcc == VA_FOURCC_P010) {
231+ vpp_stage2 = 1;
232+ vpp_stage3 = 1;
233+
234+ if((obj_src_surf->fourcc == VA_FOURCC_NV12) &&
235+ (pipeline_param->num_filters == 0 || pipeline_param->filters == NULL)) {
236+ if((src_rect.x == dst_rect.x) &&
237+ (src_rect.y == dst_rect.y) &&
238+ (src_rect.width == dst_rect.width) &&
239+ (src_rect.height == dst_rect.height))
240+ vpp_stage2 = 0;
241+ }
242+ }
243+
244+ if(vpp_stage1 == 1){
245+ memset((void *)&pipeline_param2, 0, sizeof(pipeline_param2));
246+ pipeline_param2.surface = pipeline_param->surface;
247+ pipeline_param2.surface_region = &src_rect;
248+ pipeline_param2.output_region = &src_rect;
249+ pipeline_param2.filter_flags = 0;
250+ pipeline_param2.num_filters = 0;
251+
252+ proc_ctx->pipeline_param = &pipeline_param2;
253+
254+ if(vpp_stage2 == 1) {
255+ status = i965_CreateSurfaces(ctx,
256+ obj_src_surf->orig_width,
257+ obj_src_surf->orig_height,
258+ VA_RT_FORMAT_YUV420,
259+ 1,
260+ &out_surface_id1);
261+ assert(status == VA_STATUS_SUCCESS);
262+ tmp_surfaces[num_tmp_surfaces++] = out_surface_id1;
263+ stage1_dst_surf = SURFACE(out_surface_id1);
264+ assert(stage1_dst_surf);
265+ i965_check_alloc_surface_bo(ctx, stage1_dst_surf, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
266+
267+ proc_ctx->surface_render_output_object = stage1_dst_surf;
268+ }
269+
270+ gen75_vpp_vebox(ctx, proc_ctx);
271+ }
272+
273+ if((vpp_stage3 == 1) && (vpp_stage2 == 1)) {
274+ status = i965_CreateSurfaces(ctx,
275+ obj_dst_surf->orig_width,
276+ obj_dst_surf->orig_height,
277+ VA_RT_FORMAT_YUV420,
278+ 1,
279+ &out_surface_id2);
280+ assert(status == VA_STATUS_SUCCESS);
281+ tmp_surfaces[num_tmp_surfaces++] = out_surface_id2;
282+ stage2_dst_surf = SURFACE(out_surface_id2);
283+ assert(stage2_dst_surf);
284+ i965_check_alloc_surface_bo(ctx, stage2_dst_surf, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
285+ }
286+
171287 VABufferID *filter_id = (VABufferID*) pipeline_param->filters;
172-
173- if(pipeline_param->num_filters == 0 || pipeline_param->filters == NULL ){
174- /* implicity surface format coversion and scaling */
175- gen75_vpp_fmt_cvt(ctx, profile, codec_state, hw_context);
176- }else if(pipeline_param->num_filters == 1) {
177- struct object_buffer * obj_buf = BUFFER((*filter_id) + 0);
178-
179- assert(obj_buf && obj_buf->buffer_store && obj_buf->buffer_store->buffer);
180-
181- if (!obj_buf ||
182- !obj_buf->buffer_store ||
183- !obj_buf->buffer_store->buffer) {
184- status = VA_STATUS_ERROR_INVALID_FILTER_CHAIN;
185- goto error;
186- }
187-
188- VAProcFilterParameterBuffer* filter =
189- (VAProcFilterParameterBuffer*)obj_buf-> buffer_store->buffer;
190-
191- if (filter->type == VAProcFilterNoiseReduction ||
192- filter->type == VAProcFilterDeinterlacing ||
193- filter->type == VAProcFilterSkinToneEnhancement ||
194- filter->type == VAProcFilterColorBalance){
195- gen75_vpp_vebox(ctx, proc_ctx);
196- }else if(filter->type == VAProcFilterSharpening){
197- if (obj_src_surf->fourcc != VA_FOURCC_NV12 ||
198- obj_dst_surf->fourcc != VA_FOURCC_NV12) {
199- status = VA_STATUS_ERROR_UNIMPLEMENTED;
288+
289+ if(vpp_stage2 == 1) {
290+ if(stage1_dst_surf != NULL) {
291+ proc_ctx->surface_pipeline_input_object = stage1_dst_surf;
292+ proc_ctx->surface_render_output_object = obj_dst_surf;
293+
294+ pipeline_param->surface = out_surface_id1;
295+ }
296+
297+ if(stage2_dst_surf != NULL) {
298+ proc_ctx->surface_render_output_object = stage2_dst_surf;
299+
300+ proc_st->current_render_target = out_surface_id2;
301+ }
302+
303+ proc_ctx->pipeline_param = pipeline_param;
304+
305+ if(pipeline_param->num_filters == 0 || pipeline_param->filters == NULL ){
306+ /* implicity surface format coversion and scaling */
307+
308+ gen75_vpp_fmt_cvt(ctx, profile, codec_state, hw_context);
309+ }else if(pipeline_param->num_filters == 1) {
310+ struct object_buffer * obj_buf = BUFFER((*filter_id) + 0);
311+
312+ assert(obj_buf && obj_buf->buffer_store && obj_buf->buffer_store->buffer);
313+
314+ if (!obj_buf ||
315+ !obj_buf->buffer_store ||
316+ !obj_buf->buffer_store->buffer) {
317+ status = VA_STATUS_ERROR_INVALID_FILTER_CHAIN;
200318 goto error;
201319 }
202320
203- gen75_vpp_gpe(ctx, proc_ctx);
204- }
205- }else if (pipeline_param->num_filters >= 2) {
206- unsigned int i = 0;
207- for (i = 0; i < pipeline_param->num_filters; i++){
208- struct object_buffer * obj_buf = BUFFER(pipeline_param->filters[i]);
209-
210- if (!obj_buf ||
211- !obj_buf->buffer_store ||
212- !obj_buf->buffer_store->buffer) {
213- status = VA_STATUS_ERROR_INVALID_FILTER_CHAIN;
214- goto error;
321+ VAProcFilterParameterBuffer* filter =
322+ (VAProcFilterParameterBuffer*)obj_buf-> buffer_store->buffer;
323+
324+ if (filter->type == VAProcFilterNoiseReduction ||
325+ filter->type == VAProcFilterDeinterlacing ||
326+ filter->type == VAProcFilterSkinToneEnhancement ||
327+ filter->type == VAProcFilterColorBalance){
328+ gen75_vpp_vebox(ctx, proc_ctx);
329+ }else if(filter->type == VAProcFilterSharpening){
330+ if (proc_ctx->surface_pipeline_input_object->fourcc != VA_FOURCC_NV12 ||
331+ proc_ctx->surface_render_output_object->fourcc != VA_FOURCC_NV12) {
332+ status = VA_STATUS_ERROR_UNIMPLEMENTED;
333+ goto error;
334+ }
335+
336+ gen75_vpp_gpe(ctx, proc_ctx);
337+ }
338+ }else if (pipeline_param->num_filters >= 2) {
339+ unsigned int i = 0;
340+ for (i = 0; i < pipeline_param->num_filters; i++){
341+ struct object_buffer * obj_buf = BUFFER(pipeline_param->filters[i]);
342+
343+ if (!obj_buf ||
344+ !obj_buf->buffer_store ||
345+ !obj_buf->buffer_store->buffer) {
346+ status = VA_STATUS_ERROR_INVALID_FILTER_CHAIN;
347+ goto error;
348+ }
349+
350+ VAProcFilterParameterBuffer* filter =
351+ (VAProcFilterParameterBuffer*)obj_buf-> buffer_store->buffer;
352+
353+ if (filter->type != VAProcFilterNoiseReduction &&
354+ filter->type != VAProcFilterDeinterlacing &&
355+ filter->type != VAProcFilterSkinToneEnhancement &&
356+ filter->type != VAProcFilterColorBalance) {
357+ fprintf(stderr, "Do not support multiply filters outside vebox pipeline \n");
358+ assert(0);
359+ }
215360 }
361+ gen75_vpp_vebox(ctx, proc_ctx);
362+ }
363+ }
216364
217- VAProcFilterParameterBuffer* filter =
218- (VAProcFilterParameterBuffer*)obj_buf-> buffer_store->buffer;
365+ if(vpp_stage3 == 1)
366+ {
367+ if(vpp_stage2 == 1) {
368+ memset(&pipeline_param2, 0, sizeof(pipeline_param2));
369+ pipeline_param2.surface = out_surface_id2;
370+ pipeline_param2.surface_region = &dst_rect;
371+ pipeline_param2.output_region = &dst_rect;
372+ pipeline_param2.filter_flags = 0;
373+ pipeline_param2.num_filters = 0;
374+
375+ proc_ctx->pipeline_param = &pipeline_param2;
376+ proc_ctx->surface_pipeline_input_object = proc_ctx->surface_render_output_object;
377+ proc_ctx->surface_render_output_object = obj_dst_surf;
378+ }
379+
380+ gen75_vpp_vebox(ctx, proc_ctx);
381+ }
219382
220- if (filter->type != VAProcFilterNoiseReduction &&
221- filter->type != VAProcFilterDeinterlacing &&
222- filter->type != VAProcFilterSkinToneEnhancement &&
223- filter->type != VAProcFilterColorBalance) {
224- fprintf(stderr, "Do not support multiply filters outside vebox pipeline \n");
225- assert(0);
226- }
227- }
228- gen75_vpp_vebox(ctx, proc_ctx);
229- }
383+ if (num_tmp_surfaces)
384+ i965_DestroySurfaces(ctx,
385+ tmp_surfaces,
386+ num_tmp_surfaces);
230387
231388 return VA_STATUS_SUCCESS;
232389
233390 error:
391+ if (num_tmp_surfaces)
392+ i965_DestroySurfaces(ctx,
393+ tmp_surfaces,
394+ num_tmp_surfaces);
395+
234396 return status;
235397 }
236398
--- a/src/gen75_vpp_vebox.c
+++ b/src/gen75_vpp_vebox.c
@@ -1408,7 +1408,9 @@ int hsw_veb_pre_format_convert(VADriverContextP ctx,
14081408
14091409 } else if(obj_surf_input->fourcc == VA_FOURCC_AYUV ||
14101410 obj_surf_input->fourcc == VA_FOURCC_YUY2 ||
1411- obj_surf_input->fourcc == VA_FOURCC_NV12){
1411+ obj_surf_input->fourcc == VA_FOURCC_NV12 ||
1412+ obj_surf_input->fourcc == VA_FOURCC_P010){
1413+
14121414 // nothing to do here
14131415 } else {
14141416 /* not support other format as input */
@@ -1447,7 +1449,9 @@ int hsw_veb_pre_format_convert(VADriverContextP ctx,
14471449 proc_ctx->format_convert_flags |= POST_FORMAT_CONVERT;
14481450 } else if(obj_surf_output->fourcc == VA_FOURCC_AYUV ||
14491451 obj_surf_output->fourcc == VA_FOURCC_YUY2 ||
1450- obj_surf_output->fourcc == VA_FOURCC_NV12){
1452+ obj_surf_input->fourcc == VA_FOURCC_NV12 ||
1453+ obj_surf_input->fourcc == VA_FOURCC_P010){
1454+
14511455 /* Nothing to do here */
14521456 } else {
14531457 /* not support other format as input */
@@ -1602,6 +1606,11 @@ gen75_vebox_init_filter_params(VADriverContextP ctx,
16021606 proc_ctx->is_first_frame = 0;
16031607 proc_ctx->is_second_field = 0;
16041608
1609+ if(!proc_ctx->is_di_enabled && !proc_ctx->is_dn_enabled) {
1610+ // MUST enable IECP if all DI&DN are disabled
1611+ proc_ctx->is_iecp_enabled = 1;
1612+ }
1613+
16051614 /* Check whether we are deinterlacing the second field */
16061615 if (proc_ctx->is_di_enabled) {
16071616 const VAProcFilterParameterBufferDeinterlacing * const deint_params =
@@ -2290,7 +2299,8 @@ void skl_veb_surface_state(VADriverContextP ctx, struct intel_vebox_context *pro
22902299 assert(obj_surf->fourcc == VA_FOURCC_NV12 ||
22912300 obj_surf->fourcc == VA_FOURCC_YUY2 ||
22922301 obj_surf->fourcc == VA_FOURCC_AYUV ||
2293- obj_surf->fourcc == VA_FOURCC_RGBA);
2302+ obj_surf->fourcc == VA_FOURCC_RGBA ||
2303+ obj_surf->fourcc == VA_FOURCC_P010);
22942304
22952305 if (obj_surf->fourcc == VA_FOURCC_NV12) {
22962306 surface_format = PLANAR_420_8;
@@ -2312,6 +2322,11 @@ void skl_veb_surface_state(VADriverContextP ctx, struct intel_vebox_context *pro
23122322 surface_pitch = obj_surf->width * 4;
23132323 is_uv_interleaved = 0;
23142324 half_pitch_chroma = 0;
2325+ } else if (obj_surf->fourcc == VA_FOURCC_P010) {
2326+ surface_format = PLANAR_420_16;
2327+ surface_pitch = obj_surf->width;
2328+ is_uv_interleaved = 1;
2329+ half_pitch_chroma = 0;
23152330 }
23162331
23172332 derived_pitch = surface_pitch;
--- a/src/gen8_post_processing.c
+++ b/src/gen8_post_processing.c
@@ -42,6 +42,8 @@
4242 #include "i965_yuv_coefs.h"
4343 #include "intel_media.h"
4444
45+#include "gen75_picture_process.h"
46+
4547 #define SURFACE_STATE_PADDED_SIZE SURFACE_STATE_PADDED_SIZE_GEN8
4648
4749 #define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index)
@@ -1460,6 +1462,11 @@ static void
14601462 gen8_post_processing_context_finalize(VADriverContextP ctx,
14611463 struct i965_post_processing_context *pp_context)
14621464 {
1465+ if(pp_context->vebox_proc_ctx){
1466+ gen75_vebox_context_destroy(ctx,pp_context->vebox_proc_ctx);
1467+ pp_context->vebox_proc_ctx = NULL;
1468+ }
1469+
14631470 dri_bo_unreference(pp_context->surface_state_binding_table.bo);
14641471 pp_context->surface_state_binding_table.bo = NULL;
14651472
--- a/src/gen9_mfd.c
+++ b/src/gen9_mfd.c
@@ -982,23 +982,44 @@ out:
982982 #define VP9_PROB_BUFFER_RESTORED_SECNE_2 2
983983 #define VP9_PROB_BUFFER_RESTORED_SECNE_MAX (VP9_PROB_BUFFER_RESTORED_SECNE_2 + 1)
984984
985-static void vp9_update_segmentId_buffer(VADriverContextP ctx,
985+#define ALLOC_MV_BUFFER(gen_buffer, string, size,width,height) \
986+ do { \
987+ dri_bo_unreference(gen_buffer->bo); \
988+ gen_buffer->bo = dri_bo_alloc(i965->intel.bufmgr, \
989+ string, \
990+ size, \
991+ 0x1000); \
992+ assert(gen_buffer->bo); \
993+ gen_buffer->frame_width = width ; \
994+ gen_buffer->frame_height = height; \
995+ } while (0)
996+
997+static void
998+vp9_update_segmentId_buffer(VADriverContextP ctx,
986999 struct decode_state *decode_state,
987- struct gen9_hcpd_context *gen9_hcpd_context, uint8_t isScaling)
1000+ struct gen9_hcpd_context *gen9_hcpd_context)
9881001 {
1002+ struct i965_driver_data *i965 = i965_driver_data(ctx);
9891003 VADecPictureParameterBufferVP9 *pic_param;
9901004
1005+ int size = 0;
1006+ int is_scaling = 0;
9911007 assert(decode_state->pic_param && decode_state->pic_param->buffer);
9921008 pic_param = (VADecPictureParameterBufferVP9 *)decode_state->pic_param->buffer;
9931009
994- int size = 0;
1010+ size = gen9_hcpd_context->picture_width_in_ctbs * gen9_hcpd_context->picture_height_in_ctbs * 1 ;
1011+ size <<= 6;
1012+ if (gen9_hcpd_context->vp9_segment_id_buffer.bo == NULL || pic_param->frame_width > gen9_hcpd_context->last_frame.frame_width || pic_param->frame_height > gen9_hcpd_context->last_frame.frame_height)
1013+ {
1014+ ALLOC_GEN_BUFFER((&gen9_hcpd_context->vp9_segment_id_buffer), "vp9 segment id buffer", size);
1015+ }
1016+
1017+ is_scaling = (pic_param->frame_width != gen9_hcpd_context->last_frame.frame_width) || (pic_param->frame_height != gen9_hcpd_context->last_frame.frame_height);
9951018
9961019 if((pic_param->pic_fields.bits.frame_type == HCP_VP9_KEY_FRAME) ||
9971020 pic_param->pic_fields.bits.error_resilient_mode ||
998- pic_param->pic_fields.bits.intra_only || isScaling) {
1021+ pic_param->pic_fields.bits.intra_only || is_scaling) {
9991022
1000- size = (gen9_hcpd_context->picture_width_in_min_cb_minus1+2)*(gen9_hcpd_context->picture_height_in_min_cb_minus1 + 2) * 1;
1001- size<<=6;
10021023 //VP9 Segment ID buffer needs to be zero
10031024 dri_bo_map(gen9_hcpd_context->vp9_segment_id_buffer.bo,1);
10041025 memset((unsigned char *)gen9_hcpd_context->vp9_segment_id_buffer.bo->virtual,0, size);
@@ -1007,6 +1028,31 @@ static void vp9_update_segmentId_buffer(VADriverContextP ctx,
10071028 }
10081029
10091030 static void
1031+vp9_update_mv_temporal_buffer(VADriverContextP ctx,
1032+ struct decode_state *decode_state,
1033+ struct gen9_hcpd_context *gen9_hcpd_context)
1034+{
1035+ struct i965_driver_data *i965 = i965_driver_data(ctx);
1036+ VADecPictureParameterBufferVP9 *pic_param;
1037+ int size = 0;
1038+
1039+ assert(decode_state->pic_param && decode_state->pic_param->buffer);
1040+ pic_param = (VADecPictureParameterBufferVP9 *)decode_state->pic_param->buffer;
1041+
1042+ size = gen9_hcpd_context->picture_width_in_ctbs * gen9_hcpd_context->picture_height_in_ctbs * 9 ;
1043+ size <<= 6; //CL aligned
1044+ if (gen9_hcpd_context->vp9_mv_temporal_buffer_curr.bo == NULL || pic_param->frame_width > gen9_hcpd_context->vp9_mv_temporal_buffer_curr.frame_width || pic_param->frame_height > gen9_hcpd_context->vp9_mv_temporal_buffer_curr.frame_height)
1045+ {
1046+ ALLOC_MV_BUFFER((&gen9_hcpd_context->vp9_mv_temporal_buffer_curr), "vp9 curr mv temporal buffer", size,pic_param->frame_width,pic_param->frame_height);
1047+ }
1048+ if (gen9_hcpd_context->vp9_mv_temporal_buffer_last.bo == NULL)
1049+ {
1050+ ALLOC_MV_BUFFER((&gen9_hcpd_context->vp9_mv_temporal_buffer_last), "vp9 last mv temporal buffer", size,pic_param->frame_width,pic_param->frame_height);
1051+ }
1052+
1053+}
1054+
1055+static void
10101056 vp9_gen_default_probabilities(VADriverContextP ctx, struct gen9_hcpd_context *gen9_hcpd_context)
10111057 {
10121058 int i = 0;
@@ -1103,7 +1149,7 @@ vp9_update_probabilities(VADriverContextP ctx,
11031149 }
11041150 }else if(gen9_hcpd_context->last_frame.prob_buffer_saved_flag == VP9_PROB_BUFFER_SAVED_SECNE_2)
11051151 {
1106- if((pic_param->pic_fields.bits.frame_type == HCP_VP9_KEY_FRAME) ||pic_param->pic_fields.bits.intra_only|pic_param->pic_fields.bits.error_resilient_mode)
1152+ if((pic_param->pic_fields.bits.frame_type == HCP_VP9_KEY_FRAME) ||pic_param->pic_fields.bits.intra_only||pic_param->pic_fields.bits.error_resilient_mode)
11071153 {
11081154 temp_frame_ctx_id = 0;
11091155 }
@@ -1130,7 +1176,7 @@ vp9_update_probabilities(VADriverContextP ctx,
11301176 }
11311177 }
11321178 //first part buffer update: Case 1)Reset all 4 probablity buffers
1133- if((pic_param->pic_fields.bits.frame_type == HCP_VP9_KEY_FRAME) ||pic_param->pic_fields.bits.intra_only|pic_param->pic_fields.bits.error_resilient_mode)
1179+ if((pic_param->pic_fields.bits.frame_type == HCP_VP9_KEY_FRAME) ||pic_param->pic_fields.bits.intra_only||pic_param->pic_fields.bits.error_resilient_mode)
11341180 {
11351181 if((pic_param->pic_fields.bits.frame_type == HCP_VP9_KEY_FRAME) ||
11361182 (pic_param->pic_fields.bits.reset_frame_context == 3)||
@@ -1265,9 +1311,7 @@ gen9_hcpd_init_vp9_surface(VADriverContextP ctx,
12651311 struct object_surface *obj_surface,
12661312 struct gen9_hcpd_context *gen9_hcpd_context)
12671313 {
1268- struct i965_driver_data *i965 = i965_driver_data(ctx);
12691314 GenVP9Surface *gen9_vp9_surface;
1270- uint32_t size=0;
12711315
12721316 if (!obj_surface)
12731317 return;
@@ -1277,20 +1321,11 @@ gen9_hcpd_init_vp9_surface(VADriverContextP ctx,
12771321
12781322 if (!gen9_vp9_surface) {
12791323 gen9_vp9_surface = calloc(sizeof(GenVP9Surface), 1);
1324+ assert(gen9_vp9_surface);
12801325 gen9_vp9_surface->base.frame_store_id = -1;
12811326 obj_surface->private_data = gen9_vp9_surface;
12821327 }
12831328
1284- //Super block size in VP9 is 64x64, size in SBs
1285- size = gen9_hcpd_context->picture_width_in_ctbs * gen9_hcpd_context->picture_height_in_ctbs * 9 ;
1286- size<<=6; //CL aligned
1287-
1288- if (gen9_vp9_surface->motion_vector_temporal_bo == NULL) {
1289- gen9_vp9_surface->motion_vector_temporal_bo = dri_bo_alloc(i965->intel.bufmgr,
1290- "current motion vector temporal buffer",
1291- size,
1292- 0x1000);
1293- }
12941329 gen9_vp9_surface->frame_width = pic_param->frame_width;
12951330 gen9_vp9_surface->frame_height = pic_param->frame_height;
12961331
@@ -1373,10 +1408,6 @@ gen9_hcpd_vp9_decode_init(VADriverContextP ctx,
13731408 size<<=6;
13741409 ALLOC_GEN_BUFFER((&gen9_hcpd_context->vp9_probability_buffer), "vp9 probability buffer", size);
13751410
1376- size = (gen9_hcpd_context->picture_width_in_min_cb_minus1+2)*(gen9_hcpd_context->picture_height_in_min_cb_minus1 + 2) * 1;
1377- size<<=6;
1378- ALLOC_GEN_BUFFER((&gen9_hcpd_context->vp9_segment_id_buffer), "vp9 segment id buffer", size);
1379-
13801411 gen9_hcpd_context->first_inter_slice_collocated_ref_idx = 0;
13811412 gen9_hcpd_context->first_inter_slice_collocated_from_l0_flag = 0;
13821413 gen9_hcpd_context->first_inter_slice_valid = 0;
@@ -1450,7 +1481,6 @@ gen9_hcpd_vp9_pipe_buf_addr_state(VADriverContextP ctx,
14501481 {
14511482 struct intel_batchbuffer *batch = gen9_hcpd_context->base.batch;
14521483 struct object_surface *obj_surface;
1453- GenVP9Surface *gen9_vp9_surface;
14541484 int i=0;
14551485
14561486 BEGIN_BCS_BATCH(batch, 95);
@@ -1459,8 +1489,6 @@ gen9_hcpd_vp9_pipe_buf_addr_state(VADriverContextP ctx,
14591489
14601490 obj_surface = decode_state->render_object;
14611491 assert(obj_surface && obj_surface->bo);
1462- gen9_vp9_surface = obj_surface->private_data;
1463- assert(gen9_vp9_surface && gen9_vp9_surface->motion_vector_temporal_bo);
14641492
14651493 OUT_BUFFER_MA_TARGET(obj_surface->bo); /* DW 1..3 */
14661494 OUT_BUFFER_MA_TARGET(gen9_hcpd_context->deblocking_filter_line_buffer.bo);/* DW 4..6 */
@@ -1472,7 +1500,7 @@ gen9_hcpd_vp9_pipe_buf_addr_state(VADriverContextP ctx,
14721500 OUT_BUFFER_MA_TARGET(NULL); /* DW 22..24, ignore for VP9 */
14731501 OUT_BUFFER_MA_TARGET(NULL); /* DW 25..27, ignore for VP9 */
14741502 OUT_BUFFER_MA_TARGET(NULL); /* DW 28..30, ignore for VP9 */
1475- OUT_BUFFER_MA_TARGET(gen9_vp9_surface->motion_vector_temporal_bo); /* DW 31..33 */
1503+ OUT_BUFFER_MA_TARGET(gen9_hcpd_context->vp9_mv_temporal_buffer_curr.bo); /* DW 31..33 */
14761504
14771505 OUT_BUFFER_MA_TARGET(NULL); /* DW 34..36, reserved */
14781506
@@ -1502,7 +1530,7 @@ gen9_hcpd_vp9_pipe_buf_addr_state(VADriverContextP ctx,
15021530 /* DW 66..81 - for 8 Collocated motion vectors */
15031531 for (i = 0; i < 1; i++)
15041532 {
1505- OUT_BUFFER_NMA_REFERENCE(gen9_hcpd_context->last_frame.mv_temporal_buffer_bo);
1533+ OUT_BUFFER_NMA_REFERENCE(gen9_hcpd_context->vp9_mv_temporal_buffer_last.bo);
15061534 }
15071535 for (; i < ARRAY_ELEMS(gen9_hcpd_context->reference_surfaces); i++)
15081536 {
@@ -1517,7 +1545,6 @@ gen9_hcpd_vp9_pipe_buf_addr_state(VADriverContextP ctx,
15171545 OUT_BUFFER_MA_TARGET(gen9_hcpd_context->hvd_tile_rowstore_buffer.bo);/* DW 92..94, VP9 HVD Tile Rowstore buffer */
15181546
15191547 ADVANCE_BCS_BATCH(batch);
1520- gen9_hcpd_context->last_frame.mv_temporal_buffer_bo = gen9_vp9_surface->motion_vector_temporal_bo;
15211548 }
15221549
15231550 static inline int
@@ -1718,16 +1745,25 @@ gen9_hcpd_vp9_segment_state(VADriverContextP ctx,
17181745 seg_param->segment_flags.fields.segment_reference_enabled << 3 |
17191746 seg_param->segment_flags.fields.segment_reference << 1 |
17201747 seg_param->segment_flags.fields.segment_reference_skipped <<0 ); /* DW 2 */
1721- OUT_BCS_BATCH(batch,
1722- seg_param->filter_level[1][1] << 24 | //FilterLevelRef1Mode1
1723- seg_param->filter_level[1][0] << 16 | //FilterLevelRef1Mode0
1724- seg_param->filter_level[0][1] << 8 | //FilterLevelRef0Mode1
1725- seg_param->filter_level[0][0] << 0 ); //FilterLevelRef0Mode0 /* DW 3 */
1726- OUT_BCS_BATCH(batch,
1727- seg_param->filter_level[3][1] << 24 | //FilterLevelRef3Mode1
1728- seg_param->filter_level[3][0] << 16 | //FilterLevelRef3Mode0
1729- seg_param->filter_level[2][1] << 8 | //FilterLevelRef2Mode1
1730- seg_param->filter_level[2][0] << 0 ); //FilterLevelRef2Mode0 /* DW 4 */
1748+ if(pic_param->filter_level)
1749+ {
1750+ OUT_BCS_BATCH(batch,
1751+ seg_param->filter_level[1][1] << 24 | //FilterLevelRef1Mode1
1752+ seg_param->filter_level[1][0] << 16 | //FilterLevelRef1Mode0
1753+ seg_param->filter_level[0][1] << 8 | //FilterLevelRef0Mode1
1754+ seg_param->filter_level[0][0] << 0 ); //FilterLevelRef0Mode0 /* DW 3 */
1755+ OUT_BCS_BATCH(batch,
1756+ seg_param->filter_level[3][1] << 24 | //FilterLevelRef3Mode1
1757+ seg_param->filter_level[3][0] << 16 | //FilterLevelRef3Mode0
1758+ seg_param->filter_level[2][1] << 8 | //FilterLevelRef2Mode1
1759+ seg_param->filter_level[2][0] << 0 ); //FilterLevelRef2Mode0 /* DW 4 */
1760+ }else
1761+ {
1762+ OUT_BCS_BATCH(batch,
1763+ 0 ); /* DW 3 */
1764+ OUT_BCS_BATCH(batch,
1765+ 0 ); /* DW 4 */
1766+ }
17311767 OUT_BCS_BATCH(batch,
17321768 seg_param->luma_ac_quant_scale << 16 |
17331769 seg_param->luma_dc_quant_scale << 0 ); /* DW 5 */
@@ -1765,39 +1801,35 @@ gen9_hcpd_vp9_decode_picture(VADriverContextP ctx,
17651801 struct decode_state *decode_state,
17661802 struct gen9_hcpd_context *gen9_hcpd_context)
17671803 {
1768- VAStatus vaStatus;
1804+ VAStatus vaStatus = VA_STATUS_SUCCESS;
17691805 struct i965_driver_data *i965 = i965_driver_data(ctx);
17701806 struct intel_batchbuffer *batch = gen9_hcpd_context->base.batch;
17711807 VADecPictureParameterBufferVP9 *pic_param;
17721808 VASliceParameterBufferVP9 *slice_param;
17731809 dri_bo *slice_data_bo;
1774- int i = 0, num_segments=0, isScaling=0;
1775- struct object_surface *obj_surface;
1776- GenVP9Surface *gen9_vp9_surface;
1777- vaStatus = gen9_hcpd_vp9_decode_init(ctx, decode_state, gen9_hcpd_context);
1778-
1779- if (vaStatus != VA_STATUS_SUCCESS)
1780- goto out;
1810+ dri_bo *tmp_bo;
1811+ uint16_t tmp;
1812+ int i = 0, num_segments=0;
17811813
17821814 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1815+ assert(decode_state->slice_params && decode_state->slice_params[0]->buffer);
1816+ slice_param = (VASliceParameterBufferVP9 *)decode_state->slice_params[0]->buffer;
17831817 pic_param = (VADecPictureParameterBufferVP9 *)decode_state->pic_param->buffer;
17841818
1785- //****And set the isScaling value accordingly******
1786- isScaling = 0;
1787- for(i = 0; i < 3; i++)
1819+ if(slice_param->slice_data_size == 1)
17881820 {
1789- obj_surface = gen9_hcpd_context->reference_surfaces[i].obj_surface;
1790- gen9_vp9_surface = NULL;
1791- if (obj_surface && obj_surface->private_data)
1792- {
1793- gen9_vp9_surface = obj_surface->private_data;
1794- isScaling |= (gen9_vp9_surface->frame_width == pic_param->frame_width &&
1795- gen9_vp9_surface->frame_height == pic_param->frame_height)? 0:1;
1796- }
1821+ goto out;
17971822 }
17981823
1824+ vaStatus = gen9_hcpd_vp9_decode_init(ctx, decode_state, gen9_hcpd_context);
1825+
1826+ if (vaStatus != VA_STATUS_SUCCESS)
1827+ goto out;
1828+
17991829 //Update segment id buffer if needed
1800- vp9_update_segmentId_buffer(ctx, decode_state, gen9_hcpd_context, isScaling);
1830+ vp9_update_segmentId_buffer(ctx, decode_state, gen9_hcpd_context);
1831+ //Update mv buffer if needed
1832+ vp9_update_mv_temporal_buffer(ctx, decode_state, gen9_hcpd_context);
18011833 //Update probability buffer if needed
18021834 vp9_update_probabilities(ctx, decode_state, gen9_hcpd_context);
18031835
@@ -1812,8 +1844,6 @@ gen9_hcpd_vp9_decode_picture(VADriverContextP ctx,
18121844 gen9_hcpd_vp9_surface_state(ctx, decode_state, gen9_hcpd_context);
18131845
18141846 //Only one VASliceParameterBufferVP9 should be sent per frame
1815- assert(decode_state->slice_params && decode_state->slice_params[0]->buffer);
1816- slice_param = (VASliceParameterBufferVP9 *)decode_state->slice_params[0]->buffer;
18171847 slice_data_bo = decode_state->slice_datas[0]->bo;
18181848
18191849 gen9_hcpd_ind_obj_base_addr_state(ctx, slice_data_bo, gen9_hcpd_context);
@@ -1835,6 +1865,9 @@ gen9_hcpd_vp9_decode_picture(VADriverContextP ctx,
18351865
18361866 gen9_hcpd_vp9_bsd_object(ctx, pic_param, slice_param, gen9_hcpd_context);
18371867
1868+ intel_batchbuffer_end_atomic(batch);
1869+ intel_batchbuffer_flush(batch);
1870+
18381871 // keep track of the last frame status
18391872 gen9_hcpd_context->last_frame.frame_width = pic_param->frame_width;
18401873 gen9_hcpd_context->last_frame.frame_height = pic_param->frame_height;
@@ -1844,11 +1877,23 @@ gen9_hcpd_vp9_decode_picture(VADriverContextP ctx,
18441877 gen9_hcpd_context->last_frame.frame_context_idx = pic_param->pic_fields.bits.frame_context_idx;
18451878 gen9_hcpd_context->last_frame.intra_only = pic_param->pic_fields.bits.intra_only;
18461879
1847- // update prob buffer to vp9_fc;
1880+ // switch mv buffer
1881+ if(pic_param->pic_fields.bits.frame_type != HCP_VP9_KEY_FRAME)
1882+ {
1883+ tmp_bo = gen9_hcpd_context->vp9_mv_temporal_buffer_last.bo;
1884+ gen9_hcpd_context->vp9_mv_temporal_buffer_last.bo = gen9_hcpd_context->vp9_mv_temporal_buffer_curr.bo;
1885+ gen9_hcpd_context->vp9_mv_temporal_buffer_curr.bo = tmp_bo;
18481886
1849- intel_batchbuffer_end_atomic(batch);
1850- intel_batchbuffer_flush(batch);
1887+ tmp = gen9_hcpd_context->vp9_mv_temporal_buffer_last.frame_width;
1888+ gen9_hcpd_context->vp9_mv_temporal_buffer_last.frame_width = gen9_hcpd_context->vp9_mv_temporal_buffer_curr.frame_width;
1889+ gen9_hcpd_context->vp9_mv_temporal_buffer_curr.frame_width = tmp;
1890+
1891+ tmp = gen9_hcpd_context->vp9_mv_temporal_buffer_last.frame_height;
1892+ gen9_hcpd_context->vp9_mv_temporal_buffer_last.frame_height = gen9_hcpd_context->vp9_mv_temporal_buffer_curr.frame_height;
1893+ gen9_hcpd_context->vp9_mv_temporal_buffer_curr.frame_height = tmp;
18511894
1895+
1896+ }
18521897 //update vp9_frame_ctx according to frame_context_id
18531898 if (pic_param->pic_fields.bits.refresh_frame_context)
18541899 {
@@ -1919,6 +1964,8 @@ gen9_hcpd_context_destroy(void *hw_context)
19191964 FREE_GEN_BUFFER((&gen9_hcpd_context->hvd_tile_rowstore_buffer));
19201965 FREE_GEN_BUFFER((&gen9_hcpd_context->vp9_probability_buffer));
19211966 FREE_GEN_BUFFER((&gen9_hcpd_context->vp9_segment_id_buffer));
1967+ dri_bo_unreference(gen9_hcpd_context->vp9_mv_temporal_buffer_curr.bo);
1968+ dri_bo_unreference(gen9_hcpd_context->vp9_mv_temporal_buffer_last.bo);
19221969
19231970 intel_batchbuffer_free(gen9_hcpd_context->base.batch);
19241971 free(gen9_hcpd_context);
@@ -1935,17 +1982,19 @@ static void
19351982 gen9_hcpd_vp9_context_init(VADriverContextP ctx,
19361983 struct gen9_hcpd_context *gen9_hcpd_context)
19371984 {
1938- int default_value = 255;
19391985
19401986 gen9_hcpd_context->last_frame.frame_height = 0;
19411987 gen9_hcpd_context->last_frame.show_frame = 0;
19421988 gen9_hcpd_context->last_frame.frame_type = 0;
1943- gen9_hcpd_context->last_frame.refresh_frame_context = default_value;
1944- gen9_hcpd_context->last_frame.frame_context_idx = default_value;
1989+ gen9_hcpd_context->last_frame.refresh_frame_context = 0;
1990+ gen9_hcpd_context->last_frame.frame_context_idx = 0;
19451991 gen9_hcpd_context->last_frame.intra_only = 0;
19461992 gen9_hcpd_context->last_frame.prob_buffer_saved_flag = 0;
19471993 gen9_hcpd_context->last_frame.prob_buffer_restored_flag = 0;
1948- gen9_hcpd_context->last_frame.mv_temporal_buffer_bo = NULL;
1994+
1995+ //Super block in VP9 is 64x64
1996+ gen9_hcpd_context->ctb_size = 64;
1997+ gen9_hcpd_context->min_cb_size = 8; //Min block size is 8
19491998
19501999 vp9_gen_default_probabilities(ctx, gen9_hcpd_context);
19512000 }
--- a/src/gen9_mfd.h
+++ b/src/gen9_mfd.h
@@ -49,9 +49,15 @@ typedef struct vp9_frame_status
4949 uint8_t intra_only;
5050 uint8_t prob_buffer_saved_flag;
5151 uint8_t prob_buffer_restored_flag;
52- dri_bo * mv_temporal_buffer_bo;
5352 }vp9_last_frame_status;
5453
54+typedef struct vp9_mv_temporal_buffer
55+{
56+ dri_bo *bo;
57+ uint16_t frame_width;
58+ uint16_t frame_height;
59+}VP9_MV_BUFFER;
60+
5561 struct gen9_hcpd_context
5662 {
5763 struct hw_context base;
@@ -84,6 +90,8 @@ struct gen9_hcpd_context
8490 GenBuffer hvd_tile_rowstore_buffer;
8591 GenBuffer vp9_probability_buffer;
8692 GenBuffer vp9_segment_id_buffer;
93+ VP9_MV_BUFFER vp9_mv_temporal_buffer_curr;
94+ VP9_MV_BUFFER vp9_mv_temporal_buffer_last;
8795
8896 unsigned short first_inter_slice_collocated_ref_idx;
8997 unsigned short first_inter_slice_collocated_from_l0_flag;
--- a/src/i965_device_info.c
+++ b/src/i965_device_info.c
@@ -401,6 +401,7 @@ static struct hw_codec_info bxt_hw_codec_info = {
401401 .has_hevc_encoding = 1,
402402 .has_hevc10_decoding = 1,
403403 .has_vp9_decoding = 1,
404+ .has_vpp_p010 = 1,
404405
405406 .num_filters = 5,
406407 .filters = {
@@ -412,7 +413,6 @@ static struct hw_codec_info bxt_hw_codec_info = {
412413 },
413414 };
414415
415-
416416 struct hw_codec_info *
417417 i965_get_codec_info(int devid)
418418 {
--- a/src/i965_drv_video.c
+++ b/src/i965_drv_video.c
@@ -112,6 +112,9 @@
112112 #define HAS_HEVC10_DECODING(ctx) ((ctx)->codec_info->has_hevc10_decoding && \
113113 (ctx)->intel.has_bsd)
114114
115+#define HAS_VPP_P010(ctx) ((ctx)->codec_info->has_vpp_p010 && \
116+ (ctx)->intel.has_bsd)
117+
115118 static int get_sampling_from_fourcc(unsigned int fourcc);
116119
117120 /* Check whether we are rendering to X11 (VA/X11 or VA/GLX API) */
@@ -316,6 +319,8 @@ i965_image_formats_map[I965_MAX_IMAGE_FORMATS + 1] = {
316319 { VA_FOURCC_RGBX, VA_LSB_FIRST, 32, 24, 0x000000ff, 0x0000ff00, 0x00ff0000 } },
317320 { I965_SURFACETYPE_RGBA,
318321 { VA_FOURCC_BGRX, VA_LSB_FIRST, 32, 24, 0x00ff0000, 0x0000ff00, 0x000000ff } },
322+ { I965_SURFACETYPE_YUV,
323+ { VA_FOURCC_P010, VA_LSB_FIRST, 24, } },
319324 };
320325
321326 /* List of supported subpicture formats */
@@ -878,6 +883,12 @@ i965_get_default_chroma_formats(VADriverContextP ctx, VAProfile profile,
878883 if (HAS_HEVC10_DECODING(i965) && entrypoint == VAEntrypointVLD)
879884 chroma_formats |= i965->codec_info->hevc_dec_chroma_formats;
880885 break;
886+
887+ case VAProfileNone:
888+ if(HAS_VPP_P010(i965))
889+ chroma_formats |= VA_RT_FORMAT_YUV420_10BPP;
890+ break;
891+
881892 default:
882893 break;
883894 }
@@ -3759,6 +3770,14 @@ i965_CreateImage(VADriverContextP ctx,
37593770 image->offsets[0] = 0;
37603771 image->data_size = size * 2;
37613772 break;
3773+ case VA_FOURCC_P010:
3774+ image->num_planes = 2;
3775+ image->pitches[0] = awidth * 2;
3776+ image->offsets[0] = 0;
3777+ image->pitches[1] = awidth * 2;
3778+ image->offsets[1] = size * 2;
3779+ image->data_size = size * 2 + 2 * size2 * 2;
3780+ break;
37623781 default:
37633782 goto error;
37643783 }
@@ -3819,22 +3838,22 @@ i965_check_alloc_surface_bo(VADriverContextP ctx,
38193838
38203839 int bpp_1stplane = bpp_1stplane_by_fourcc(fourcc);
38213840
3822- if (obj_surface->user_h_stride_set) {
3823- ASSERT_RET(IS_ALIGNED(obj_surface->width, 128), VA_STATUS_ERROR_INVALID_PARAMETER);
3824- } else
3825- obj_surface->width = ALIGN(obj_surface->orig_width * bpp_1stplane, 128);
3826-
3827- if (obj_surface->user_v_stride_set) {
3828- ASSERT_RET(IS_ALIGNED(obj_surface->height, 32), VA_STATUS_ERROR_INVALID_PARAMETER);
3829- } else
3830- obj_surface->height = ALIGN(obj_surface->orig_height, 32);
3831-
38323841 if ((tiled && !obj_surface->user_disable_tiling)) {
38333842 ASSERT_RET(fourcc != VA_FOURCC_I420 &&
38343843 fourcc != VA_FOURCC_IYUV &&
38353844 fourcc != VA_FOURCC_YV12,
38363845 VA_STATUS_ERROR_UNSUPPORTED_RT_FORMAT);
38373846
3847+ if (obj_surface->user_h_stride_set) {
3848+ ASSERT_RET(IS_ALIGNED(obj_surface->width, 128), VA_STATUS_ERROR_INVALID_PARAMETER);
3849+ } else
3850+ obj_surface->width = ALIGN(obj_surface->orig_width * bpp_1stplane, 128);
3851+
3852+ if (obj_surface->user_v_stride_set) {
3853+ ASSERT_RET(IS_ALIGNED(obj_surface->height, 32), VA_STATUS_ERROR_INVALID_PARAMETER);
3854+ }else
3855+ obj_surface->height = ALIGN(obj_surface->orig_height, 32);
3856+
38383857 region_height = obj_surface->height;
38393858
38403859 switch (fourcc) {
@@ -5688,6 +5707,14 @@ i965_QuerySurfaceAttributes(VADriverContextP ctx,
56885707 attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE;
56895708 attribs[i].value.value.i = VA_FOURCC_YV16;
56905709 i++;
5710+
5711+ if(HAS_VPP_P010(i965)) {
5712+ attribs[i].type = VASurfaceAttribPixelFormat;
5713+ attribs[i].value.type = VAGenericValueTypeInteger;
5714+ attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE;
5715+ attribs[i].value.value.i = VA_FOURCC_P010;
5716+ i++;
5717+ }
56915718 }
56925719 }
56935720 }
--- a/src/i965_drv_video.h
+++ b/src/i965_drv_video.h
@@ -388,6 +388,7 @@ struct hw_codec_info
388388 unsigned int has_hevc_encoding:1;
389389 unsigned int has_hevc10_decoding:1;
390390 unsigned int has_vp9_decoding:1;
391+ unsigned int has_vpp_p010:1;
391392
392393 unsigned int num_filters;
393394 struct i965_filter filters[VAProcFilterCount];
--- a/src/i965_post_processing.c
+++ b/src/i965_post_processing.c
@@ -41,6 +41,8 @@
4141 #include "i965_yuv_coefs.h"
4242 #include "intel_media.h"
4343
44+#include "gen75_picture_process.h"
45+
4446 extern VAStatus
4547 vpp_surface_convert(VADriverContextP ctx,
4648 struct object_surface *src_obj_surf,
@@ -5296,6 +5298,183 @@ i965_image_pl1_processing(VADriverContextP ctx,
52965298 return vaStatus;
52975299 }
52985300
5301+// it only support NV12 and P010 for vebox proc ctx
5302+static struct object_surface *derive_surface(VADriverContextP ctx,
5303+ struct object_image *obj_image,
5304+ struct object_surface *obj_surface)
5305+{
5306+ VAImage * const image = &obj_image->image;
5307+
5308+ memset((void *)obj_surface, 0, sizeof(*obj_surface));
5309+ obj_surface->fourcc = image->format.fourcc;
5310+ obj_surface->orig_width = image->width;
5311+ obj_surface->orig_height = image->height;
5312+ obj_surface->width = image->pitches[0];
5313+ obj_surface->height = image->height;
5314+ obj_surface->y_cb_offset = image->offsets[1] / obj_surface->width;
5315+ obj_surface->y_cr_offset = obj_surface->y_cb_offset;
5316+ obj_surface->bo = obj_image->bo;
5317+ obj_surface->subsampling = SUBSAMPLE_YUV420;
5318+
5319+ return obj_surface;
5320+}
5321+
5322+static VAStatus
5323+vebox_processing_simple(VADriverContextP ctx,
5324+ struct i965_post_processing_context *pp_context,
5325+ struct object_surface *src_obj_surface,
5326+ struct object_surface *dst_obj_surface,
5327+ const VARectangle *rect)
5328+{
5329+ struct i965_driver_data *i965 = i965_driver_data(ctx);
5330+ VAProcPipelineParameterBuffer pipeline_param;
5331+ VAStatus status = VA_STATUS_ERROR_UNIMPLEMENTED;
5332+
5333+ if(pp_context->vebox_proc_ctx == NULL) {
5334+ pp_context->vebox_proc_ctx = gen75_vebox_context_init(ctx);
5335+ }
5336+
5337+ memset((void *)&pipeline_param, 0, sizeof(pipeline_param));
5338+ pipeline_param.surface_region = rect;
5339+ pipeline_param.output_region = rect;
5340+ pipeline_param.filter_flags = 0;
5341+ pipeline_param.num_filters = 0;
5342+
5343+ pp_context->vebox_proc_ctx->pipeline_param = &pipeline_param;
5344+ pp_context->vebox_proc_ctx->surface_input_object = src_obj_surface;
5345+ pp_context->vebox_proc_ctx->surface_output_object = dst_obj_surface;
5346+
5347+ if (IS_GEN9(i965->intel.device_info))
5348+ status = gen9_vebox_process_picture(ctx, pp_context->vebox_proc_ctx);
5349+
5350+ return status;
5351+}
5352+
5353+static VAStatus
5354+i965_image_p010_processing(VADriverContextP ctx,
5355+ const struct i965_surface *src_surface,
5356+ const VARectangle *src_rect,
5357+ struct i965_surface *dst_surface,
5358+ const VARectangle *dst_rect)
5359+{
5360+#define HAS_VPP_P010(ctx) ((ctx)->codec_info->has_vpp_p010 && \
5361+ (ctx)->intel.has_bsd)
5362+
5363+ struct i965_driver_data *i965 = i965_driver_data(ctx);
5364+ struct i965_post_processing_context *pp_context = i965->pp_context;
5365+ struct object_surface *src_obj_surface = NULL, *dst_obj_surface = NULL;
5366+ struct object_surface tmp_src_obj_surface, tmp_dst_obj_surface;
5367+ struct object_surface *tmp_surface = NULL;
5368+ VASurfaceID tmp_surface_id[3], out_surface_id = VA_INVALID_ID;
5369+ int num_tmp_surfaces = 0;
5370+ int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
5371+ VAStatus vaStatus = VA_STATUS_ERROR_UNIMPLEMENTED;
5372+ int vpp_post = 0;
5373+
5374+ if(HAS_VPP_P010(i965)) {
5375+ vpp_post = 0;
5376+ switch(fourcc) {
5377+ case VA_FOURCC_NV12:
5378+ if(src_rect->x != dst_rect->x ||
5379+ src_rect->y != dst_rect->y ||
5380+ src_rect->width != dst_rect->width ||
5381+ src_rect->height != dst_rect->height) {
5382+ vpp_post = 1;
5383+ }
5384+ break;
5385+ case VA_FOURCC_P010:
5386+ // don't support scaling while the fourcc of dst_surface is P010
5387+ if(src_rect->x != dst_rect->x ||
5388+ src_rect->y != dst_rect->y ||
5389+ src_rect->width != dst_rect->width ||
5390+ src_rect->height != dst_rect->height) {
5391+ vaStatus = VA_STATUS_ERROR_UNIMPLEMENTED;
5392+ goto EXIT;
5393+ }
5394+ break;
5395+ default:
5396+ vpp_post = 1;
5397+ break;
5398+ }
5399+
5400+ if(src_surface->type == I965_SURFACE_TYPE_IMAGE) {
5401+ src_obj_surface = derive_surface(ctx, (struct object_image *)src_surface->base,
5402+ &tmp_src_obj_surface);
5403+ }
5404+ else
5405+ src_obj_surface = (struct object_surface *)src_surface->base;
5406+
5407+ if(src_obj_surface == NULL) {
5408+ vaStatus = VA_STATUS_ERROR_ALLOCATION_FAILED;
5409+ goto EXIT;
5410+ }
5411+
5412+ if(vpp_post == 1) {
5413+ vaStatus = i965_CreateSurfaces(ctx,
5414+ src_obj_surface->orig_width,
5415+ src_obj_surface->orig_height,
5416+ VA_RT_FORMAT_YUV420,
5417+ 1,
5418+ &out_surface_id);
5419+ assert(vaStatus == VA_STATUS_SUCCESS);
5420+ tmp_surface_id[num_tmp_surfaces++] = out_surface_id;
5421+ tmp_surface = SURFACE(out_surface_id);
5422+ assert(tmp_surface);
5423+ i965_check_alloc_surface_bo(ctx, tmp_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
5424+ }
5425+
5426+ if(tmp_surface != NULL)
5427+ dst_obj_surface = tmp_surface;
5428+ else {
5429+ if(dst_surface->type == I965_SURFACE_TYPE_IMAGE) {
5430+ dst_obj_surface = derive_surface(ctx, (struct object_image *)dst_surface->base,
5431+ &tmp_dst_obj_surface);
5432+ }
5433+ else
5434+ dst_obj_surface = (struct object_surface *)dst_surface->base;
5435+ }
5436+
5437+ if(dst_obj_surface == NULL) {
5438+ vaStatus = VA_STATUS_ERROR_ALLOCATION_FAILED;
5439+ goto EXIT;
5440+ }
5441+
5442+ vaStatus = vebox_processing_simple(ctx,
5443+ pp_context,
5444+ src_obj_surface,
5445+ dst_obj_surface,
5446+ src_rect);
5447+ if(vaStatus != VA_STATUS_SUCCESS)
5448+ goto EXIT;
5449+
5450+ if(vpp_post == 1) {
5451+ struct i965_surface src_surface_new;
5452+
5453+ if(tmp_surface != NULL){
5454+ src_surface_new.base = (struct object_base *)tmp_surface;
5455+ src_surface_new.type = I965_SURFACE_TYPE_SURFACE;
5456+ src_surface_new.flags = I965_SURFACE_FLAG_FRAME;
5457+ }
5458+ else
5459+ memcpy((void *)&src_surface_new, (void *)src_surface, sizeof(src_surface_new));
5460+
5461+ vaStatus = i965_image_pl2_processing(ctx,
5462+ &src_surface_new,
5463+ src_rect,
5464+ dst_surface,
5465+ dst_rect);
5466+ }
5467+ }
5468+
5469+EXIT:
5470+ if(num_tmp_surfaces)
5471+ i965_DestroySurfaces(ctx,
5472+ tmp_surface_id,
5473+ num_tmp_surfaces);
5474+
5475+ return vaStatus;
5476+}
5477+
52995478 VAStatus
53005479 i965_image_processing(VADriverContextP ctx,
53015480 const struct i965_surface *src_surface,
@@ -5353,6 +5532,13 @@ i965_image_processing(VADriverContextP ctx,
53535532 dst_surface,
53545533 dst_rect);
53555534 break;
5535+ case VA_FOURCC_P010:
5536+ status = i965_image_p010_processing(ctx,
5537+ src_surface,
5538+ src_rect,
5539+ dst_surface,
5540+ dst_rect);
5541+ break;
53565542 default:
53575543 status = VA_STATUS_ERROR_UNIMPLEMENTED;
53585544 break;
--- a/src/i965_post_processing.h
+++ b/src/i965_post_processing.h
@@ -528,6 +528,8 @@ struct i965_post_processing_context
528528 unsigned int curbe_allocation_size : 16;
529529 } vfe_gpu_state;
530530
531+ struct intel_vebox_context *vebox_proc_ctx;
532+
531533 struct pp_load_save_context pp_load_save_context;
532534 struct pp_scaling_context pp_scaling_context;
533535 struct pp_avs_context pp_avs_context;
--- a/src/intel_media_common.c
+++ b/src/intel_media_common.c
@@ -123,9 +123,6 @@ void gen_free_vp9_surface(void **data)
123123 return;
124124 }
125125
126- dri_bo_unreference(vp9_surface->motion_vector_temporal_bo);
127- vp9_surface->motion_vector_temporal_bo = NULL;
128-
129126 free(vp9_surface);
130127 *data = NULL;
131128