Commit: 5fb654b2577be19005bd9792a0b62c3ac1d2395b - hardware-intel-intel-driver (git)

hardware/intel/intel-driver

Commit MetaInfo

• Revision: 5fb654b2577be19005bd9792a0b62c3ac1d2395b (tree)
• Zeit: 2016-01-29 14:44:34
• Autor: Peng Chen <peng.c.chen@inte...>
• Commiter: Xiang, Haihao

Log Message

KBL driver enabling

v2:
remove the file mode change

v1:
initial

Signed-off-by: peng.chen <[e-mail]>

Ändern Zusammenfassung

• modified: src/gen9_mfc_hevc.c
• modified: src/i965_device_info.c
• modified: src/i965_pciids.h
• modified: src/intel_driver.h

Diff

--- a/src/gen9_mfc_hevc.c
+++ b/src/gen9_mfc_hevc.c
@@ -152,13 +152,24 @@ gen9_hcpe_pipe_mode_select(VADriverContextP ctx,
                            int standard_select,
                            struct intel_encoder_context *encoder_context)
 {
+    struct i965_driver_data *i965 = i965_driver_data(ctx);
     struct intel_batchbuffer *batch = encoder_context->base.batch;
 
     assert(standard_select == HCP_CODEC_HEVC);
 
-    BEGIN_BCS_BATCH(batch, 4);
+    if(IS_KBL(i965->intel.device_info))
+    {
+        BEGIN_BCS_BATCH(batch, 6);
+
+        OUT_BCS_BATCH(batch, HCP_PIPE_MODE_SELECT | (6 - 2));
+    }
+    else
+    {
+        BEGIN_BCS_BATCH(batch, 4);
+
+        OUT_BCS_BATCH(batch, HCP_PIPE_MODE_SELECT | (4 - 2));
+    }
 
-    OUT_BCS_BATCH(batch, HCP_PIPE_MODE_SELECT | (4 - 2));
     OUT_BCS_BATCH(batch,
                   (standard_select << 5) |
                   (0 << 3) | /* disable Pic Status / Error Report */
@@ -166,6 +177,12 @@ gen9_hcpe_pipe_mode_select(VADriverContextP ctx,
     OUT_BCS_BATCH(batch, 0);
     OUT_BCS_BATCH(batch, 0);
 
+    if(IS_KBL(i965->intel.device_info))
+    {
+        OUT_BCS_BATCH(batch, 0);
+        OUT_BCS_BATCH(batch, 0);
+    }
+
     ADVANCE_BCS_BATCH(batch);
 }
 
@@ -209,6 +226,7 @@ static void
 gen9_hcpe_pipe_buf_addr_state(VADriverContextP ctx, struct encode_state *encode_state,
                               struct intel_encoder_context *encoder_context)
 {
+    struct i965_driver_data *i965 = i965_driver_data(ctx);
     struct intel_batchbuffer *batch = encoder_context->base.batch;
     struct gen9_hcpe_context *mfc_context = encoder_context->mfc_context;
     struct object_surface *obj_surface;
@@ -216,9 +234,18 @@ gen9_hcpe_pipe_buf_addr_state(VADriverContextP ctx, struct encode_state *encode_
     dri_bo *bo;
     unsigned int i;
 
-    BEGIN_BCS_BATCH(batch, 95);
+    if(IS_KBL(i965->intel.device_info))
+    {
+        BEGIN_BCS_BATCH(batch, 104);
 
-    OUT_BCS_BATCH(batch, HCP_PIPE_BUF_ADDR_STATE | (95 - 2));
+        OUT_BCS_BATCH(batch, HCP_PIPE_BUF_ADDR_STATE | (104 - 2));
+    }
+    else
+    {
+        BEGIN_BCS_BATCH(batch, 95);
+
+        OUT_BCS_BATCH(batch, HCP_PIPE_BUF_ADDR_STATE | (95 - 2));
+    }
 
     obj_surface = encode_state->reconstructed_object;
     assert(obj_surface && obj_surface->bo);
@@ -269,6 +296,12 @@ gen9_hcpe_pipe_buf_addr_state(VADriverContextP ctx, struct encode_state *encode_
     OUT_BUFFER_MA_TARGET(NULL);    /* DW 89..91, ignore for HEVC */
     OUT_BUFFER_MA_TARGET(NULL);    /* DW 92..94, ignore for HEVC */
 
+    if(IS_KBL(i965->intel.device_info))
+    {
+        for(i = 0;i < 9;i++)
+            OUT_BCS_BATCH(batch, 0);
+    }
+
     ADVANCE_BCS_BATCH(batch);
 }
 
@@ -459,6 +492,7 @@ static void
 gen9_hcpe_hevc_pic_state(VADriverContextP ctx, struct encode_state *encode_state,
                          struct intel_encoder_context *encoder_context)
 {
+    struct i965_driver_data *i965 = i965_driver_data(ctx);
     struct intel_batchbuffer *batch = encoder_context->base.batch;
     struct gen9_hcpe_context *mfc_context = encoder_context->mfc_context;
     VAEncPictureParameterBufferHEVC *pic_param ;
@@ -504,9 +538,18 @@ gen9_hcpe_hevc_pic_state(VADriverContextP ctx, struct encode_state *encode_state
     /* set zero for encoder */
     loop_filter_across_tiles_enabled_flag = 0;
 
-    BEGIN_BCS_BATCH(batch, 19);
+    if(IS_KBL(i965->intel.device_info))
+    {
+        BEGIN_BCS_BATCH(batch, 31);
 
-    OUT_BCS_BATCH(batch, HCP_PIC_STATE | (19 - 2));
+        OUT_BCS_BATCH(batch, HCP_PIC_STATE | (31 - 2));
+    }
+    else
+    {
+        BEGIN_BCS_BATCH(batch, 19);
+
+        OUT_BCS_BATCH(batch, HCP_PIC_STATE | (19 - 2));
+    }
 
     OUT_BCS_BATCH(batch,
                   mfc_context->pic_size.picture_height_in_min_cb_minus1 << 16 |
@@ -523,7 +566,7 @@ gen9_hcpe_hevc_pic_state(VADriverContextP ctx, struct encode_state *encode_state
                   seq_param->log2_min_luma_coding_block_size_minus3);
     OUT_BCS_BATCH(batch, 0); /* DW 3, ignored */
     OUT_BCS_BATCH(batch,
-                  0 << 27 | /* CU packet structure is 0 for SKL */
+                  (IS_KBL(i965->intel.device_info)? 1 : 0) << 27 | /* CU packet structure is 0 for SKL */
                   seq_param->seq_fields.bits.strong_intra_smoothing_enabled_flag << 26 |
                   pic_param->pic_fields.bits.transquant_bypass_enabled_flag << 25 |
                   seq_param->seq_fields.bits.amp_enabled_flag << 23 |
@@ -577,6 +620,14 @@ gen9_hcpe_hevc_pic_state(VADriverContextP ctx, struct encode_state *encode_state
                   0 << 30 |
                   minframesize);    /* DW 18, min frame size units */
 
+    if(IS_KBL(i965->intel.device_info))
+    {
+        int i = 0;
+
+        for(i = 0;i < 12;i++)
+            OUT_BCS_BATCH(batch, 0);
+    }
+
     ADVANCE_BCS_BATCH(batch);
 }
 
@@ -723,6 +774,7 @@ gen9_hcpe_hevc_slice_state(VADriverContextP ctx,
                            struct intel_encoder_context *encoder_context,
                            struct intel_batchbuffer *batch)
 {
+    struct i965_driver_data *i965 = i965_driver_data(ctx);
     VAEncSequenceParameterBufferHEVC *pSequenceParameter = (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
     int slice_type = slice_param->slice_type;
 
@@ -754,9 +806,18 @@ gen9_hcpe_hevc_slice_state(VADriverContextP ctx,
         }
     }
 
-    BEGIN_BCS_BATCH(batch, 9);
+    if(IS_KBL(i965->intel.device_info))
+    {
+        BEGIN_BCS_BATCH(batch, 11);
+
+        OUT_BCS_BATCH(batch, HCP_SLICE_STATE | (11 - 2));
+    }
+    else
+    {
+        BEGIN_BCS_BATCH(batch, 9);
 
-    OUT_BCS_BATCH(batch, HCP_SLICE_STATE | (9 - 2));
+        OUT_BCS_BATCH(batch, HCP_SLICE_STATE | (9 - 2));
+    }
 
     OUT_BCS_BATCH(batch,
                   slice_ver_pos << 16 |
@@ -801,6 +862,12 @@ gen9_hcpe_hevc_slice_state(VADriverContextP ctx,
                   0);        /* Ignored for decoding */
     OUT_BCS_BATCH(batch, 0); /* PAK-BSE data start offset */
 
+    if(IS_KBL(i965->intel.device_info))
+    {
+        OUT_BCS_BATCH(batch, 0);
+        OUT_BCS_BATCH(batch, 0);
+    }
+
     ADVANCE_BCS_BATCH(batch);
 }
 
@@ -1097,8 +1164,12 @@ gen9_hcpe_hevc_pak_object(VADriverContextP ctx, int lcu_x, int lcu_y, int isLast
                           int cu_count_in_lcu, unsigned int split_coding_unit_flag,
                           struct intel_batchbuffer *batch)
 {
+    struct i965_driver_data *i965 = i965_driver_data(ctx);
     int len_in_dwords = 3;
 
+    if(IS_KBL(i965->intel.device_info))
+        len_in_dwords = 5;
+
     if (batch == NULL)
         batch = encoder_context->base.batch;
 
@@ -1112,6 +1183,12 @@ gen9_hcpe_hevc_pak_object(VADriverContextP ctx, int lcu_x, int lcu_y, int isLast
 
     OUT_BCS_BATCH(batch, (lcu_y << 16) | lcu_x);        /* LCU  for Y*/
 
+    if(IS_KBL(i965->intel.device_info))
+    {
+        OUT_BCS_BATCH(batch, 0);
+        OUT_BCS_BATCH(batch, 0);
+    }
+
     ADVANCE_BCS_BATCH(batch);
 
     return len_in_dwords;

--- a/src/i965_device_info.c
+++ b/src/i965_device_info.c
@@ -413,6 +413,57 @@ static struct hw_codec_info bxt_hw_codec_info = {
     },
 };
 
+static struct hw_codec_info kbl_hw_codec_info = {
+    .dec_hw_context_init = gen9_dec_hw_context_init,
+    .enc_hw_context_init = gen9_enc_hw_context_init,
+    .proc_hw_context_init = gen75_proc_context_init,
+    .render_init = gen9_render_init,
+    .post_processing_context_init = gen9_post_processing_context_init,
+
+    .max_width = 4096,
+    .max_height = 4096,
+    .min_linear_wpitch = 64,
+    .min_linear_hpitch = 16,
+
+    .h264_mvc_dec_profiles = (VA_PROFILE_MASK(H264StereoHigh) |
+                              VA_PROFILE_MASK(H264MultiviewHigh)),
+    .h264_dec_chroma_formats = EXTRA_H264_DEC_CHROMA_FORMATS,
+    .jpeg_dec_chroma_formats = EXTRA_JPEG_DEC_CHROMA_FORMATS,
+    .jpeg_enc_chroma_formats = EXTRA_JPEG_ENC_CHROMA_FORMATS,
+    .hevc_dec_chroma_formats = EXTRA_HEVC_DEC_CHROMA_FORMATS,
+
+    .has_mpeg2_decoding = 1,
+    .has_mpeg2_encoding = 1,
+    .has_h264_decoding = 1,
+    .has_h264_encoding = 1,
+    .has_vc1_decoding = 1,
+    .has_jpeg_decoding = 1,
+    .has_jpeg_encoding = 1,
+    .has_vpp = 1,
+    .has_accelerated_getimage = 1,
+    .has_accelerated_putimage = 1,
+    .has_tiled_surface = 1,
+    .has_di_motion_adptive = 1,
+    .has_di_motion_compensated = 1,
+    .has_vp8_decoding = 1,
+    .has_vp8_encoding = 1,
+    .has_h264_mvc_encoding = 1,
+    .has_hevc_decoding = 1,
+    .has_hevc_encoding = 1,
+    .has_hevc10_decoding = 1,
+    .has_vp9_decoding = 1,
+    .has_vpp_p010 = 1,
+
+    .num_filters = 5,
+    .filters = {
+        { VAProcFilterNoiseReduction, I965_RING_VEBOX },
+        { VAProcFilterDeinterlacing, I965_RING_VEBOX },
+        { VAProcFilterSharpening, I965_RING_NULL },
+        { VAProcFilterColorBalance, I965_RING_VEBOX},
+        { VAProcFilterSkinToneEnhancement, I965_RING_VEBOX},
+    },
+};
+
 struct hw_codec_info *
 i965_get_codec_info(int devid)
 {
@@ -549,6 +600,15 @@ static const struct intel_device_info bxt_device_info = {
     .is_broxton = 1,
 };
 
+static const struct intel_device_info kbl_device_info = {
+    .gen = 9,
+
+    .urb_size = 4096,
+    .max_wm_threads = 64,       /* per PSD */
+
+    .is_kabylake = 1,
+};
+
 const struct intel_device_info *
 i965_get_device_info(int devid)
 {

--- a/src/i965_pciids.h
+++ b/src/i965_pciids.h
@@ -158,3 +158,25 @@ CHIPSET(0x193D, skl, skl,       "Intel(R) Skylake")
 CHIPSET(0x0A84, bxt, bxt,       "Intel(R) Broxton")
 CHIPSET(0x1A84, bxt, bxt,       "Intel(R) Broxton")
 CHIPSET(0x5A84, bxt, bxt,       "Intel(R) Broxton")
+CHIPSET(0x5916, kbl, kbl,       "Intel(R) Kabylake")
+CHIPSET(0x5913, kbl, kbl,       "Intel(R) Kabylake")
+CHIPSET(0x5906, kbl, kbl,       "Intel(R) Kabylake")
+CHIPSET(0x5926, kbl, kbl,       "Intel(R) Kabylake")
+CHIPSET(0x5921, kbl, kbl,       "Intel(R) Kabylake")
+CHIPSET(0x5915, kbl, kbl,       "Intel(R) Kabylake")
+CHIPSET(0x590E, kbl, kbl,       "Intel(R) Kabylake")
+CHIPSET(0x591E, kbl, kbl,       "Intel(R) Kabylake")
+CHIPSET(0x5912, kbl, kbl,       "Intel(R) Kabylake")
+CHIPSET(0x5917, kbl, kbl,       "Intel(R) Kabylake")
+CHIPSET(0x5902, kbl, kbl,       "Intel(R) Kabylake")
+CHIPSET(0x5932, kbl, kbl,       "Intel(R) Kabylake")
+CHIPSET(0x591B, kbl, kbl,       "Intel(R) Kabylake")
+CHIPSET(0x592B, kbl, kbl,       "Intel(R) Kabylake")
+CHIPSET(0x593B, kbl, kbl,       "Intel(R) Kabylake")
+CHIPSET(0x590B, kbl, kbl,       "Intel(R) Kabylake")
+CHIPSET(0x591A, kbl, kbl,       "Intel(R) Kabylake")
+CHIPSET(0x592A, kbl, kbl,       "Intel(R) Kabylake")
+CHIPSET(0x593A, kbl, kbl,       "Intel(R) Kabylake")
+CHIPSET(0x590A, kbl, kbl,       "Intel(R) Kabylake")
+CHIPSET(0x591D, kbl, kbl,       "Intel(R) Kabylake")
+CHIPSET(0x593D, kbl, kbl,       "Intel(R) Kabylake")
\ No newline at end of file

--- a/src/intel_driver.h
+++ b/src/intel_driver.h
@@ -137,6 +137,7 @@ struct intel_device_info
     unsigned int is_haswell     : 1; /* gen7 */
     unsigned int is_cherryview  : 1; /* gen8 */
     unsigned int is_broxton     : 1; /* gen9 */
+    unsigned int is_kabylake    : 1; /* gen9p5 */
 };
 
 struct intel_driver_data 
@@ -198,4 +199,6 @@ struct intel_region
 
 #define IS_GEN9(device_info)            (device_info->gen == 9)
 
+#define IS_KBL(device_info)             (device_info->is_kabylake)
+
 #endif /* _INTEL_DRIVER_H_ */