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cli: cy_io - data in/dual in OK

fpga: cy_io: ctrl OK

fpga: cy_io_test quartus

fpga: cy_io_test_sim

fpga: cy_io quartus

fpga: cy_io: cy_in_out_core

fpga: cy_in_out_core

fpga: cy_io_test

fpga: cy_io_test: cfg_in

fpga: cy_io_test_sim

fpga: cy_in_burst_core, cy_io

fpga: cy_io -> cy_in

fpga: cy_io.. -> cy_in; cy_burst

fpga: fifo mixed; cnt_test

fpga: fifo mixed widths test

fpga: clock mux test

fpga: pll clock mux test

fpga: cy_in_out_test fixed; bulk_speed: updated

fpga: cy_in_out: data_in_req/_ack

fpga: cy_in_out pktend

cy_in_out synthesised, time constrains updated

fpga: cy_in_out

fpga: ctrl.txt

fpga: fifo read timing

gui: trigger number limit

gui: pan_trigger, zoom_all

constant iso ring time

fpga: pll test with 180MHz

fpga: pll test with 130MHz

fpga: cy_io_burst made more similar to _burst2