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digital oscilloscope


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Revisionf59d81af1ec8fc3091590dd54b30231e90af3384 (tree)
Zeit2018-11-23 20:30:57
AutorPJ_WORK
CommiterPJ_WORK

Log Message

ep3/cy_max_test: capture DATA in on falling edge

Ändern Zusammenfassung

Diff

diff -r 6ae688c6805a -r f59d81af1ec8 ep3/cy_max_test.sdc
--- a/ep3/cy_max_test.sdc Thu Nov 22 20:41:00 2018 +0000
+++ b/ep3/cy_max_test.sdc Fri Nov 23 11:30:57 2018 +0000
@@ -44,23 +44,23 @@
4444 set usb_flags [get_ports { usb_flaga_i usb_flagb_i usb_flagc_i }]
4545
4646 # margin
47-set cy_out_extra_setup 1.0
48-set cy_out_extra_hold 0.5
49-set cy_dout_extra_setup 5.0
50-set cy_dout_extra_hold 2.0
51-set cy_flg_setup_margin 2.0
47+set cy_out_setup_margin 1.0
48+set cy_out_hold_margin 0.5
49+set cy_dout_setup_margin 5.0
50+set cy_dout_hold_margin 2.0
51+set cy_flg_setup_margin 2.5
5252 set cy_din_hold_margin 0.5
5353
5454 set din_rel_to_clk 1
5555 if $din_rel_to_clk {
5656 set din_clk $clk
5757 # (desired) Din setup (rel to clk)
58-#set cy_din_setup 2.0
5958 set cy_din_setup 1.0
6059 set cy_din_setup_margin 1.0
6160 # (desired) Din hold (rel to clk)
6261 #set cy_din_hold 3.0
63-set cy_din_hold 5.0
62+#set cy_din_hold 5.0
63+set cy_din_hold 10.0
6464 } else {
6565 set din_clk ifclk
6666 # (desired) Din setup (rel to ifclk)
@@ -73,18 +73,33 @@
7373 }
7474
7575 # max out delay = setup + margin
76-set cy_slrd_max [expr { $cy_out_extra_setup + 12.7 }]
77-set cy_slwr_max [expr { $cy_out_extra_setup + 12.1 }]
78-set cy_pend_max [expr { $cy_out_extra_setup + 8.6 }]
79-set cy_fadr_max [expr { $cy_out_extra_setup + 25 }]
80-set cy_dout_max [expr { $cy_dout_extra_setup + 3.2 }]
76+set cy_slrd_max [expr { $cy_out_setup_margin + 12.7 }]
77+set cy_slwr_max [expr { $cy_out_setup_margin + 12.1 }]
78+set cy_pend_max [expr { $cy_out_setup_margin + 8.6 }]
79+set cy_fadr_max [expr { $cy_out_setup_margin + 25 }]
80+set cy_dout_max [expr { $cy_dout_setup_margin + 3.2 }]
8181
8282 # min out delay = - (hold + margin)
83-set cy_slrd_min [expr { - ( $cy_out_extra_hold + 3.7 ) }]
84-set cy_slwr_min [expr { - ( $cy_out_extra_hold + 3.6 ) }]
85-set cy_pend_min [expr { - ( $cy_out_extra_hold + 2.5 ) }]
86-set cy_fadr_min [expr { - ( $cy_out_extra_hold + 10 ) }]
87-set cy_dout_min [expr { - ( $cy_dout_extra_hold + 4.5 ) }]
83+set cy_slrd_min [expr { - ( $cy_out_hold_margin + 3.7 ) }]
84+set cy_slwr_min [expr { - ( $cy_out_hold_margin + 3.6 ) }]
85+set cy_pend_min [expr { - ( $cy_out_hold_margin + 2.5 ) }]
86+set cy_fadr_min [expr { - ( $cy_out_hold_margin + 10 ) }]
87+set cy_dout_min [expr { - ( $cy_dout_hold_margin + 4.5 ) }]
88+
89+# max in delay = max output time + margin
90+set cy_flags_max [expr { $cy_flg_setup_margin + 13.5 }]
91+# min in delay = min output time - margin
92+set cy_flags_min 0
93+
94+# setup = Din setup + SLOE_to_data_ON + margin
95+set cy_sloe_max [expr { $cy_out_setup_margin + $cy_din_setup + 10.5 }]
96+# hold = Din hold - SLOE_to_data_OFF_min + margin
97+set cy_sloe_min [expr { - ( $cy_out_hold_margin + $cy_din_hold - 8.0 ) }]
98+
99+# max in delay = max output time + margin
100+set cy_din_max [expr { $CLK_period - $cy_din_setup + $cy_din_setup_margin }]
101+# min in delay = min output time - margin
102+set cy_din_min [expr { $cy_din_hold - $cy_din_hold_margin }]
88103
89104 # assume SLRD,SLWR,PKTEND are driven 1.5 cycle ahead and removed 0.5 cycle later
90105 set_multicycle_path -setup -start 2 -from $clk -to $usb_slrd
@@ -98,26 +113,14 @@
98113 # assume FIFOADR is driven 2 cycles ahead, and removed 1 cycle later
99114 set_multicycle_path -setup -start 3 -from $clk -to $usb_fifoadr
100115 set_multicycle_path -hold -start 3 -from $clk -to $usb_fifoadr
116+# assume SLOE is driven 2 cycle ahead
117+set_multicycle_path -setup -start 2 -from $clk -to $usb_sloe
118+set_multicycle_path -hold -start 1 -from $clk -to $usb_sloe
101119
102120 # FLAGx captured one cycle later
103121 set_multicycle_path -setup -end 2 -from $usb_flags -to $clk
104122 set_multicycle_path -hold -end 1 -from $usb_flags -to $clk
105123
106-# max in delay = max output time + margin
107-set cy_flags_max [expr { $cy_flg_setup_margin + 13.5 }]
108-# min in delay = min output time - margin
109-set cy_flags_min 0
110-
111-# setup = Din setup + SLOE_to_data_ON + margin
112-set cy_sloe_max [expr { $cy_out_extra_setup + $cy_din_setup + 10.5 }]
113-# hold = Din hold - SLOE_to_data_OFF_min + margin
114-set cy_sloe_min [expr { - ( $cy_out_extra_hold + $cy_din_hold - 8.0 ) }]
115-
116-# max in delay = max output time + margin
117-set cy_din_max [expr { $CLK_period - $cy_din_setup + $cy_din_setup_margin }]
118-# min in delay = min output time - margin
119-set cy_din_min [expr { $cy_din_hold - $cy_din_hold_margin }]
120-
121124 if 1 {
122125 set_output_delay -clock ifclk -max $cy_slrd_max $usb_slrd
123126 set_output_delay -clock ifclk -min $cy_slrd_min $usb_slrd
@@ -133,18 +136,28 @@
133136 set_output_delay -clock ifclk -min $cy_dout_min $usb_data
134137 }
135138
136-if 0 {
139+if 1 {
140+if $din_rel_to_clk {
141+set_output_delay -clock $din_clk -clock_fall -max $cy_sloe_max $usb_sloe
142+set_output_delay -clock $din_clk -clock_fall -min $cy_sloe_min $usb_sloe
143+} else {
137144 set_output_delay -clock $din_clk -max $cy_sloe_max $usb_sloe
138145 set_output_delay -clock $din_clk -min $cy_sloe_min $usb_sloe
139146 }
147+}
140148
141149 if 1 {
142150 set_input_delay -clock ifclk -max $cy_flags_max $usb_flags
143151 set_input_delay -clock ifclk -min $cy_flags_min $usb_flags
144152
153+if $din_rel_to_clk {
154+set_input_delay -clock $din_clk -clock_fall -max $cy_din_max $usb_data
155+set_input_delay -clock $din_clk -clock_fall -min $cy_din_min $usb_data
156+} else {
145157 set_input_delay -clock $din_clk -max $cy_din_max $usb_data
146158 set_input_delay -clock $din_clk -min $cy_din_min $usb_data
147159 }
160+}
148161
149162
150163 #######
diff -r 6ae688c6805a -r f59d81af1ec8 ep3/cy_max_test.v
--- a/ep3/cy_max_test.v Thu Nov 22 20:41:00 2018 +0000
+++ b/ep3/cy_max_test.v Fri Nov 23 11:30:57 2018 +0000
@@ -149,7 +149,6 @@
149149 begin
150150 usb_ifclk_o <= ifclk_next;
151151
152- usb_sloe_n_o <= sloe_n_next;
153152 usb_fifoadr_o <= fifoadr_next;
154153 end
155154
@@ -158,6 +157,8 @@
158157 usb_slrd_n_o <= slrd_n_next;
159158 usb_slwr_n_o <= slwr_n_next;
160159 usb_pktend_n_o <= pktend_n_next;
160+
161+ usb_sloe_n_o <= sloe_n_next;
161162 end
162163
163164 assign usb_ifclk = usb_ifclk_o;
@@ -185,7 +186,8 @@
185186
186187 // Cypress data input reg
187188 reg [15:0] usb_data_in;
188-always @(posedge clk)
189+//always @(posedge clk)
190+always @(negedge clk)
189191 begin
190192 if (usb_data_rd) begin
191193 usb_data_in[ 7:0] <= usb_pb_io;
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