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digital oscilloscope


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Revisionad164e61b60f4d0d023dcc1c1893a63c2f0768b7 (tree)
Zeit2018-11-23 23:22:52
AutorPJ_WORK
CommiterPJ_WORK

Log Message

ep3/cy_max_test.sdc: SLOE rel to IFCLK

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Diff

diff -r f59d81af1ec8 -r ad164e61b60f ep3/cy_max_test.sdc
--- a/ep3/cy_max_test.sdc Fri Nov 23 11:30:57 2018 +0000
+++ b/ep3/cy_max_test.sdc Fri Nov 23 14:22:52 2018 +0000
@@ -51,25 +51,25 @@
5151 set cy_flg_setup_margin 2.5
5252 set cy_din_hold_margin 0.5
5353
54-set din_rel_to_clk 1
54+set din_rel_to_clk 0
5555 if $din_rel_to_clk {
56-set din_clk $clk
5756 # (desired) Din setup (rel to clk)
5857 set cy_din_setup 1.0
5958 set cy_din_setup_margin 1.0
59+set cy_sloe_setup_margin 1.0
6060 # (desired) Din hold (rel to clk)
6161 #set cy_din_hold 3.0
6262 #set cy_din_hold 5.0
6363 set cy_din_hold 10.0
6464 } else {
65-set din_clk ifclk
6665 # (desired) Din setup (rel to ifclk)
67-#set cy_din_setup 10.7
68-set cy_din_setup 8.0
69-set cy_din_setup_margin 0.5
66+#set cy_din_setup 4.0
67+set cy_din_setup 4.9
68+set cy_din_setup_margin 0.0
69+set cy_sloe_setup_margin 0.0
7070 # (desired) Din hold (rel to ifclk)
71-#set cy_din_hold -1.0
72-set cy_din_hold -2.0
71+set cy_din_hold -1.0
72+#set cy_din_hold -2.0
7373 }
7474
7575 # max out delay = setup + margin
@@ -92,12 +92,16 @@
9292 set cy_flags_min 0
9393
9494 # setup = Din setup + SLOE_to_data_ON + margin
95-set cy_sloe_max [expr { $cy_out_setup_margin + $cy_din_setup + 10.5 }]
95+set cy_sloe_max [expr { $cy_sloe_setup_margin + $cy_din_setup + 10.5 }]
9696 # hold = Din hold - SLOE_to_data_OFF_min + margin
9797 set cy_sloe_min [expr { - ( $cy_out_hold_margin + $cy_din_hold - 8.0 ) }]
9898
9999 # max in delay = max output time + margin
100-set cy_din_max [expr { $CLK_period - $cy_din_setup + $cy_din_setup_margin }]
100+if $din_rel_to_clk {
101+#set cy_din_max [expr { $CLK_period - $cy_din_setup + $cy_din_setup_margin }]
102+} else {
103+set cy_din_max [expr { $CLK_period/2 - $cy_din_setup + $cy_din_setup_margin }]
104+}
101105 # min in delay = min output time - margin
102106 set cy_din_min [expr { $cy_din_hold - $cy_din_hold_margin }]
103107
@@ -113,7 +117,7 @@
113117 # assume FIFOADR is driven 2 cycles ahead, and removed 1 cycle later
114118 set_multicycle_path -setup -start 3 -from $clk -to $usb_fifoadr
115119 set_multicycle_path -hold -start 3 -from $clk -to $usb_fifoadr
116-# assume SLOE is driven 2 cycle ahead
120+# assume SLOE is driven 2 cycle ahead of rd DATA capture
117121 set_multicycle_path -setup -start 2 -from $clk -to $usb_sloe
118122 set_multicycle_path -hold -start 1 -from $clk -to $usb_sloe
119123
@@ -138,25 +142,21 @@
138142
139143 if 1 {
140144 if $din_rel_to_clk {
141-set_output_delay -clock $din_clk -clock_fall -max $cy_sloe_max $usb_sloe
142-set_output_delay -clock $din_clk -clock_fall -min $cy_sloe_min $usb_sloe
145+ set_output_delay -clock $clk -clock_fall -max $cy_sloe_max $usb_sloe
146+ set_output_delay -clock $clk -clock_fall -min $cy_sloe_min $usb_sloe
147+ set_input_delay -clock $clk -clock_fall -max $cy_din_max $usb_data
148+ set_input_delay -clock $clk -clock_fall -min $cy_din_min $usb_data
143149 } else {
144-set_output_delay -clock $din_clk -max $cy_sloe_max $usb_sloe
145-set_output_delay -clock $din_clk -min $cy_sloe_min $usb_sloe
150+ set_output_delay -clock ifclk -max $cy_sloe_max $usb_sloe
151+ set_output_delay -clock ifclk -min $cy_sloe_min $usb_sloe
152+ set_input_delay -clock ifclk -max $cy_din_max $usb_data
153+ set_input_delay -clock ifclk -min $cy_din_min $usb_data
146154 }
147155 }
148156
149157 if 1 {
150158 set_input_delay -clock ifclk -max $cy_flags_max $usb_flags
151159 set_input_delay -clock ifclk -min $cy_flags_min $usb_flags
152-
153-if $din_rel_to_clk {
154-set_input_delay -clock $din_clk -clock_fall -max $cy_din_max $usb_data
155-set_input_delay -clock $din_clk -clock_fall -min $cy_din_min $usb_data
156-} else {
157-set_input_delay -clock $din_clk -max $cy_din_max $usb_data
158-set_input_delay -clock $din_clk -min $cy_din_min $usb_data
159-}
160160 }
161161
162162
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