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digital oscilloscope


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Revisiona03dc92c6cfb1ea38ba4efa25c9a4761ccc6eccd (tree)
Zeit2018-11-23 05:14:23
AutorPJ
CommiterPJ

Log Message

ep3/cy_max_test: SLRD/WR ok

Ändern Zusammenfassung

Diff

diff -r 9fe2d3fc7988 -r a03dc92c6cfb ep3/cy_max_test.sdc
--- a/ep3/cy_max_test.sdc Thu Nov 22 19:36:22 2018 +0000
+++ b/ep3/cy_max_test.sdc Thu Nov 22 20:14:23 2018 +0000
@@ -92,18 +92,20 @@
9292 set cy_fadr_min [expr { - ( $cy_out_extra_hold + 10 ) }]
9393 set cy_dout_min [expr { - ( $cy_out_extra_hold + 4.5 ) }]
9494
95-# outputs held for one extra CLK cycle by the state machine
96-#set_multicycle_path -hold -start 1 -from $clk -to $usb_slrd
97-#set_multicycle_path -hold -start 1 -from $clk -to $usb_slwr
98-#set_multicycle_path -hold -start 1 -from $clk -to $usb_pktend
99-#set_multicycle_path -hold -start 1 -from $clk -to $usb_data
100-# assume FIFOADR is driven 1 cycle ahead
101-set_multicycle_path -setup -start 2 -from $clk -to $usb_fifoadr
102-set_multicycle_path -hold -start 2 -from $clk -to $usb_fifoadr
95+# assume SLRD,SLWR,PKTEND are driven 1.5 cycle ahead and removed 0.5 cycle later
96+set_multicycle_path -setup -start 2 -from $clk -to $usb_slrd
97+set_multicycle_path -hold -start 1 -from $clk -to $usb_slrd
98+set_multicycle_path -setup -start 2 -from $clk -to $usb_slwr
99+set_multicycle_path -hold -start 1 -from $clk -to $usb_slwr
100+set_multicycle_path -setup -start 2 -from $clk -to $usb_pktend
101+set_multicycle_path -hold -start 1 -from $clk -to $usb_pktend
102+# assume FIFOADR is driven 2 cycles ahead, and removed 1 cycle later
103+set_multicycle_path -setup -start 3 -from $clk -to $usb_fifoadr
104+set_multicycle_path -hold -start 3 -from $clk -to $usb_fifoadr
103105
104106 # FLAGx captured one cycle later
105107 set_multicycle_path -setup -end 2 -from $usb_flags -to $clk
106-set_multicycle_path -hold -end 2 -from $usb_flags -to $clk
108+set_multicycle_path -hold -end 1 -from $usb_flags -to $clk
107109
108110 # max in delay = max output time + margin
109111 set cy_flags_max [expr { $cy_flg_setup_margin + 13.5 }]
@@ -120,7 +122,7 @@
120122 # min in delay = min output time - margin
121123 set cy_din_min [expr { $cy_din_hold - $cy_din_hold_margin }]
122124
123-if 0 {
125+if 1 {
124126 set_output_delay -clock ifclk -max $cy_slrd_max $usb_slrd
125127 set_output_delay -clock ifclk -min $cy_slrd_min $usb_slrd
126128 set_output_delay -clock ifclk -max $cy_slwr_max $usb_slwr
@@ -129,6 +131,8 @@
129131 set_output_delay -clock ifclk -min $cy_pend_min $usb_pktend
130132 set_output_delay -clock ifclk -max $cy_fadr_max $usb_fifoadr
131133 set_output_delay -clock ifclk -min $cy_fadr_min $usb_fifoadr
134+}
135+if 0 {
132136 set_output_delay -clock ifclk -max $cy_dout_max $usb_data
133137 set_output_delay -clock ifclk -min $cy_dout_min $usb_data
134138 }
diff -r 9fe2d3fc7988 -r a03dc92c6cfb ep3/cy_max_test.v
--- a/ep3/cy_max_test.v Thu Nov 22 19:36:22 2018 +0000
+++ b/ep3/cy_max_test.v Thu Nov 22 20:14:23 2018 +0000
@@ -148,18 +148,18 @@
148148 always @(posedge clk)
149149 begin
150150 usb_ifclk_o <= ifclk_next;
151+
152+ usb_sloe_n_o <= sloe_n_next;
153+ usb_fifoadr_o <= fifoadr_next;
154+end
155+
156+always @(negedge clk)
157+begin
151158 usb_slrd_n_o <= slrd_n_next;
152159 usb_slwr_n_o <= slwr_n_next;
153- usb_sloe_n_o <= sloe_n_next;
154160 usb_pktend_n_o <= pktend_n_next;
155161 end
156162
157-//always @(negedge clk)
158-always @(posedge clk)
159-begin
160- usb_fifoadr_o <= fifoadr_next;
161-end
162-
163163 //assign usb_ifclk = clk;
164164 assign usb_ifclk = usb_ifclk_o;
165165
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