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digital oscilloscope


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Revision9fe2d3fc7988b3cc61ce1449ed646a34399de9f3 (tree)
Zeit2018-11-23 04:36:22
AutorPJ
CommiterPJ

Log Message

ep3/cy_max_test: IFCLK=CLK/2

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diff -r 5d95eb57c0c7 -r 9fe2d3fc7988 ep3/cy_max_test.sdc
--- a/ep3/cy_max_test.sdc Wed Nov 21 21:20:42 2018 +0000
+++ b/ep3/cy_max_test.sdc Thu Nov 22 19:36:22 2018 +0000
@@ -10,12 +10,12 @@
1010 set clk { i_pll|auto_generated|pll1|clk[0] }
1111
1212 # IFCLK, internal
13-#set ifclk_int_loc [get_pins cy_io|usb_ifclk_o|q ]
14-#create_generated_clock -name ifclk_int -source $clk -edges { 1 9 17 } $ifclk_int_loc
13+set ifclk_int_loc [get_pins usb_ifclk_o|q ]
14+create_generated_clock -name ifclk_int -source $clk -edges { 1 3 5 } $ifclk_int_loc
1515
1616 # IFCLK, output
17-create_generated_clock -name ifclk -source $clk [get_ports usb_ifclk ]
18-#create_generated_clock -name ifclk -source $ifclk_int_loc [get_ports usb_ifclk ]
17+#create_generated_clock -name ifclk -source $clk [get_ports usb_ifclk ]
18+create_generated_clock -name ifclk -source $ifclk_int_loc [get_ports usb_ifclk ]
1919
2020 # Slave FIFO Synchronous Read/Write Parameters with Externally Sourced IFCLK
2121 # IFCLK = CLK/2
@@ -23,13 +23,17 @@
2323 set CLK_period [get_clock_info -period $clk ]
2424 set IFCLK_period [get_clock_info -period ifclk ]
2525
26-# test if IFCLK output delay can be influenced
27-# without constrains: max: 7.432/7.334, min: 3.460/3.506
28-# with constrains: the same
29-#set ifclk_del_min -1.0
30-#set ifclk_del_max [expr {$CLK_period / 2 - 5.0}]
31-#set_output_delay -clock $clk -min $ifclk_del_min [get_ports { usb_ifclk }]
32-#set_output_delay -clock $clk -max $ifclk_del_max [get_ports { usb_ifclk }]
26+# can IFCLK output delay can be influenced?
27+# a) IFCLK source: clk
28+# without constrains: max: 7.432/7.334, min: 3.460/3.506
29+# with constrains: the same
30+# b) IFCLK source: FF(clk)
31+# without constrains: max: 8.670/8.582, min: 3.954/3.994
32+# with constrains: max: 8.227/8.162, min: 3.811/3.802 (loc in DDIOOUTCELL)
33+set ifclk_del_min -1.0
34+set ifclk_del_max [expr {$CLK_period - 7.0}]
35+set_output_delay -clock $clk -min $ifclk_del_min [get_ports { usb_ifclk }]
36+set_output_delay -clock $clk -max $ifclk_del_max [get_ports { usb_ifclk }]
3337
3438 set usb_data [get_ports { usb_pb_io* usb_pd_io* }]
3539 set usb_slrd [get_ports usb_slrd_n_o ]
@@ -45,20 +49,24 @@
4549 #set cy_out_extra_hold 1.0
4650 set cy_out_extra_hold 0.5
4751 set cy_flg_setup_margin 2.0
48-set cy_din_setup_margin 0.5
4952 set cy_din_hold_margin 0.5
5053
5154 set din_rel_to_clk 1
5255 if $din_rel_to_clk {
56+set din_clk $clk
5357 # (desired) Din setup (rel to clk)
54-set cy_din_setup 2.0
58+#set cy_din_setup 2.0
59+set cy_din_setup 1.0
60+set cy_din_setup_margin 1.0
5561 # (desired) Din hold (rel to clk)
56-#set cy_din_hold 1.0
57-set cy_din_hold 3.0
62+#set cy_din_hold 3.0
63+set cy_din_hold 5.0
5864 } else {
65+set din_clk ifclk
5966 # (desired) Din setup (rel to ifclk)
6067 #set cy_din_setup 10.7
6168 set cy_din_setup 8.0
69+set cy_din_setup_margin 0.5
6270 # (desired) Din hold (rel to ifclk)
6371 #set cy_din_hold -1.0
6472 set cy_din_hold -2.0
@@ -93,6 +101,10 @@
93101 set_multicycle_path -setup -start 2 -from $clk -to $usb_fifoadr
94102 set_multicycle_path -hold -start 2 -from $clk -to $usb_fifoadr
95103
104+# FLAGx captured one cycle later
105+set_multicycle_path -setup -end 2 -from $usb_flags -to $clk
106+set_multicycle_path -hold -end 2 -from $usb_flags -to $clk
107+
96108 # max in delay = max output time + margin
97109 set cy_flags_max [expr { $cy_flg_setup_margin + 13.5 }]
98110 # min in delay = min output time - margin
@@ -121,27 +133,17 @@
121133 set_output_delay -clock ifclk -min $cy_dout_min $usb_data
122134 }
123135
124-if 1 {
125-if $din_rel_to_clk {
126-set_output_delay -clock $clk -max $cy_sloe_max $usb_sloe
127-set_output_delay -clock $clk -min $cy_sloe_min $usb_sloe
128-} else {
129-set_output_delay -clock ifclk -max $cy_sloe_max $usb_sloe
130-set_output_delay -clock ifclk -min $cy_sloe_min $usb_sloe
131-}
136+if 0 {
137+set_output_delay -clock $din_clk -max $cy_sloe_max $usb_sloe
138+set_output_delay -clock $din_clk -min $cy_sloe_min $usb_sloe
132139 }
133140
134141 if 1 {
135142 set_input_delay -clock ifclk -max $cy_flags_max $usb_flags
136143 set_input_delay -clock ifclk -min $cy_flags_min $usb_flags
137144
138-if $din_rel_to_clk {
139-set_input_delay -clock $clk -max $cy_din_max $usb_data
140-set_input_delay -clock $clk -min $cy_din_min $usb_data
141-} else {
142-set_input_delay -clock ifclk -max $cy_din_max $usb_data
143-set_input_delay -clock ifclk -min $cy_din_min $usb_data
144-}
145+set_input_delay -clock $din_clk -max $cy_din_max $usb_data
146+set_input_delay -clock $din_clk -min $cy_din_min $usb_data
145147 }
146148
147149
diff -r 5d95eb57c0c7 -r 9fe2d3fc7988 ep3/cy_max_test.v
--- a/ep3/cy_max_test.v Wed Nov 21 21:20:42 2018 +0000
+++ b/ep3/cy_max_test.v Thu Nov 22 19:36:22 2018 +0000
@@ -1,4 +1,4 @@
1-// Cypress Slave FIFO max throughput test
1+// Cypress Slave FIFO timing test with 48MHz IFCLK
22 // using EEG32 PCB with EP3C5 + Cypress
33 // © Copyright 2018 Pawel Jewstafjew Pawel<dot>Jewstafjew<at>gmail<dot>com
44
@@ -77,7 +77,8 @@
7777 .operation_mode ("NO_COMPENSATION"), // internal PLL feedback, jitter is minimized
7878 .bandwidth_type ("LOW"), // reduce jitter (?)
7979 .inclk0_input_frequency (83333), // 12MHz, period in ps
80- .clk0_divide_by (1), .clk0_multiply_by (4) // 48MHz
80+// .clk0_divide_by (1), .clk0_multiply_by (4) // 48MHz
81+ .clk0_divide_by (1), .clk0_multiply_by (8) // 96MHz
8182 ) i_pll (
8283 .inclk (pll_clk_in), // PLL clock input
8384 .clk (pll_clk_out), // PLL clock output
@@ -153,13 +154,15 @@
153154 usb_pktend_n_o <= pktend_n_next;
154155 end
155156
156-always @(negedge clk)
157+//always @(negedge clk)
158+always @(posedge clk)
157159 begin
158160 usb_fifoadr_o <= fifoadr_next;
159161 end
160162
161-assign usb_ifclk = clk;
162-//assign usb_ifclk = usb_ifclk_o;
163+//assign usb_ifclk = clk;
164+assign usb_ifclk = usb_ifclk_o;
165+
163166 assign usb_pa2 = usb_sloe_n_o;
164167 assign usb_pa4 = usb_fifoadr_o[0];
165168 assign usb_pa5 = usb_fifoadr_o[1];
@@ -170,8 +173,8 @@
170173 // Cypress data output reg
171174 reg [15:0] usb_data_out;
172175 reg usb_data_oe;
173-//always @(posedge clk)
174-always @(negedge clk)
176+always @(posedge clk)
177+//always @(negedge clk)
175178 begin
176179 usb_data_oe <= data_oe_next;
177180 if (usb_data_wr)
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