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digital oscilloscope

ep3/cy_max_test: IFCLK=CLK/2

diff -r 5d95eb57c0c7 -r 9fe2d3fc7988 ep3/cy_max_test.sdc

--- a/ep3/cy_max_test.sdc Wed Nov 21 21:20:42 2018 +0000

+++ b/ep3/cy_max_test.sdc Thu Nov 22 19:36:22 2018 +0000

		@@ -10,12 +10,12 @@
10	10	set clk { i_pll\|auto_generated\|pll1\|clk[0] }
11	11
12	12	# IFCLK, internal
13		-#set ifclk_int_loc [get_pins cy_io\|usb_ifclk_o\|q ]
14		-#create_generated_clock -name ifclk_int -source $clk -edges { 1 9 17 } $ifclk_int_loc
	13	+set ifclk_int_loc [get_pins usb_ifclk_o\|q ]
	14	+create_generated_clock -name ifclk_int -source $clk -edges { 1 3 5 } $ifclk_int_loc
15	15
16	16	# IFCLK, output
17		-create_generated_clock -name ifclk -source $clk [get_ports usb_ifclk ]
18		-#create_generated_clock -name ifclk -source $ifclk_int_loc [get_ports usb_ifclk ]
	17	+#create_generated_clock -name ifclk -source $clk [get_ports usb_ifclk ]
	18	+create_generated_clock -name ifclk -source $ifclk_int_loc [get_ports usb_ifclk ]
19	19
20	20	# Slave FIFO Synchronous Read/Write Parameters with Externally Sourced IFCLK
21	21	# IFCLK = CLK/2

		@@ -23,13 +23,17 @@
23	23	set CLK_period [get_clock_info -period $clk ]
24	24	set IFCLK_period [get_clock_info -period ifclk ]
25	25
26		-# test if IFCLK output delay can be influenced
27		-# without constrains: max: 7.432/7.334, min: 3.460/3.506
28		-# with constrains: the same
29		-#set ifclk_del_min -1.0
30		-#set ifclk_del_max [expr {$CLK_period / 2 - 5.0}]
31		-#set_output_delay -clock $clk -min $ifclk_del_min [get_ports { usb_ifclk }]
32		-#set_output_delay -clock $clk -max $ifclk_del_max [get_ports { usb_ifclk }]
	26	+# can IFCLK output delay can be influenced?
	27	+# a) IFCLK source: clk
	28	+# without constrains: max: 7.432/7.334, min: 3.460/3.506
	29	+# with constrains: the same
	30	+# b) IFCLK source: FF(clk)
	31	+# without constrains: max: 8.670/8.582, min: 3.954/3.994
	32	+# with constrains: max: 8.227/8.162, min: 3.811/3.802 (loc in DDIOOUTCELL)
	33	+set ifclk_del_min -1.0
	34	+set ifclk_del_max [expr {$CLK_period - 7.0}]
	35	+set_output_delay -clock $clk -min $ifclk_del_min [get_ports { usb_ifclk }]
	36	+set_output_delay -clock $clk -max $ifclk_del_max [get_ports { usb_ifclk }]
33	37
34	38	set usb_data [get_ports { usb_pb_io* usb_pd_io* }]
35	39	set usb_slrd [get_ports usb_slrd_n_o ]

		@@ -45,20 +49,24 @@
45	49	#set cy_out_extra_hold 1.0
46	50	set cy_out_extra_hold 0.5
47	51	set cy_flg_setup_margin 2.0
48		-set cy_din_setup_margin 0.5
49	52	set cy_din_hold_margin 0.5
50	53
51	54	set din_rel_to_clk 1
52	55	if $din_rel_to_clk {
	56	+set din_clk $clk
53	57	# (desired) Din setup (rel to clk)
54		-set cy_din_setup 2.0
	58	+#set cy_din_setup 2.0
	59	+set cy_din_setup 1.0
	60	+set cy_din_setup_margin 1.0
55	61	# (desired) Din hold (rel to clk)
56		-#set cy_din_hold 1.0
57		-set cy_din_hold 3.0
	62	+#set cy_din_hold 3.0
	63	+set cy_din_hold 5.0
58	64	} else {
	65	+set din_clk ifclk
59	66	# (desired) Din setup (rel to ifclk)
60	67	#set cy_din_setup 10.7
61	68	set cy_din_setup 8.0
	69	+set cy_din_setup_margin 0.5
62	70	# (desired) Din hold (rel to ifclk)
63	71	#set cy_din_hold -1.0
64	72	set cy_din_hold -2.0

		@@ -93,6 +101,10 @@
93	101	set_multicycle_path -setup -start 2 -from $clk -to $usb_fifoadr
94	102	set_multicycle_path -hold -start 2 -from $clk -to $usb_fifoadr
95	103
	104	+# FLAGx captured one cycle later
	105	+set_multicycle_path -setup -end 2 -from $usb_flags -to $clk
	106	+set_multicycle_path -hold -end 2 -from $usb_flags -to $clk
	107	+
96	108	# max in delay = max output time + margin
97	109	set cy_flags_max [expr { $cy_flg_setup_margin + 13.5 }]
98	110	# min in delay = min output time - margin

		@@ -121,27 +133,17 @@
121	133	set_output_delay -clock ifclk -min $cy_dout_min $usb_data
122	134	}
123	135
124		-if 1 {
125		-if $din_rel_to_clk {
126		-set_output_delay -clock $clk -max $cy_sloe_max $usb_sloe
127		-set_output_delay -clock $clk -min $cy_sloe_min $usb_sloe
128		-} else {
129		-set_output_delay -clock ifclk -max $cy_sloe_max $usb_sloe
130		-set_output_delay -clock ifclk -min $cy_sloe_min $usb_sloe
131		-}
	136	+if 0 {
	137	+set_output_delay -clock $din_clk -max $cy_sloe_max $usb_sloe
	138	+set_output_delay -clock $din_clk -min $cy_sloe_min $usb_sloe
132	139	}
133	140
134	141	if 1 {
135	142	set_input_delay -clock ifclk -max $cy_flags_max $usb_flags
136	143	set_input_delay -clock ifclk -min $cy_flags_min $usb_flags
137	144
138		-if $din_rel_to_clk {
139		-set_input_delay -clock $clk -max $cy_din_max $usb_data
140		-set_input_delay -clock $clk -min $cy_din_min $usb_data
141		-} else {
142		-set_input_delay -clock ifclk -max $cy_din_max $usb_data
143		-set_input_delay -clock ifclk -min $cy_din_min $usb_data
144		-}
	145	+set_input_delay -clock $din_clk -max $cy_din_max $usb_data
	146	+set_input_delay -clock $din_clk -min $cy_din_min $usb_data
145	147	}
146	148
147	149

diff -r 5d95eb57c0c7 -r 9fe2d3fc7988 ep3/cy_max_test.v

--- a/ep3/cy_max_test.v Wed Nov 21 21:20:42 2018 +0000

+++ b/ep3/cy_max_test.v Thu Nov 22 19:36:22 2018 +0000

		@@ -1,4 +1,4 @@
1		-// Cypress Slave FIFO max throughput test
	1	+// Cypress Slave FIFO timing test with 48MHz IFCLK
2	2	// using EEG32 PCB with EP3C5 + Cypress
3	3	// © Copyright 2018 Pawel Jewstafjew Pawel<dot>Jewstafjew<at>gmail<dot>com
4	4

		@@ -77,7 +77,8 @@
77	77	.operation_mode ("NO_COMPENSATION"), // internal PLL feedback, jitter is minimized
78	78	.bandwidth_type ("LOW"), // reduce jitter (?)
79	79	.inclk0_input_frequency (83333), // 12MHz, period in ps
80		- .clk0_divide_by (1), .clk0_multiply_by (4) // 48MHz
	80	+// .clk0_divide_by (1), .clk0_multiply_by (4) // 48MHz
	81	+ .clk0_divide_by (1), .clk0_multiply_by (8) // 96MHz
81	82	) i_pll (
82	83	.inclk (pll_clk_in), // PLL clock input
83	84	.clk (pll_clk_out), // PLL clock output