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digital oscilloscope


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Revision9ec289b9b4fe0d3754d76c63836522d1c1ffce5a (tree)
Zeit2018-11-24 23:06:30
AutorPJ
CommiterPJ

Log Message

ep3/cy_max_test: rd DATA timing relative to SLOE

Ändern Zusammenfassung

Diff

diff -r 0e3db1460a3a -r 9ec289b9b4fe ep3/cy_max_test.sdc
--- a/ep3/cy_max_test.sdc Sat Nov 24 10:29:24 2018 +0000
+++ b/ep3/cy_max_test.sdc Sat Nov 24 14:06:30 2018 +0000
@@ -9,13 +9,28 @@
99 #set clk in_clk1
1010 set clk { i_pll|auto_generated|pll1|clk[0] }
1111
12+set usb_ifclk [get_ports usb_ifclk ]
13+set usb_sloe [get_ports usb_pa2 ]
14+set usb_data [get_ports { usb_pb_io* usb_pd_io* }]
15+set usb_slrd [get_ports usb_slrd_n_o ]
16+set usb_slwr [get_ports usb_slwr_n_o ]
17+set usb_pktend [get_ports usb_pa6 ]
18+set usb_fifoadr [get_ports { usb_pa4 usb_pa5 }]
19+set usb_flags [get_ports { usb_flaga_i usb_flagb_i usb_flagc_i }]
20+
1221 # IFCLK, internal
1322 set ifclk_int_loc [get_pins usb_ifclk_o|q ]
1423 create_generated_clock -name ifclk_int -source $clk -edges { 1 3 5 } $ifclk_int_loc
1524
1625 # IFCLK, output
17-#create_generated_clock -name ifclk -source $clk [get_ports usb_ifclk ]
18-create_generated_clock -name ifclk -source $ifclk_int_loc [get_ports usb_ifclk ]
26+#create_generated_clock -name ifclk -source $clk $usb_ifclk
27+create_generated_clock -name ifclk -source $ifclk_int_loc $usb_ifclk
28+
29+
30+# SLOE
31+set sloe_int_loc [get_pins usb_sloe_n_o|q ]
32+create_generated_clock -name sloe_int -source $clk -edges { 2 4 6 } $sloe_int_loc
33+create_generated_clock -name sloe_clk -source $sloe_int_loc $usb_sloe
1934
2035 # Slave FIFO Synchronous Read/Write Parameters with Externally Sourced IFCLK
2136 # IFCLK = CLK/2
@@ -30,18 +45,19 @@
3045 # b) IFCLK source: FF(clk)
3146 # without constrains: max: 8.670/8.582, min: 3.954/3.994
3247 # with constrains: max: 8.227/8.162, min: 3.811/3.802 (loc in DDIOOUTCELL)
48+
49+# output IFCLK as early as possible
3350 set ifclk_del_min -1.0
3451 set ifclk_del_max [expr {$CLK_period - 7.0}]
35-set_output_delay -clock $clk -min $ifclk_del_min [get_ports { usb_ifclk }]
36-set_output_delay -clock $clk -max $ifclk_del_max [get_ports { usb_ifclk }]
52+set_output_delay -clock $clk -min $ifclk_del_min $usb_ifclk
53+set_output_delay -clock $clk -max $ifclk_del_max $usb_ifclk
3754
38-set usb_data [get_ports { usb_pb_io* usb_pd_io* }]
39-set usb_slrd [get_ports usb_slrd_n_o ]
40-set usb_slwr [get_ports usb_slwr_n_o ]
41-set usb_sloe [get_ports usb_pa2 ]
42-set usb_pktend [get_ports usb_pa6 ]
43-set usb_fifoadr [get_ports { usb_pa4 usb_pa5 }]
44-set usb_flags [get_ports { usb_flaga_i usb_flagb_i usb_flagc_i }]
55+# output SLOE as early as possible
56+set sloe_del_min -1.0
57+set sloe_del_max [expr {$CLK_period - 7.1}]
58+set_output_delay -clock $clk -clock_fall -min $sloe_del_min $usb_sloe
59+set_output_delay -clock $clk -clock_fall -max $sloe_del_max $usb_sloe
60+
4561
4662 # margin
4763 set cy_out_setup_margin 1.0
@@ -49,26 +65,14 @@
4965 set cy_dout_setup_margin 5.0
5066 set cy_dout_hold_margin 2.0
5167 set cy_flg_setup_margin 2.5
52-set cy_din_hold_margin 0.5
68+#set cy_din_hold_margin 0.5
69+set cy_din_setup_margin 0.485 ;# sum of SLOE out & DATA in delays
70+#set cy_din_setup_margin 0.5
5371
54-set din_rel_to_clk 1
55-if $din_rel_to_clk {
5672 # (desired) Din setup (rel to clk)
57-set cy_din_setup 1.0
58-set cy_din_setup_margin 1.5
59-set cy_sloe_setup_margin 1.5
6073 # (desired) Din hold (rel to clk)
6174 set cy_din_hold 6.0
6275 #set cy_din_hold 10.0
63-} else {
64-# (desired) Din setup (rel to ifclk)
65-set cy_din_setup 4.9
66-set cy_din_setup_margin 0.0
67-set cy_sloe_setup_margin 0.0
68-# (desired) Din hold (rel to ifclk)
69-set cy_din_hold -1.0
70-#set cy_din_hold -2.0
71-}
7276
7377 # max out delay = setup + margin
7478 set cy_slrd_max [expr { $cy_out_setup_margin + 12.7 }]
@@ -89,20 +93,11 @@
8993 # min in delay = min output time - margin
9094 set cy_flags_min 0
9195
92-# setup = Din setup + SLOE_to_data_ON + margin
93-set cy_sloe_max [expr { $cy_sloe_setup_margin + $cy_din_setup + 10.5 }]
94-# hold = Din hold - SLOE_to_data_OFF_min + margin
95-set cy_sloe_min [expr { - ( $cy_out_hold_margin + $cy_din_hold - 5.0 ) }]
96-
97-# max in delay = max output time + margin
98-if $din_rel_to_clk {
99-set cy_din_max [expr { $CLK_period - $cy_din_setup + $cy_din_setup_margin }]
100-} else {
101-set cy_din_max [expr { $CLK_period/2 - $cy_din_setup + $cy_din_setup_margin }]
102-}
96+# max in delay (rel to SLOE) = SLOE_to_data_ON + margin
97+set cy_din_max [expr { 10.5 + $cy_din_setup_margin }]
10398 # min in delay = min output time - margin
10499 #set cy_din_min [expr { $cy_din_hold - $cy_din_hold_margin }]
105-set cy_din_min [expr { $cy_din_hold - $cy_din_hold_margin + $CLK_period}]
100+set cy_din_min 0
106101
107102 # assume SLRD,SLWR,PKTEND are driven 1.5 cycle ahead and removed 0.5 cycle later
108103 set_multicycle_path -setup -start 2 -from $clk -to $usb_slrd
@@ -117,13 +112,16 @@
117112 set_multicycle_path -setup -start 3 -from $clk -to $usb_fifoadr
118113 set_multicycle_path -hold -start 3 -from $clk -to $usb_fifoadr
119114 # assume SLOE is driven 2 cycle ahead of rd DATA capture
120-set_multicycle_path -setup -start 2 -from $clk -to $usb_sloe
121-set_multicycle_path -hold -start 1 -from $clk -to $usb_sloe
115+#set_multicycle_path -setup -start 2 -from $clk -to $usb_sloe
116+#set_multicycle_path -hold -start 1 -from $clk -to $usb_sloe
122117
123118 # FLAGx captured one cycle later
124119 set_multicycle_path -setup -end 2 -from $usb_flags -to $clk
125120 set_multicycle_path -hold -end 1 -from $usb_flags -to $clk
126121
122+set_multicycle_path -setup -end 2 -from $usb_data -to $clk
123+set_multicycle_path -hold -end 1 -from $usb_data -to $clk
124+
127125 if 1 {
128126 set_output_delay -clock ifclk -max $cy_slrd_max $usb_slrd
129127 set_output_delay -clock ifclk -min $cy_slrd_min $usb_slrd
@@ -140,25 +138,19 @@
140138 }
141139
142140 if 1 {
143-if $din_rel_to_clk {
144- set_output_delay -clock $clk -clock_fall -max $cy_sloe_max $usb_sloe
145- set_output_delay -clock $clk -clock_fall -min $cy_sloe_min $usb_sloe
146- set_input_delay -clock $clk -clock_fall -max $cy_din_max $usb_data
147- set_input_delay -clock $clk -clock_fall -min $cy_din_min $usb_data
141+#set_multicycle_path -setup -end 0 -from $usb_data -to $clk
142+# set_output_delay -clock $clk -max $cy_sloe_max $usb_sloe
143+# set_output_delay -clock $clk -min $cy_sloe_min $usb_sloe
144+ set_input_delay -clock sloe_clk -max $cy_din_max $usb_data
145+ set_input_delay -clock sloe_clk -min $cy_din_min $usb_data
146+}
148147 # ensure data in capture before rising edge of IFCLK
149148 #FIXME
150149 #set_multicycle_path -hold -end -1 -from ifclk -to $usb_data
151150 #set_multicycle_path -hold -end -1 -from ifclk -through $usb_data -to $clk
152-set_multicycle_path -hold -end -1 -from $usb_data -to $clk
153- set_input_delay -add_delay -clock ifclk -min 0 $usb_data
154- set_input_delay -add_delay -clock ifclk -max -10 $usb_data
155-} else {
156- set_output_delay -clock ifclk -max $cy_sloe_max $usb_sloe
157- set_output_delay -clock ifclk -min $cy_sloe_min $usb_sloe
158- set_input_delay -clock ifclk -max $cy_din_max $usb_data
159- set_input_delay -clock ifclk -min $cy_din_min $usb_data
160-}
161-}
151+#set_multicycle_path -hold -end -1 -from $usb_data -to $clk
152+# set_input_delay -add_delay -clock ifclk -min 0 $usb_data
153+# set_input_delay -add_delay -clock ifclk -max -10 $usb_data
162154
163155 if 1 {
164156 set_input_delay -clock ifclk -max $cy_flags_max $usb_flags
diff -r 0e3db1460a3a -r 9ec289b9b4fe ep3/cy_max_test.v
--- a/ep3/cy_max_test.v Sat Nov 24 10:29:24 2018 +0000
+++ b/ep3/cy_max_test.v Sat Nov 24 14:06:30 2018 +0000
@@ -186,8 +186,8 @@
186186
187187 // Cypress data input reg
188188 reg [15:0] usb_data_in;
189-//always @(posedge clk)
190-always @(negedge clk)
189+always @(posedge clk)
190+//always @(negedge clk)
191191 begin
192192 if (usb_data_rd) begin
193193 usb_data_in[ 7:0] <= usb_pb_io;
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