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digital oscilloscope


Commit MetaInfo

Revision6ae688c6805ae56001ef99f5964b26751b019020 (tree)
Zeit2018-11-23 05:41:00
AutorPJ
CommiterPJ

Log Message

ep3/cy_max_test: DATA out ok

Ändern Zusammenfassung

Diff

diff -r a03dc92c6cfb -r 6ae688c6805a ep3/cy_max_test.sdc
--- a/ep3/cy_max_test.sdc Thu Nov 22 20:14:23 2018 +0000
+++ b/ep3/cy_max_test.sdc Thu Nov 22 20:41:00 2018 +0000
@@ -45,9 +45,9 @@
4545
4646 # margin
4747 set cy_out_extra_setup 1.0
48-set cy_dout_extra_setup 2.0
49-#set cy_out_extra_hold 1.0
5048 set cy_out_extra_hold 0.5
49+set cy_dout_extra_setup 5.0
50+set cy_dout_extra_hold 2.0
5151 set cy_flg_setup_margin 2.0
5252 set cy_din_hold_margin 0.5
5353
@@ -80,17 +80,11 @@
8080 set cy_dout_max [expr { $cy_dout_extra_setup + 3.2 }]
8181
8282 # min out delay = - (hold + margin)
83-#set cy_slrd_min [expr { $CLK_period - ( $cy_out_extra_hold + 3.7 ) }]
84-#set cy_slwr_min [expr { $CLK_period - ( $cy_out_extra_hold + 3.6 ) }]
85-#set cy_pend_min [expr { $CLK_period - ( $cy_out_extra_hold + 2.5 ) }]
86-#set cy_fadr_min [expr { $CLK_period - ( $cy_out_extra_hold + 10 ) }]
87-#set cy_dout_min [expr { $CLK_period - ( $cy_out_extra_hold + 4.5 ) }]
88-
89-set cy_slrd_min [expr { - ( $cy_out_extra_hold + 3.7 ) }]
90-set cy_slwr_min [expr { - ( $cy_out_extra_hold + 3.6 ) }]
91-set cy_pend_min [expr { - ( $cy_out_extra_hold + 2.5 ) }]
92-set cy_fadr_min [expr { - ( $cy_out_extra_hold + 10 ) }]
93-set cy_dout_min [expr { - ( $cy_out_extra_hold + 4.5 ) }]
83+set cy_slrd_min [expr { - ( $cy_out_extra_hold + 3.7 ) }]
84+set cy_slwr_min [expr { - ( $cy_out_extra_hold + 3.6 ) }]
85+set cy_pend_min [expr { - ( $cy_out_extra_hold + 2.5 ) }]
86+set cy_fadr_min [expr { - ( $cy_out_extra_hold + 10 ) }]
87+set cy_dout_min [expr { - ( $cy_dout_extra_hold + 4.5 ) }]
9488
9589 # assume SLRD,SLWR,PKTEND are driven 1.5 cycle ahead and removed 0.5 cycle later
9690 set_multicycle_path -setup -start 2 -from $clk -to $usb_slrd
@@ -99,6 +93,8 @@
9993 set_multicycle_path -hold -start 1 -from $clk -to $usb_slwr
10094 set_multicycle_path -setup -start 2 -from $clk -to $usb_pktend
10195 set_multicycle_path -hold -start 1 -from $clk -to $usb_pktend
96+# assume DATA is removed 1 cycle later
97+set_multicycle_path -hold -start 1 -from $clk -to $usb_data
10298 # assume FIFOADR is driven 2 cycles ahead, and removed 1 cycle later
10399 set_multicycle_path -setup -start 3 -from $clk -to $usb_fifoadr
104100 set_multicycle_path -hold -start 3 -from $clk -to $usb_fifoadr
@@ -132,7 +128,7 @@
132128 set_output_delay -clock ifclk -max $cy_fadr_max $usb_fifoadr
133129 set_output_delay -clock ifclk -min $cy_fadr_min $usb_fifoadr
134130 }
135-if 0 {
131+if 1 {
136132 set_output_delay -clock ifclk -max $cy_dout_max $usb_data
137133 set_output_delay -clock ifclk -min $cy_dout_min $usb_data
138134 }
diff -r a03dc92c6cfb -r 6ae688c6805a ep3/cy_max_test.v
--- a/ep3/cy_max_test.v Thu Nov 22 20:14:23 2018 +0000
+++ b/ep3/cy_max_test.v Thu Nov 22 20:41:00 2018 +0000
@@ -160,7 +160,6 @@
160160 usb_pktend_n_o <= pktend_n_next;
161161 end
162162
163-//assign usb_ifclk = clk;
164163 assign usb_ifclk = usb_ifclk_o;
165164
166165 assign usb_pa2 = usb_sloe_n_o;
@@ -174,7 +173,6 @@
174173 reg [15:0] usb_data_out;
175174 reg usb_data_oe;
176175 always @(posedge clk)
177-//always @(negedge clk)
178176 begin
179177 usb_data_oe <= data_oe_next;
180178 if (usb_data_wr)
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