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digital oscilloscope


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Revision5d95eb57c0c79f28d7e006df646a8a734e027777 (tree)
Zeit2018-11-22 06:20:42
AutorPJ
CommiterPJ

Log Message

ep3/cy_max_test: sloe -> din ok

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Diff

diff -r 29cedb0d9ee0 -r 5d95eb57c0c7 ep3/cy_max_test.sdc
--- a/ep3/cy_max_test.sdc Wed Nov 21 19:42:16 2018 +0000
+++ b/ep3/cy_max_test.sdc Wed Nov 21 21:20:42 2018 +0000
@@ -23,6 +23,14 @@
2323 set CLK_period [get_clock_info -period $clk ]
2424 set IFCLK_period [get_clock_info -period ifclk ]
2525
26+# test if IFCLK output delay can be influenced
27+# without constrains: max: 7.432/7.334, min: 3.460/3.506
28+# with constrains: the same
29+#set ifclk_del_min -1.0
30+#set ifclk_del_max [expr {$CLK_period / 2 - 5.0}]
31+#set_output_delay -clock $clk -min $ifclk_del_min [get_ports { usb_ifclk }]
32+#set_output_delay -clock $clk -max $ifclk_del_max [get_ports { usb_ifclk }]
33+
2634 set usb_data [get_ports { usb_pb_io* usb_pd_io* }]
2735 set usb_slrd [get_ports usb_slrd_n_o ]
2836 set usb_slwr [get_ports usb_slwr_n_o ]
@@ -32,17 +40,29 @@
3240 set usb_flags [get_ports { usb_flaga_i usb_flagb_i usb_flagc_i }]
3341
3442 # margin
35-set cy_out_extra_setup 2.0
43+set cy_out_extra_setup 1.0
3644 set cy_dout_extra_setup 2.0
37-set cy_out_extra_hold 1.0
38-set cy_in_setup_margin 2.0
45+#set cy_out_extra_hold 1.0
46+set cy_out_extra_hold 0.5
47+set cy_flg_setup_margin 2.0
3948 set cy_din_setup_margin 0.5
4049 set cy_din_hold_margin 0.5
4150
51+set din_rel_to_clk 1
52+if $din_rel_to_clk {
53+# (desired) Din setup (rel to clk)
54+set cy_din_setup 2.0
55+# (desired) Din hold (rel to clk)
56+#set cy_din_hold 1.0
57+set cy_din_hold 3.0
58+} else {
4259 # (desired) Din setup (rel to ifclk)
43-set cy_din_setup 10.7
60+#set cy_din_setup 10.7
61+set cy_din_setup 8.0
4462 # (desired) Din hold (rel to ifclk)
45-set cy_din_hold -1.0
63+#set cy_din_hold -1.0
64+set cy_din_hold -2.0
65+}
4666
4767 # max out delay = setup + margin
4868 set cy_slrd_max [expr { $cy_out_extra_setup + 12.7 }]
@@ -69,11 +89,12 @@
6989 #set_multicycle_path -hold -start 1 -from $clk -to $usb_slwr
7090 #set_multicycle_path -hold -start 1 -from $clk -to $usb_pktend
7191 #set_multicycle_path -hold -start 1 -from $clk -to $usb_data
72-#set_multicycle_path -setup -start 2 -from $clk -to $usb_fifoadr
73-#set_multicycle_path -hold -start 2 -from $clk -to $usb_fifoadr
92+# assume FIFOADR is driven 1 cycle ahead
93+set_multicycle_path -setup -start 2 -from $clk -to $usb_fifoadr
94+set_multicycle_path -hold -start 2 -from $clk -to $usb_fifoadr
7495
7596 # max in delay = max output time + margin
76-set cy_flags_max [expr { $cy_in_setup_margin + 13.5 }]
97+set cy_flags_max [expr { $cy_flg_setup_margin + 13.5 }]
7798 # min in delay = min output time - margin
7899 set cy_flags_min 0
79100
@@ -87,6 +108,7 @@
87108 # min in delay = min output time - margin
88109 set cy_din_min [expr { $cy_din_hold - $cy_din_hold_margin }]
89110
111+if 0 {
90112 set_output_delay -clock ifclk -max $cy_slrd_max $usb_slrd
91113 set_output_delay -clock ifclk -min $cy_slrd_min $usb_slrd
92114 set_output_delay -clock ifclk -max $cy_slwr_max $usb_slwr
@@ -97,15 +119,30 @@
97119 set_output_delay -clock ifclk -min $cy_fadr_min $usb_fifoadr
98120 set_output_delay -clock ifclk -max $cy_dout_max $usb_data
99121 set_output_delay -clock ifclk -min $cy_dout_min $usb_data
122+}
100123
124+if 1 {
125+if $din_rel_to_clk {
126+set_output_delay -clock $clk -max $cy_sloe_max $usb_sloe
127+set_output_delay -clock $clk -min $cy_sloe_min $usb_sloe
128+} else {
101129 set_output_delay -clock ifclk -max $cy_sloe_max $usb_sloe
102130 set_output_delay -clock ifclk -min $cy_sloe_min $usb_sloe
131+}
132+}
103133
134+if 1 {
104135 set_input_delay -clock ifclk -max $cy_flags_max $usb_flags
105136 set_input_delay -clock ifclk -min $cy_flags_min $usb_flags
106137
138+if $din_rel_to_clk {
139+set_input_delay -clock $clk -max $cy_din_max $usb_data
140+set_input_delay -clock $clk -min $cy_din_min $usb_data
141+} else {
107142 set_input_delay -clock ifclk -max $cy_din_max $usb_data
108143 set_input_delay -clock ifclk -min $cy_din_min $usb_data
144+}
145+}
109146
110147
111148 #######
diff -r 29cedb0d9ee0 -r 5d95eb57c0c7 ep3/cy_max_test.v
--- a/ep3/cy_max_test.v Wed Nov 21 19:42:16 2018 +0000
+++ b/ep3/cy_max_test.v Wed Nov 21 21:20:42 2018 +0000
@@ -144,16 +144,18 @@
144144 reg [1:0] usb_fifoadr_o;
145145 reg usb_sloe_n_o;
146146 reg usb_pktend_n_o;
147-reg usb_data_oe;
148147 always @(posedge clk)
149148 begin
150149 usb_ifclk_o <= ifclk_next;
151- usb_fifoadr_o <= fifoadr_next;
152150 usb_slrd_n_o <= slrd_n_next;
153151 usb_slwr_n_o <= slwr_n_next;
154152 usb_sloe_n_o <= sloe_n_next;
155153 usb_pktend_n_o <= pktend_n_next;
156- usb_data_oe <= data_oe_next;
154+end
155+
156+always @(negedge clk)
157+begin
158+ usb_fifoadr_o <= fifoadr_next;
157159 end
158160
159161 assign usb_ifclk = clk;
@@ -163,11 +165,15 @@
163165 assign usb_pa5 = usb_fifoadr_o[1];
164166 assign usb_pa6 = usb_pktend_n_o;
165167
166-// Cypress data output reg
167168 wire [15:0] data_out;
169+
170+// Cypress data output reg
168171 reg [15:0] usb_data_out;
169-always @(posedge clk)
172+reg usb_data_oe;
173+//always @(posedge clk)
174+always @(negedge clk)
170175 begin
176+ usb_data_oe <= data_oe_next;
171177 if (usb_data_wr)
172178 usb_data_out <= data_out;
173179 end
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