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digital oscilloscope


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Revision29cedb0d9ee05b1dd1a2cecac48c1bd99e86af48 (tree)
Zeit2018-11-22 04:42:16
AutorPJ
CommiterPJ

Log Message

ep3/cy_max_test: compiled

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diff -r 0826fcbbd905 -r 29cedb0d9ee0 .hgignore
--- a/.hgignore Wed Nov 21 18:59:49 2018 +0000
+++ b/.hgignore Wed Nov 21 19:42:16 2018 +0000
@@ -6,6 +6,7 @@
66 cli/monitor
77 cli/speed_bulk
88 cli/test_in
9+ep3/quartus/*.qws
910 ep3/quartus/db/
1011 ep3/quartus/incremental_db/
1112 ep3/quartus/output_files/
diff -r 0826fcbbd905 -r 29cedb0d9ee0 ep3/cy_max_test.sdc
--- a/ep3/cy_max_test.sdc Wed Nov 21 18:59:49 2018 +0000
+++ b/ep3/cy_max_test.sdc Wed Nov 21 19:42:16 2018 +0000
@@ -10,11 +10,12 @@
1010 set clk { i_pll|auto_generated|pll1|clk[0] }
1111
1212 # IFCLK, internal
13-set ifclk_int_loc [get_pins cy_io|usb_ifclk_o|q ]
14-create_generated_clock -name ifclk_int -source $clk -edges { 1 9 17 } $ifclk_int_loc
13+#set ifclk_int_loc [get_pins cy_io|usb_ifclk_o|q ]
14+#create_generated_clock -name ifclk_int -source $clk -edges { 1 9 17 } $ifclk_int_loc
1515
1616 # IFCLK, output
17-create_generated_clock -name ifclk -source $ifclk_int_loc [get_ports usb_ifclk ]
17+create_generated_clock -name ifclk -source $clk [get_ports usb_ifclk ]
18+#create_generated_clock -name ifclk -source $ifclk_int_loc [get_ports usb_ifclk ]
1819
1920 # Slave FIFO Synchronous Read/Write Parameters with Externally Sourced IFCLK
2021 # IFCLK = CLK/2
@@ -64,12 +65,12 @@
6465 set cy_dout_min [expr { - ( $cy_out_extra_hold + 4.5 ) }]
6566
6667 # outputs held for one extra CLK cycle by the state machine
67-set_multicycle_path -hold -start 1 -from $clk -to $usb_slrd
68-set_multicycle_path -hold -start 1 -from $clk -to $usb_slwr
69-set_multicycle_path -hold -start 1 -from $clk -to $usb_pktend
70-set_multicycle_path -hold -start 1 -from $clk -to $usb_data
71-set_multicycle_path -setup -start 2 -from $clk -to $usb_fifoadr
72-set_multicycle_path -hold -start 2 -from $clk -to $usb_fifoadr
68+#set_multicycle_path -hold -start 1 -from $clk -to $usb_slrd
69+#set_multicycle_path -hold -start 1 -from $clk -to $usb_slwr
70+#set_multicycle_path -hold -start 1 -from $clk -to $usb_pktend
71+#set_multicycle_path -hold -start 1 -from $clk -to $usb_data
72+#set_multicycle_path -setup -start 2 -from $clk -to $usb_fifoadr
73+#set_multicycle_path -hold -start 2 -from $clk -to $usb_fifoadr
7374
7475 # max in delay = max output time + margin
7576 set cy_flags_max [expr { $cy_in_setup_margin + 13.5 }]
@@ -119,15 +120,15 @@
119120 set_input_delay -clock $io_clk -min $in_del_min [get_ports { usb_pa0 usb_pa1 usb_pa7 }]
120121 set_input_delay -clock $io_clk -max $in_del_max [get_ports { usb_pa0 usb_pa1 usb_pa7 }]
121122
122-set_input_delay -clock $io_clk -min $in_del_min [get_ports { ads_drdy_n_i ads_dout01_i ads_dout23_i ads_pwr_oc_n_i }]
123-set_input_delay -clock $io_clk -max $in_del_max [get_ports { ads_drdy_n_i ads_dout01_i ads_dout23_i ads_pwr_oc_n_i }]
123+#set_input_delay -clock $io_clk -min $in_del_min [get_ports { ads_drdy_n_i ads_dout01_i ads_dout23_i ads_pwr_oc_n_i }]
124+#set_input_delay -clock $io_clk -max $in_del_max [get_ports { ads_drdy_n_i ads_dout01_i ads_dout23_i ads_pwr_oc_n_i }]
124125
125126 # push output regs into I/O cells
126127 set out_del_min -1.0
127128 set out_del_max [expr {$io_clk_period - 9.0}]
128129
129-set_output_delay -clock $io_clk -min $out_del_min [get_ports { ads_cs02_n_o ads_cs13_n_o ads_sclk_o ads_din01_o ads_din23_o ads_pwr_en_o }]
130-set_output_delay -clock $io_clk -max $out_del_max [get_ports { ads_cs02_n_o ads_cs13_n_o ads_sclk_o ads_din01_o ads_din23_o ads_pwr_en_o }]
130+#set_output_delay -clock $io_clk -min $out_del_min [get_ports { ads_cs02_n_o ads_cs13_n_o ads_sclk_o ads_din01_o ads_din23_o ads_pwr_en_o }]
131+#set_output_delay -clock $io_clk -max $out_del_max [get_ports { ads_cs02_n_o ads_cs13_n_o ads_sclk_o ads_din01_o ads_din23_o ads_pwr_en_o }]
131132
132133 #set_output_delay -clock $io_clk -min $out_del_min [get_ports { rs_tx_1_o rs_tx_2_o }]
133134 #set_output_delay -clock $io_clk -max $out_del_max [get_ports { rs_tx_1_o rs_tx_2_o }]
diff -r 0826fcbbd905 -r 29cedb0d9ee0 ep3/cy_max_test.v
--- a/ep3/cy_max_test.v Wed Nov 21 18:59:49 2018 +0000
+++ b/ep3/cy_max_test.v Wed Nov 21 19:42:16 2018 +0000
@@ -31,8 +31,8 @@
3131 input usb_flaga_i,
3232 input usb_flagb_i,
3333 input usb_flagc_i,
34-output usb_slrd_n_o, // Out FIFO Read
35-output usb_slwr_n_o, // In FIFO Write
34+output reg usb_slrd_n_o, // Out FIFO Read
35+output reg usb_slwr_n_o, // In FIFO Write
3636 inout [7:0] usb_pb_io, // usb_data (bidir)
3737 inout [7:0] usb_pd_io, // usb_data (bidir)
3838
@@ -98,16 +98,6 @@
9898 mode_in[2] <= usb_pa7;
9999 end
100100
101-reg clear; // sync reset
102-reg enable_ctrl_io; // enable Ctrl In/Out
103-reg enable_data_in_raw; // enable Data In
104-always @(posedge clk)
105-begin
106- clear <= (mode_in == 3'b111);
107- enable_ctrl_io <= (mode_in == 3'b110) || (mode_in == 3'b100);
108- enable_data_in_raw <= (mode_in == 3'b100);
109-end
110-
111101 //// ADS pins - unused
112102 assign ads_pwr_en_o = 1'b0;
113103 assign ads_sclk_o = 1'b0;
@@ -118,73 +108,85 @@
118108
119109
120110 //// Cypress
121-wire usb_data_rd; // capture data input
122-wire usb_data_wr; // update data output (in the next cycle)
123-wire usb_data_sel; // select ctrl(0)/data(1) (in the next cycle)
124-wire usb_data_oe; // data output enable
111+reg [9:0] cy_cnt;
112+always @(posedge clk)
113+begin
114+ cy_cnt <= cy_cnt + 1'b1;
115+end
125116
126-cy_io_div_v5 #(
127-// .fifoadr_c_out_p (2), // EP6 - Ctrl OUT FIFO
128-// .fifoadr_c_in_p (3), // EP8 - Ctrl IN FIFO
129-// .fifoadr_d_in_p (0) // EP2 - Data IN FIFO
130- .fifoadr_c_out_p (1), // EP4 - Ctrl OUT FIFO
131- .fifoadr_c_in_p (3), // EP8 - Ctrl IN FIFO
132- .fifoadr_d_in_p (2) // EP6 - Data IN FIFO
133-) cy_io (
134- .clk (clk),
135- .clear (clear), // clear state & disable
136-// Cypress FIFO
137- .usb_ifclk_o (usb_ifclk),
138- .usb_fifoadr_o ({usb_pa5, usb_pa4}),
139- .usb_flag_c_out_empty_i (usb_flagc_i), // Ctrl Out FIFO empty
140- .usb_flag_c_in_full_i (usb_flagb_i), // Ctrl In FIFO full
141- .usb_flag_d_in_full_i (usb_flaga_i), // Data In FIFO full
142- .usb_slrd_n_o (usb_slrd_n_o),
143- .usb_slwr_n_o (usb_slwr_n_o),
144- .usb_sloe_n_o (usb_pa2),
145- .usb_pktend_n_o (usb_pa6),
146- .usb_data_rd_o (usb_data_rd), // capture data input
147- .usb_data_wr_o (usb_data_wr), // update data output (in the next cycle)
148- .usb_data_sel_o (usb_data_sel), // select ctrl(0)/data(1) (in the next cycle)
149- .usb_data_oe_o (usb_data_oe), // data output enable
150-// Data IN
151- .data_in_pktend_i (data_in_pktend),
152- .data_in_ready_i (data_in_ready),
153- .data_in_next_o (data_in_next),
154-// Ctrl IN
155- .ctrl_in_ready_i (ctrl_in_ready),
156- .ctrl_in_next_o (ctrl_in_next),
157- .ctrl_in_pktend_req_i (ctrl_in_pktend_req),
158- .ctrl_in_pktend_ack_o (ctrl_in_pktend_ack),
159-// Ctrl OUT
160- .ctrl_out_ready_i (ctrl_out_ready),
161- .ctrl_out_strobe_o (ctrl_out_strobe),
162- .ctrl_out_empty_o (ctrl_out_empty)
163-);
117+wire ifclk_next = cy_cnt[0];
164118
165-// Cypress data output reg, Ctrl/Data mux
166-reg [7:0] usb_data_out;
119+// random drive
120+wire usb_flag_cap = cy_cnt[4];
121+wire usb_data_wr = cy_cnt[5];
122+wire usb_data_rd = cy_cnt[7];
123+wire data_oe_next = cy_cnt[3];
124+wire pktend_n_next = cy_cnt[4];
125+wire [1:0] fifoadr_next = cy_cnt[6:5];
126+wire slrd_n_next = cy_cnt[7];
127+wire slwr_n_next = cy_cnt[8];
128+wire sloe_n_next = cy_cnt[9];
129+
130+
131+// input reg
132+reg usb_flaga_reg, usb_flagb_reg, usb_flagc_reg;
133+always @(posedge clk)
134+begin
135+ if (usb_flag_cap) begin
136+ usb_flaga_reg <= usb_flaga_i;
137+ usb_flagb_reg <= usb_flagb_i;
138+ usb_flagc_reg <= usb_flagc_i;
139+ end
140+end
141+
142+// output reg
143+reg usb_ifclk_o;
144+reg [1:0] usb_fifoadr_o;
145+reg usb_sloe_n_o;
146+reg usb_pktend_n_o;
147+reg usb_data_oe;
148+always @(posedge clk)
149+begin
150+ usb_ifclk_o <= ifclk_next;
151+ usb_fifoadr_o <= fifoadr_next;
152+ usb_slrd_n_o <= slrd_n_next;
153+ usb_slwr_n_o <= slwr_n_next;
154+ usb_sloe_n_o <= sloe_n_next;
155+ usb_pktend_n_o <= pktend_n_next;
156+ usb_data_oe <= data_oe_next;
157+end
158+
159+assign usb_ifclk = clk;
160+//assign usb_ifclk = usb_ifclk_o;
161+assign usb_pa2 = usb_sloe_n_o;
162+assign usb_pa4 = usb_fifoadr_o[0];
163+assign usb_pa5 = usb_fifoadr_o[1];
164+assign usb_pa6 = usb_pktend_n_o;
165+
166+// Cypress data output reg
167+wire [15:0] data_out;
168+reg [15:0] usb_data_out;
167169 always @(posedge clk)
168170 begin
169171 if (usb_data_wr)
170- usb_data_out <= usb_data_sel ? data_in_data : ctrl_in_data;
172+ usb_data_out <= data_out;
171173 end
172174
173-// bidir
174-wire [7:0] usb_pd_out = 8'bz;
175-//wire [7:0] usb_pb_in = usb_pb_io;
176-wire [7:0] usb_pd_in = usb_pd_io;
177-assign usb_pb_io = (usb_data_oe) ? usb_data_out : 8'bz; // 3-st data output
178-assign usb_pd_io = usb_pd_out;
175+// 3-st data output
176+assign usb_pb_io = (usb_data_oe) ? usb_data_out[ 7:0] : 8'bz;
177+assign usb_pd_io = (usb_data_oe) ? usb_data_out[15:8] : 8'bz;
179178
180179 // Cypress data input reg
181-reg [7:0] usb_data_in;
180+reg [15:0] usb_data_in;
182181 always @(posedge clk)
183182 begin
184- if (usb_data_rd)
185- usb_data_in <= usb_pb_io;
183+ if (usb_data_rd) begin
184+ usb_data_in[ 7:0] <= usb_pb_io;
185+ usb_data_in[15:8] <= usb_pd_io;
186+ end
186187 end
187-assign ctrl_out_data = usb_data_in;
188+
189+assign data_out = ~usb_data_in ^ { usb_flaga_reg, usb_flagb_reg, usb_flagc_reg };
188190
189191 ///////////////////////////////////////////////////////////////
190192
@@ -193,8 +195,8 @@
193195 begin
194196 cnt <= cnt + 1'b1;
195197 end
196-wire led1 = clear ? cnt[24] : (enable_data_in ? cnt[21] : cnt[23]);
197-wire led2 = cnt[24];
198+wire led1 = cnt[23] ^ mode_in[0];
199+wire led2 = cnt[24] ^ mode_in[1];
198200
199201 //`define TEST_CY_IO
200202
@@ -214,8 +216,8 @@
214216 assign test[17:0] = cnt[17:0];
215217 //assign test[17:8] = cnt[17:8];
216218
217-assign ext1 = cnt[10];
218-assign ext2 = cnt[11];
219+assign ext1 = cnt[10] ^ mode_in[2];
220+assign ext2 = cnt[11] ^ ads_drdy_n_i ^ ads_dout01_i ^ ads_dout23_i ^ ads_pwr_oc_n_i;
219221 assign ext3 = cnt[12];
220222 assign ext4 = cnt[13];
221223
@@ -223,4 +225,5 @@
223225 assign led1_n_o = led1 ? 1'b1 : 1'bz;
224226 assign led2_n_o = led2 ? 1'b1 : 1'bz;
225227
226-endmodule : cy_max_test
228+endmodule
229+//endmodule : cy_max_test
diff -r 0826fcbbd905 -r 29cedb0d9ee0 ep3/quartus/cy_max_test.qsf
--- a/ep3/quartus/cy_max_test.qsf Wed Nov 21 18:59:49 2018 +0000
+++ b/ep3/quartus/cy_max_test.qsf Wed Nov 21 19:42:16 2018 +0000
@@ -5,7 +5,7 @@
55 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
66
77 # pin assignment
8-source ../pins.qsf
8+source ../pins_eeg32.qsf
99
1010 #weak outputs: LVCMOS with 2mA current
1111 set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to *
@@ -27,4 +27,5 @@
2727 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
2828 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
2929 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
30-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
30+
31+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
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