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digital oscilloscope


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Revision0e3db1460a3ac27090e7c685995f460e7a9bd1ea (tree)
Zeit2018-11-24 19:29:24
AutorPJ
CommiterPJ

Log Message

ep3/cy_max_test.sdc: sloe/din rel to clk

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Diff

diff -r ad164e61b60f -r 0e3db1460a3a ep3/cy_max_test.sdc
--- a/ep3/cy_max_test.sdc Fri Nov 23 14:22:52 2018 +0000
+++ b/ep3/cy_max_test.sdc Sat Nov 24 10:29:24 2018 +0000
@@ -51,19 +51,17 @@
5151 set cy_flg_setup_margin 2.5
5252 set cy_din_hold_margin 0.5
5353
54-set din_rel_to_clk 0
54+set din_rel_to_clk 1
5555 if $din_rel_to_clk {
5656 # (desired) Din setup (rel to clk)
5757 set cy_din_setup 1.0
58-set cy_din_setup_margin 1.0
59-set cy_sloe_setup_margin 1.0
58+set cy_din_setup_margin 1.5
59+set cy_sloe_setup_margin 1.5
6060 # (desired) Din hold (rel to clk)
61-#set cy_din_hold 3.0
62-#set cy_din_hold 5.0
63-set cy_din_hold 10.0
61+set cy_din_hold 6.0
62+#set cy_din_hold 10.0
6463 } else {
6564 # (desired) Din setup (rel to ifclk)
66-#set cy_din_setup 4.0
6765 set cy_din_setup 4.9
6866 set cy_din_setup_margin 0.0
6967 set cy_sloe_setup_margin 0.0
@@ -94,16 +92,17 @@
9492 # setup = Din setup + SLOE_to_data_ON + margin
9593 set cy_sloe_max [expr { $cy_sloe_setup_margin + $cy_din_setup + 10.5 }]
9694 # hold = Din hold - SLOE_to_data_OFF_min + margin
97-set cy_sloe_min [expr { - ( $cy_out_hold_margin + $cy_din_hold - 8.0 ) }]
95+set cy_sloe_min [expr { - ( $cy_out_hold_margin + $cy_din_hold - 5.0 ) }]
9896
9997 # max in delay = max output time + margin
10098 if $din_rel_to_clk {
101-#set cy_din_max [expr { $CLK_period - $cy_din_setup + $cy_din_setup_margin }]
99+set cy_din_max [expr { $CLK_period - $cy_din_setup + $cy_din_setup_margin }]
102100 } else {
103101 set cy_din_max [expr { $CLK_period/2 - $cy_din_setup + $cy_din_setup_margin }]
104102 }
105103 # min in delay = min output time - margin
106-set cy_din_min [expr { $cy_din_hold - $cy_din_hold_margin }]
104+#set cy_din_min [expr { $cy_din_hold - $cy_din_hold_margin }]
105+set cy_din_min [expr { $cy_din_hold - $cy_din_hold_margin + $CLK_period}]
107106
108107 # assume SLRD,SLWR,PKTEND are driven 1.5 cycle ahead and removed 0.5 cycle later
109108 set_multicycle_path -setup -start 2 -from $clk -to $usb_slrd
@@ -146,6 +145,13 @@
146145 set_output_delay -clock $clk -clock_fall -min $cy_sloe_min $usb_sloe
147146 set_input_delay -clock $clk -clock_fall -max $cy_din_max $usb_data
148147 set_input_delay -clock $clk -clock_fall -min $cy_din_min $usb_data
148+# ensure data in capture before rising edge of IFCLK
149+#FIXME
150+#set_multicycle_path -hold -end -1 -from ifclk -to $usb_data
151+#set_multicycle_path -hold -end -1 -from ifclk -through $usb_data -to $clk
152+set_multicycle_path -hold -end -1 -from $usb_data -to $clk
153+ set_input_delay -add_delay -clock ifclk -min 0 $usb_data
154+ set_input_delay -add_delay -clock ifclk -max -10 $usb_data
149155 } else {
150156 set_output_delay -clock ifclk -max $cy_sloe_max $usb_sloe
151157 set_output_delay -clock ifclk -min $cy_sloe_min $usb_sloe
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