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linux-2.4.36: Commit

2.4.36-stable kernel tree

Commit MetaInfo

Revision	f9a33c5a01c8df82fd33830dfd4cd817012cf063 (tree)
Zeit	2007-02-06 09:56:43
Autor	Jesse Brandeburg <jesse.brandeburg@inte...>
Commiter	Auke Kok

Log Message

e1000: integrate latest 2.4 linux driver

This updates the e1000 driver to our out-of-tree equivalent of 7.3.20.
This adds support for several new pieces of e100 hardware, including
quad-port 82571's (copper only), integrated nics of ICH8. The patch
includes dynamic interrupt support, many rewrites of subcomponents such
as wol enabling, manageability handling, shutdown/reset race fixes,

To keep the difference with the 2.6-version of this driver minimal
(which will facilitate future updates) we include a small compatibility
layer exclusively for e1000.

Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com>

Ändern Zusammenfassung

modified: drivers/net/e1000/Makefile (diff)
modified: drivers/net/e1000/e1000.h (diff)
modified: drivers/net/e1000/e1000_ethtool.c (diff)
modified: drivers/net/e1000/e1000_hw.c (diff)
modified: drivers/net/e1000/e1000_hw.h (diff)
modified: drivers/net/e1000/e1000_main.c (diff)
modified: drivers/net/e1000/e1000_osdep.h (diff)
modified: drivers/net/e1000/e1000_param.c (diff)
add: drivers/net/e1000/kcompat.c (diff)
add: drivers/net/e1000/kcompat.h (diff)

Diff

--- a/drivers/net/e1000/Makefile

+++ b/drivers/net/e1000/Makefile

		@@ -32,7 +32,7 @@
32	32
33	33	O_TARGET := e1000.o
34	34
35		-obj-y := e1000_main.o e1000_hw.o e1000_ethtool.o e1000_param.o
	35	+obj-y := e1000_main.o e1000_hw.o e1000_ethtool.o e1000_param.o kcompat.o
36	36	obj-m := $(O_TARGET)
37	37
38	38	include $(TOPDIR)/Rules.make

--- a/drivers/net/e1000/e1000.h

+++ b/drivers/net/e1000/e1000.h

		@@ -1,27 +1,27 @@
1	1	/*******************************************************************************
2	2
3		-
4		- Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
5		-
6		- This program is free software; you can redistribute it and/or modify it
7		- under the terms of the GNU General Public License as published by the Free
8		- Software Foundation; either version 2 of the License, or (at your option)
9		- any later version.
10		-
11		- This program is distributed in the hope that it will be useful, but WITHOUT
12		- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13		- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	3	+ Intel PRO/1000 Linux driver
	4	+ Copyright(c) 1999 - 2006 Intel Corporation.
	5	+
	6	+ This program is free software; you can redistribute it and/or modify it
	7	+ under the terms and conditions of the GNU General Public License,
	8	+ version 2, as published by the Free Software Foundation.
	9	+
	10	+ This program is distributed in the hope it will be useful, but WITHOUT
	11	+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14	13	more details.
15		-
	14	+
16	15	You should have received a copy of the GNU General Public License along with
17		- this program; if not, write to the Free Software Foundation, Inc., 59
18		- Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19		-
20		- The full GNU General Public License is included in this distribution in the
21		- file called LICENSE.
22		-
	16	+ this program; if not, write to the Free Software Foundation, Inc.,
	17	+ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18	+
	19	+ The full GNU General Public License is included in this distribution in
	20	+ the file called "COPYING".
	21	+
23	22	Contact Information:
24	23	Linux NICS <linux.nics@intel.com>
	24	+ e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25	25	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26	26
27	27	*******************************************************************************/

		@@ -33,7 +33,6 @@
33	33	#define _E1000_H_
34	34
35	35	#include <linux/stddef.h>
36		-#include <linux/config.h>
37	36	#include <linux/module.h>
38	37	#include <linux/types.h>
39	38	#include <asm/byteorder.h>

		@@ -53,7 +52,7 @@
53	52	#include <linux/interrupt.h>
54	53	#include <linux/string.h>
55	54	#include <linux/pagemap.h>
56		-#include <asm/bitops.h>
	55	+#include <linux/bitops.h>
57	56	#include <asm/io.h>
58	57	#include <asm/irq.h>
59	58	#include <linux/capability.h>

		@@ -64,21 +63,21 @@
64	63	#include <net/pkt_sched.h>
65	64	#include <linux/list.h>
66	65	#include <linux/reboot.h>
67		-#ifdef NETIF_F_TSO
68		-#include <net/checksum.h>
69		-#endif
70		-#include <linux/tqueue.h>
	66	+#ifdef SIOCGMIIPHY
71	67	#include <linux/mii.h>
	68	+#endif
	69	+#ifdef SIOCETHTOOL
72	70	#include <linux/ethtool.h>
	71	+#endif
	72	+#ifdef NETIF_F_HW_VLAN_TX
73	73	#include <linux/if_vlan.h>
74		-#include <linux/moduleparam.h>
	74	+#endif
75	75
76	76	#define BAR_0 0
77	77	#define BAR_1 1
78	78	#define BAR_5 5
79		-#define PCI_DMA_64BIT 0xffffffffffffffffULL
80		-#define PCI_DMA_32BIT 0x00000000ffffffffULL
81	79
	80	+#include "kcompat.h"
82	81	#define INTEL_E1000_ETHERNET_DEVICE(device_id) {\
83	82	PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)}
84	83

		@@ -86,11 +85,7 @@ struct e1000_adapter;
86	85
87	86	#include "e1000_hw.h"
88	87
89		-#ifdef DBG
90		-#define E1000_DBG(args...) printk(KERN_DEBUG "e1000: " args)
91		-#else
92	88	#define E1000_DBG(args...)
93		-#endif
94	89
95	90	#define E1000_ERR(args...) printk(KERN_ERR "e1000: " args)
96	91

		@@ -113,7 +108,14 @@ struct e1000_adapter;
113	108	#define E1000_MIN_RXD 80
114	109	#define E1000_MAX_82544_RXD 4096
115	110
	111	+/* this is the size past which hardware will drop packets when setting LPE=0 */
	112	+#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
	113	+
116	114	/* Supported Rx Buffer Sizes */
	115	+#define E1000_RXBUFFER_128 128 /* Used for packet split */
	116	+#define E1000_RXBUFFER_256 256 /* Used for packet split */
	117	+#define E1000_RXBUFFER_512 512
	118	+#define E1000_RXBUFFER_1024 1024
117	119	#define E1000_RXBUFFER_2048 2048
118	120	#define E1000_RXBUFFER_4096 4096
119	121	#define E1000_RXBUFFER_8192 8192

		@@ -139,15 +141,22 @@ struct e1000_adapter;
139	141	/* How many Rx Buffers do we bundle into one write to the hardware ? */
140	142	#define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
141	143
142		-#define AUTO_ALL_MODES 0
143		-#define E1000_EEPROM_82544_APM 0x0004
144		-#define E1000_EEPROM_APME 0x0400
	144	+#define AUTO_ALL_MODES 0
	145	+#define E1000_EEPROM_82544_APM 0x0004
	146	+#define E1000_EEPROM_ICH8_APME 0x0004
	147	+#define E1000_EEPROM_APME 0x0400
145	148
146	149	#ifndef E1000_MASTER_SLAVE
147	150	/* Switch to override PHY master/slave setting */
148	151	#define E1000_MASTER_SLAVE e1000_ms_hw_default
149	152	#endif
150	153
	154	+#ifdef NETIF_F_HW_VLAN_TX
	155	+#define E1000_MNG_VLAN_NONE -1
	156	+#endif
	157	+/* Number of packet split data buffers (not including the header buffer) */
	158	+#define PS_PAGE_BUFFERS MAX_PS_BUFFERS-1
	159	+
151	160	/* only works for sizes that are powers of 2 */
152	161	#define E1000_ROUNDUP(i, size) ((i) = (((i) + (size) - 1) & ~((size) - 1)))
153	162

		@@ -155,13 +164,39 @@ struct e1000_adapter;
155	164	* so a DMA handle can be stored along with the buffer */
156	165	struct e1000_buffer {
157	166	struct sk_buff *skb;
158		- uint64_t dma;
	167	+ dma_addr_t dma;
159	168	unsigned long time_stamp;
160	169	uint16_t length;
161	170	uint16_t next_to_watch;
162	171	};
163	172
164		-struct e1000_desc_ring {
	173	+
	174	+struct e1000_ps_page { struct page *ps_page[PS_PAGE_BUFFERS]; };
	175	+struct e1000_ps_page_dma { uint64_t ps_page_dma[PS_PAGE_BUFFERS]; };
	176	+
	177	+struct e1000_tx_ring {
	178	+ /* pointer to the descriptor ring memory */
	179	+ void *desc;
	180	+ /* physical address of the descriptor ring */
	181	+ dma_addr_t dma;
	182	+ /* length of descriptor ring in bytes */
	183	+ unsigned int size;
	184	+ /* number of descriptors in the ring */
	185	+ unsigned int count;
	186	+ /* next descriptor to associate a buffer with */
	187	+ unsigned int next_to_use;
	188	+ /* next descriptor to check for DD status bit */
	189	+ unsigned int next_to_clean;
	190	+ /* array of buffer information structs */
	191	+ struct e1000_buffer *buffer_info;
	192	+
	193	+ spinlock_t tx_lock;
	194	+ uint16_t tdh;
	195	+ uint16_t tdt;
	196	+ boolean_t last_tx_tso;
	197	+};
	198	+
	199	+struct e1000_rx_ring {
165	200	/* pointer to the descriptor ring memory */
166	201	void *desc;
167	202	/* physical address of the descriptor ring */

		@@ -176,12 +211,25 @@ struct e1000_desc_ring {
176	211	unsigned int next_to_clean;
177	212	/* array of buffer information structs */
178	213	struct e1000_buffer *buffer_info;
	214	+ /* arrays of page information for packet split */
	215	+ struct e1000_ps_page *ps_page;
	216	+ struct e1000_ps_page_dma *ps_page_dma;
	217	+
	218	+ /* cpu for rx queue */
	219	+ int cpu;
	220	+
	221	+ uint16_t rdh;
	222	+ uint16_t rdt;
179	223	};
180	224
181	225	#define E1000_DESC_UNUSED(R) \
182	226	((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
183	227	(R)->next_to_clean - (R)->next_to_use - 1)
184	228
	229	+#define E1000_RX_DESC_PS(R, i) \
	230	+ (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
	231	+#define E1000_RX_DESC_EXT(R, i) \
	232	+ (&(((union e1000_rx_desc_extended *)((R).desc))[i]))
185	233	#define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
186	234	#define E1000_RX_DESC(R, i) E1000_GET_DESC(R, i, e1000_rx_desc)
187	235	#define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)

		@@ -193,27 +241,44 @@ struct e1000_adapter {
193	241	struct timer_list tx_fifo_stall_timer;
194	242	struct timer_list watchdog_timer;
195	243	struct timer_list phy_info_timer;
	244	+#ifdef NETIF_F_HW_VLAN_TX
196	245	struct vlan_group *vlgrp;
	246	+ uint16_t mng_vlan_id;
	247	+#endif
197	248	uint32_t bd_number;
198	249	uint32_t rx_buffer_len;
199		- uint32_t part_num;
200	250	uint32_t wol;
201	251	uint32_t smartspeed;
202	252	uint32_t en_mng_pt;
203	253	uint16_t link_speed;
204	254	uint16_t link_duplex;
205	255	spinlock_t stats_lock;
	256	+#ifdef CONFIG_E1000_NAPI
	257	+ spinlock_t tx_queue_lock;
	258	+#endif
206	259	atomic_t irq_sem;
207		- struct tq_struct tx_timeout_task;
	260	+ unsigned int total_tx_bytes;
	261	+ unsigned int total_tx_packets;
	262	+ unsigned int total_rx_bytes;
	263	+ unsigned int total_rx_packets;
	264	+ /* Interrupt Throttle Rate */
	265	+ uint32_t itr;
	266	+ uint32_t itr_setting;
	267	+ uint16_t tx_itr;
	268	+ uint16_t rx_itr;
	269	+
	270	+ struct work_struct reset_task;
208	271	uint8_t fc_autoneg;
209	272
	273	+#ifdef ETHTOOL_PHYS_ID
210	274	struct timer_list blink_timer;
211	275	unsigned long led_status;
	276	+#endif
212	277
213	278	/* TX */
214		- struct e1000_desc_ring tx_ring;
215		- struct e1000_buffer previous_buffer_info;
216		- spinlock_t tx_lock;
	279	+ struct e1000_tx_ring tx_ring; / One per active queue */
	280	+ unsigned int restart_queue;
	281	+ unsigned long tx_queue_len;
217	282	uint32_t txd_cmd;
218	283	uint32_t tx_int_delay;
219	284	uint32_t tx_abs_int_delay;

		@@ -221,25 +286,46 @@ struct e1000_adapter {
221	286	uint64_t gotcl_old;
222	287	uint64_t tpt_old;
223	288	uint64_t colc_old;
	289	+ uint32_t tx_timeout_count;
224	290	uint32_t tx_fifo_head;
225	291	uint32_t tx_head_addr;
226	292	uint32_t tx_fifo_size;
	293	+ uint8_t tx_timeout_factor;
227	294	atomic_t tx_fifo_stall;
228	295	boolean_t pcix_82544;
229	296	boolean_t detect_tx_hung;
230	297
231	298	/* RX */
232		- struct e1000_desc_ring rx_ring;
	299	+#ifdef CONFIG_E1000_NAPI
	300	+ boolean_t (clean_rx) (struct e1000_adapter adapter,
	301	+ struct e1000_rx_ring *rx_ring,
	302	+ int *work_done, int work_to_do);
	303	+#else
	304	+ boolean_t (clean_rx) (struct e1000_adapter adapter,
	305	+ struct e1000_rx_ring *rx_ring);
	306	+#endif
	307	+ void (alloc_rx_buf) (struct e1000_adapter adapter,
	308	+ struct e1000_rx_ring *rx_ring,
	309	+ int cleaned_count);
	310	+ struct e1000_rx_ring rx_ring; / One per active queue */
	311	+#ifdef CONFIG_E1000_NAPI
	312	+ struct net_device polling_netdev; / One per active queue */
	313	+#endif
	314	+ int num_tx_queues;
	315	+ int num_rx_queues;
	316	+
233	317	uint64_t hw_csum_err;
234	318	uint64_t hw_csum_good;
	319	+ uint64_t rx_hdr_split;
	320	+ uint32_t alloc_rx_buff_failed;
235	321	uint32_t rx_int_delay;
236	322	uint32_t rx_abs_int_delay;
237	323	boolean_t rx_csum;
	324	+ unsigned int rx_ps_pages;
238	325	uint32_t gorcl;
239	326	uint64_t gorcl_old;
	327	+ uint16_t rx_ps_bsize0;
240	328
241		- /* Interrupt Throttle Rate */
242		- uint32_t itr;
243	329
244	330	/* OS defined structs */
245	331	struct net_device *netdev;

		@@ -252,12 +338,37 @@ struct e1000_adapter {
252	338	struct e1000_phy_info phy_info;
253	339	struct e1000_phy_stats phy_stats;
254	340
	341	+#ifdef ETHTOOL_TEST
255	342	uint32_t test_icr;
256		- struct e1000_desc_ring test_tx_ring;
257		- struct e1000_desc_ring test_rx_ring;
	343	+ struct e1000_tx_ring test_tx_ring;
	344	+ struct e1000_rx_ring test_rx_ring;
	345	+#endif
258	346
	347	+#ifdef E1000_COUNT_ICR
	348	+ uint64_t icr_txdw;
	349	+ uint64_t icr_txqe;
	350	+ uint64_t icr_lsc;
	351	+ uint64_t icr_rxseq;
	352	+ uint64_t icr_rxdmt;
	353	+ uint64_t icr_rxo;
	354	+ uint64_t icr_rxt;
	355	+ uint64_t icr_mdac;
	356	+ uint64_t icr_rxcfg;
	357	+ uint64_t icr_gpi;
	358	+#endif
259	359
260		- uint32_t pci_state[16];
	360	+ uint32_t *config_space;
261	361	int msg_enable;
	362	+ /* to not mess up cache alignment, always add to the bottom */
	363	+ boolean_t smart_power_down; /* phy smart power down */
	364	+ boolean_t quad_port_a;
	365	+ unsigned long flags;
	366	+ uint32_t eeprom_wol;
	367	+};
	368	+
	369	+enum e1000_state_t {
	370	+ __E1000_TESTING,
	371	+ __E1000_RESETTING,
	372	+ __E1000_DOWN
262	373	};
263	374	#endif /* _E1000_H_ */

--- a/drivers/net/e1000/e1000_ethtool.c

+++ b/drivers/net/e1000/e1000_ethtool.c

		@@ -1,27 +1,27 @@
1	1	/*******************************************************************************
2	2
3		-
4		- Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
5		-
6		- This program is free software; you can redistribute it and/or modify it
7		- under the terms of the GNU General Public License as published by the Free
8		- Software Foundation; either version 2 of the License, or (at your option)
9		- any later version.
10		-
11		- This program is distributed in the hope that it will be useful, but WITHOUT
12		- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13		- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	3	+ Intel PRO/1000 Linux driver
	4	+ Copyright(c) 1999 - 2006 Intel Corporation.
	5	+
	6	+ This program is free software; you can redistribute it and/or modify it
	7	+ under the terms and conditions of the GNU General Public License,
	8	+ version 2, as published by the Free Software Foundation.
	9	+
	10	+ This program is distributed in the hope it will be useful, but WITHOUT
	11	+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14	13	more details.
15		-
	14	+
16	15	You should have received a copy of the GNU General Public License along with
17		- this program; if not, write to the Free Software Foundation, Inc., 59
18		- Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19		-
20		- The full GNU General Public License is included in this distribution in the
21		- file called LICENSE.
22		-
	16	+ this program; if not, write to the Free Software Foundation, Inc.,
	17	+ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18	+
	19	+ The full GNU General Public License is included in this distribution in
	20	+ the file called "COPYING".
	21	+
23	22	Contact Information:
24	23	Linux NICS <linux.nics@intel.com>
	24	+ e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25	25	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26	26
27	27	*******************************************************************************/

		@@ -30,6 +30,7 @@
30	30
31	31	#include "e1000.h"
32	32
	33	+#ifdef SIOCETHTOOL
33	34	#include <asm/uaccess.h>
34	35
35	36	extern char e1000_driver_name[];

		@@ -37,14 +38,16 @@ extern char e1000_driver_version[];
37	38
38	39	extern int e1000_up(struct e1000_adapter *adapter);
39	40	extern void e1000_down(struct e1000_adapter *adapter);
	41	+extern void e1000_reinit_locked(struct e1000_adapter *adapter);
40	42	extern void e1000_reset(struct e1000_adapter *adapter);
41	43	extern int e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx);
42		-extern int e1000_setup_rx_resources(struct e1000_adapter *adapter);
43		-extern int e1000_setup_tx_resources(struct e1000_adapter *adapter);
44		-extern void e1000_free_rx_resources(struct e1000_adapter *adapter);
45		-extern void e1000_free_tx_resources(struct e1000_adapter *adapter);
	44	+extern int e1000_setup_all_rx_resources(struct e1000_adapter *adapter);
	45	+extern int e1000_setup_all_tx_resources(struct e1000_adapter *adapter);
	46	+extern void e1000_free_all_rx_resources(struct e1000_adapter *adapter);
	47	+extern void e1000_free_all_tx_resources(struct e1000_adapter *adapter);
46	48	extern void e1000_update_stats(struct e1000_adapter *adapter);
47	49
	50	+#ifdef ETHTOOL_GSTATS
48	51	struct e1000_stats {
49	52	char stat_string[ETH_GSTRING_LEN];
50	53	int sizeof_stat;

		@@ -54,31 +57,36 @@ struct e1000_stats {
54	57	#define E1000_STAT(m) sizeof(((struct e1000_adapter *)0)->m), \
55	58	offsetof(struct e1000_adapter, m)
56	59	static const struct e1000_stats e1000_gstrings_stats[] = {
57		- { "rx_packets", E1000_STAT(net_stats.rx_packets) },
58		- { "tx_packets", E1000_STAT(net_stats.tx_packets) },
59		- { "rx_bytes", E1000_STAT(net_stats.rx_bytes) },
60		- { "tx_bytes", E1000_STAT(net_stats.tx_bytes) },
	60	+ { "rx_packets", E1000_STAT(stats.gprc) },
	61	+ { "tx_packets", E1000_STAT(stats.gptc) },
	62	+ { "rx_bytes", E1000_STAT(stats.gorcl) },
	63	+ { "tx_bytes", E1000_STAT(stats.gotcl) },
	64	+ { "rx_broadcast", E1000_STAT(stats.bprc) },
	65	+ { "tx_broadcast", E1000_STAT(stats.bptc) },
	66	+ { "rx_multicast", E1000_STAT(stats.mprc) },
	67	+ { "tx_multicast", E1000_STAT(stats.mptc) },
61	68	{ "rx_errors", E1000_STAT(net_stats.rx_errors) },
62	69	{ "tx_errors", E1000_STAT(net_stats.tx_errors) },
63		- { "rx_dropped", E1000_STAT(net_stats.rx_dropped) },
64	70	{ "tx_dropped", E1000_STAT(net_stats.tx_dropped) },
65		- { "multicast", E1000_STAT(net_stats.multicast) },
66		- { "collisions", E1000_STAT(net_stats.collisions) },
	71	+ { "multicast", E1000_STAT(stats.mprc) },
	72	+ { "collisions", E1000_STAT(stats.colc) },
67	73	{ "rx_length_errors", E1000_STAT(net_stats.rx_length_errors) },
68	74	{ "rx_over_errors", E1000_STAT(net_stats.rx_over_errors) },
69		- { "rx_crc_errors", E1000_STAT(net_stats.rx_crc_errors) },
	75	+ { "rx_crc_errors", E1000_STAT(stats.crcerrs) },
70	76	{ "rx_frame_errors", E1000_STAT(net_stats.rx_frame_errors) },
71		- { "rx_fifo_errors", E1000_STAT(net_stats.rx_fifo_errors) },
72		- { "rx_missed_errors", E1000_STAT(net_stats.rx_missed_errors) },
73		- { "tx_aborted_errors", E1000_STAT(net_stats.tx_aborted_errors) },
74		- { "tx_carrier_errors", E1000_STAT(net_stats.tx_carrier_errors) },
	77	+ { "rx_no_buffer_count", E1000_STAT(stats.rnbc) },
	78	+ { "rx_missed_errors", E1000_STAT(stats.mpc) },
	79	+ { "tx_aborted_errors", E1000_STAT(stats.ecol) },
	80	+ { "tx_carrier_errors", E1000_STAT(stats.tncrs) },
75	81	{ "tx_fifo_errors", E1000_STAT(net_stats.tx_fifo_errors) },
76	82	{ "tx_heartbeat_errors", E1000_STAT(net_stats.tx_heartbeat_errors) },
77		- { "tx_window_errors", E1000_STAT(net_stats.tx_window_errors) },
	83	+ { "tx_window_errors", E1000_STAT(stats.latecol) },
78	84	{ "tx_abort_late_coll", E1000_STAT(stats.latecol) },
79	85	{ "tx_deferred_ok", E1000_STAT(stats.dc) },
80	86	{ "tx_single_coll_ok", E1000_STAT(stats.scc) },
81	87	{ "tx_multi_coll_ok", E1000_STAT(stats.mcc) },
	88	+ { "tx_timeout_count", E1000_STAT(tx_timeout_count) },
	89	+ { "tx_restart_queue", E1000_STAT(restart_queue) },
82	90	{ "rx_long_length_errors", E1000_STAT(stats.roc) },
83	91	{ "rx_short_length_errors", E1000_STAT(stats.ruc) },
84	92	{ "rx_align_errors", E1000_STAT(stats.algnerrc) },

		@@ -90,24 +98,47 @@ static const struct e1000_stats e1000_gstrings_stats[] = {
90	98	{ "tx_flow_control_xoff", E1000_STAT(stats.xofftxc) },
91	99	{ "rx_long_byte_count", E1000_STAT(stats.gorcl) },
92	100	{ "rx_csum_offload_good", E1000_STAT(hw_csum_good) },
93		- { "rx_csum_offload_errors", E1000_STAT(hw_csum_err) }
	101	+ { "rx_csum_offload_errors", E1000_STAT(hw_csum_err) },
	102	+ { "rx_header_split", E1000_STAT(rx_hdr_split) },
	103	+ { "alloc_rx_buff_failed", E1000_STAT(alloc_rx_buff_failed) },
	104	+ { "tx_smbus", E1000_STAT(stats.mgptc) },
	105	+ { "rx_smbus", E1000_STAT(stats.mgprc) },
	106	+ { "dropped_smbus", E1000_STAT(stats.mgpdc) },
	107	+#ifdef E1000_COUNT_ICR
	108	+ { "txdw", E1000_STAT(icr_txdw) },
	109	+ { "txqe", E1000_STAT(icr_txqe) },
	110	+ { "lsc", E1000_STAT(icr_lsc) },
	111	+ { "rxseq", E1000_STAT(icr_rxseq) },
	112	+ { "rxdmt", E1000_STAT(icr_rxdmt) },
	113	+ { "rxo", E1000_STAT(icr_rxo) },
	114	+ { "rxt", E1000_STAT(icr_rxt) },
	115	+ { "mdac", E1000_STAT(icr_mdac) },
	116	+ { "rxcfg", E1000_STAT(icr_rxcfg) },
	117	+ { "gpi", E1000_STAT(icr_gpi) },
	118	+#endif
94	119	};
95		-#define E1000_STATS_LEN \
	120	+
	121	+#define E1000_QUEUE_STATS_LEN 0
	122	+#define E1000_GLOBAL_STATS_LEN \
96	123	sizeof(e1000_gstrings_stats) / sizeof(struct e1000_stats)
	124	+#define E1000_STATS_LEN (E1000_GLOBAL_STATS_LEN + E1000_QUEUE_STATS_LEN)
	125	+#endif /* ETHTOOL_GSTATS */
	126	+#ifdef ETHTOOL_TEST
97	127	static const char e1000_gstrings_test[][ETH_GSTRING_LEN] = {
98	128	"Register test (offline)", "Eeprom test (offline)",
99	129	"Interrupt test (offline)", "Loopback test (offline)",
100	130	"Link test (on/offline)"
101	131	};
102	132	#define E1000_TEST_LEN sizeof(e1000_gstrings_test) / ETH_GSTRING_LEN
	133	+#endif /* ETHTOOL_TEST */
103	134
104	135	static int
105	136	e1000_get_settings(struct net_device netdev, struct ethtool_cmd ecmd)
106	137	{
107		- struct e1000_adapter *adapter = netdev->priv;
	138	+ struct e1000_adapter *adapter = netdev_priv(netdev);
108	139	struct e1000_hw *hw = &adapter->hw;
109	140
110		- if(hw->media_type == e1000_media_type_copper) {
	141	+ if (hw->media_type == e1000_media_type_copper) {
111	142
112	143	ecmd->supported = (SUPPORTED_10baseT_Half \|
113	144	SUPPORTED_10baseT_Full \|

		@@ -116,21 +147,20 @@ e1000_get_settings(struct net_device netdev, struct ethtool_cmd ecmd)
116	147	SUPPORTED_1000baseT_Full\|
117	148	SUPPORTED_Autoneg \|
118	149	SUPPORTED_TP);
119		-
	150	+ if (hw->phy_type == e1000_phy_ife)
	151	+ ecmd->supported &= ~SUPPORTED_1000baseT_Full;
120	152	ecmd->advertising = ADVERTISED_TP;
121	153
122		- if(hw->autoneg == 1) {
	154	+ if (hw->autoneg == 1) {
123	155	ecmd->advertising \|= ADVERTISED_Autoneg;
124		-
125	156	/* the e1000 autoneg seems to match ethtool nicely */
126		-
127	157	ecmd->advertising \|= hw->autoneg_advertised;
128	158	}
129	159
130	160	ecmd->port = PORT_TP;
131	161	ecmd->phy_address = hw->phy_addr;
132	162
133		- if(hw->mac_type == e1000_82543)
	163	+ if (hw->mac_type == e1000_82543)
134	164	ecmd->transceiver = XCVR_EXTERNAL;
135	165	else
136	166	ecmd->transceiver = XCVR_INTERNAL;

		@@ -140,19 +170,19 @@ e1000_get_settings(struct net_device netdev, struct ethtool_cmd ecmd)
140	170	SUPPORTED_FIBRE \|
141	171	SUPPORTED_Autoneg);
142	172
143		- ecmd->advertising = (SUPPORTED_1000baseT_Full \|
144		- SUPPORTED_FIBRE \|
145		- SUPPORTED_Autoneg);
	173	+ ecmd->advertising = (ADVERTISED_1000baseT_Full \|
	174	+ ADVERTISED_FIBRE \|
	175	+ ADVERTISED_Autoneg);
146	176
147	177	ecmd->port = PORT_FIBRE;
148	178
149		- if(hw->mac_type >= e1000_82545)
	179	+ if (hw->mac_type >= e1000_82545)
150	180	ecmd->transceiver = XCVR_INTERNAL;
151	181	else
152	182	ecmd->transceiver = XCVR_EXTERNAL;
153	183	}
154	184
155		- if(netif_carrier_ok(adapter->netdev)) {
	185	+ if (netif_carrier_ok(adapter->netdev)) {
156	186
157	187	e1000_get_speed_and_duplex(hw, &adapter->link_speed,
158	188	&adapter->link_duplex);

		@@ -161,7 +191,7 @@ e1000_get_settings(struct net_device netdev, struct ethtool_cmd ecmd)
161	191	/* unfortunatly FULL_DUPLEX != DUPLEX_FULL
162	192	* and HALF_DUPLEX != DUPLEX_HALF */
163	193
164		- if(adapter->link_duplex == FULL_DUPLEX)
	194	+ if (adapter->link_duplex == FULL_DUPLEX)
165	195	ecmd->duplex = DUPLEX_FULL;
166	196	else
167	197	ecmd->duplex = DUPLEX_HALF;

		@@ -178,26 +208,46 @@ e1000_get_settings(struct net_device netdev, struct ethtool_cmd ecmd)
178	208	static int
179	209	e1000_set_settings(struct net_device netdev, struct ethtool_cmd ecmd)
180	210	{
181		- struct e1000_adapter *adapter = netdev->priv;
	211	+ struct e1000_adapter *adapter = netdev_priv(netdev);
182	212	struct e1000_hw *hw = &adapter->hw;
183	213
184		- if(ecmd->autoneg == AUTONEG_ENABLE) {
	214	+ /* When SoL/IDER sessions are active, autoneg/speed/duplex
	215	+ * cannot be changed */
	216	+ if (e1000_check_phy_reset_block(hw)) {
	217	+ DPRINTK(DRV, ERR, "Cannot change link characteristics "
	218	+ "when SoL/IDER is active.\n");
	219	+ return -EINVAL;
	220	+ }
	221	+
	222	+ while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
	223	+ msleep(1);
	224	+
	225	+ if (ecmd->autoneg == AUTONEG_ENABLE) {
185	226	hw->autoneg = 1;
186		- hw->autoneg_advertised = 0x002F;
187		- ecmd->advertising = 0x002F;
	227	+ if (hw->media_type == e1000_media_type_fiber)
	228	+ hw->autoneg_advertised = ADVERTISED_1000baseT_Full \|
	229	+ ADVERTISED_FIBRE \|
	230	+ ADVERTISED_Autoneg;
	231	+ else
	232	+ hw->autoneg_advertised = ecmd->advertising \|
	233	+ ADVERTISED_TP \|
	234	+ ADVERTISED_Autoneg;
	235	+ ecmd->advertising = hw->autoneg_advertised;
188	236	} else
189		- if(e1000_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex))
	237	+ if (e1000_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {
	238	+ clear_bit(__E1000_RESETTING, &adapter->flags);
190	239	return -EINVAL;
	240	+ }
191	241
192	242	/* reset the link */
193	243
194		- if(netif_running(adapter->netdev)) {
	244	+ if (netif_running(adapter->netdev)) {
195	245	e1000_down(adapter);
196		- e1000_reset(adapter);
197	246	e1000_up(adapter);
198	247	} else
199	248	e1000_reset(adapter);
200	249
	250	+ clear_bit(__E1000_RESETTING, &adapter->flags);
201	251	return 0;
202	252	}
203	253

		@@ -205,17 +255,17 @@ static void
205	255	e1000_get_pauseparam(struct net_device *netdev,
206	256	struct ethtool_pauseparam *pause)
207	257	{
208		- struct e1000_adapter *adapter = netdev->priv;
	258	+ struct e1000_adapter *adapter = netdev_priv(netdev);
209	259	struct e1000_hw *hw = &adapter->hw;
210	260
211		- pause->autoneg =
	261	+ pause->autoneg =
212	262	(adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
213		-
214		- if(hw->fc == e1000_fc_rx_pause)
	263	+
	264	+ if (hw->fc == E1000_FC_RX_PAUSE)
215	265	pause->rx_pause = 1;
216		- else if(hw->fc == e1000_fc_tx_pause)
	266	+ else if (hw->fc == E1000_FC_TX_PAUSE)
217	267	pause->tx_pause = 1;
218		- else if(hw->fc == e1000_fc_full) {
	268	+ else if (hw->fc == E1000_FC_FULL) {
219	269	pause->rx_pause = 1;
220	270	pause->tx_pause = 1;
221	271	}

		@@ -225,57 +275,60 @@ static int
225	275	e1000_set_pauseparam(struct net_device *netdev,
226	276	struct ethtool_pauseparam *pause)
227	277	{
228		- struct e1000_adapter *adapter = netdev->priv;
	278	+ struct e1000_adapter *adapter = netdev_priv(netdev);
229	279	struct e1000_hw *hw = &adapter->hw;
230		-
	280	+ int retval = 0;
	281	+
231	282	adapter->fc_autoneg = pause->autoneg;
232	283
233		- if(pause->rx_pause && pause->tx_pause)
234		- hw->fc = e1000_fc_full;
235		- else if(pause->rx_pause && !pause->tx_pause)
236		- hw->fc = e1000_fc_rx_pause;
237		- else if(!pause->rx_pause && pause->tx_pause)
238		- hw->fc = e1000_fc_tx_pause;
239		- else if(!pause->rx_pause && !pause->tx_pause)
240		- hw->fc = e1000_fc_none;
	284	+ while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
	285	+ msleep(1);
	286	+
	287	+ if (pause->rx_pause && pause->tx_pause)
	288	+ hw->fc = E1000_FC_FULL;
	289	+ else if (pause->rx_pause && !pause->tx_pause)
	290	+ hw->fc = E1000_FC_RX_PAUSE;
	291	+ else if (!pause->rx_pause && pause->tx_pause)
	292	+ hw->fc = E1000_FC_TX_PAUSE;
	293	+ else if (!pause->rx_pause && !pause->tx_pause)
	294	+ hw->fc = E1000_FC_NONE;
241	295
242	296	hw->original_fc = hw->fc;
243	297
244		- if(adapter->fc_autoneg == AUTONEG_ENABLE) {
245		- if(netif_running(adapter->netdev)) {
	298	+ if (adapter->fc_autoneg == AUTONEG_ENABLE) {
	299	+ if (netif_running(adapter->netdev)) {
246	300	e1000_down(adapter);
247	301	e1000_up(adapter);
248	302	} else
249	303	e1000_reset(adapter);
250		- }
251		- else
252		- return ((hw->media_type == e1000_media_type_fiber) ?
253		- e1000_setup_link(hw) : e1000_force_mac_fc(hw));
254		-
255		- return 0;
	304	+ } else
	305	+ retval = ((hw->media_type == e1000_media_type_fiber) ?
	306	+ e1000_setup_link(hw) : e1000_force_mac_fc(hw));
	307	+
	308	+ clear_bit(__E1000_RESETTING, &adapter->flags);
	309	+ return retval;
256	310	}
257	311
258	312	static uint32_t
259	313	e1000_get_rx_csum(struct net_device *netdev)
260	314	{
261		- struct e1000_adapter *adapter = netdev->priv;
	315	+ struct e1000_adapter *adapter = netdev_priv(netdev);
262	316	return adapter->rx_csum;
263	317	}
264	318
265	319	static int
266	320	e1000_set_rx_csum(struct net_device *netdev, uint32_t data)
267	321	{
268		- struct e1000_adapter *adapter = netdev->priv;
	322	+ struct e1000_adapter *adapter = netdev_priv(netdev);
269	323	adapter->rx_csum = data;
270	324
271		- if(netif_running(netdev)) {
272		- e1000_down(adapter);
273		- e1000_up(adapter);
274		- } else
	325	+ if (netif_running(netdev))
	326	+ e1000_reinit_locked(adapter);
	327	+ else
275	328	e1000_reset(adapter);
276	329	return 0;
277	330	}
278		-
	331	+
279	332	static uint32_t
280	333	e1000_get_tx_csum(struct net_device *netdev)
281	334	{

		@@ -285,9 +338,9 @@ e1000_get_tx_csum(struct net_device *netdev)
285	338	static int
286	339	e1000_set_tx_csum(struct net_device *netdev, uint32_t data)
287	340	{
288		- struct e1000_adapter *adapter = netdev->priv;
	341	+ struct e1000_adapter *adapter = netdev_priv(netdev);
289	342
290		- if(adapter->hw.mac_type < e1000_82543) {
	343	+ if (adapter->hw.mac_type < e1000_82543) {
291	344	if (!data)
292	345	return -EINVAL;
293	346	return 0;

		@@ -301,38 +354,21 @@ e1000_set_tx_csum(struct net_device *netdev, uint32_t data)
301	354	return 0;
302	355	}
303	356
304		-#ifdef NETIF_F_TSO
305		-static int
306		-e1000_set_tso(struct net_device *netdev, uint32_t data)
307		-{
308		- struct e1000_adapter *adapter = netdev->priv;
309		- if ((adapter->hw.mac_type < e1000_82544) \|\|
310		- (adapter->hw.mac_type == e1000_82547))
311		- return data ? -EINVAL : 0;
312		-
313		- if (data)
314		- netdev->features \|= NETIF_F_TSO;
315		- else
316		- netdev->features &= ~NETIF_F_TSO;
317		- return 0;
318		-}
319		-#endif /* NETIF_F_TSO */
320		-
321	357	static uint32_t
322	358	e1000_get_msglevel(struct net_device *netdev)
323	359	{
324		- struct e1000_adapter *adapter = netdev->priv;
	360	+ struct e1000_adapter *adapter = netdev_priv(netdev);
325	361	return adapter->msg_enable;
326	362	}
327	363
328	364	static void
329	365	e1000_set_msglevel(struct net_device *netdev, uint32_t data)
330	366	{
331		- struct e1000_adapter *adapter = netdev->priv;
	367	+ struct e1000_adapter *adapter = netdev_priv(netdev);
332	368	adapter->msg_enable = data;
333	369	}
334	370
335		-static int
	371	+static int
336	372	e1000_get_regs_len(struct net_device *netdev)
337	373	{
338	374	#define E1000_REGS_LEN 32

		@@ -343,7 +379,7 @@ static void
343	379	e1000_get_regs(struct net_device *netdev,
344	380	struct ethtool_regs regs, void p)
345	381	{
346		- struct e1000_adapter *adapter = netdev->priv;
	382	+ struct e1000_adapter *adapter = netdev_priv(netdev);
347	383	struct e1000_hw *hw = &adapter->hw;
348	384	uint32_t *regs_buff = p;
349	385	uint16_t phy_data;

		@@ -368,7 +404,7 @@ e1000_get_regs(struct net_device *netdev,
368	404	regs_buff[11] = E1000_READ_REG(hw, TIDV);
369	405
370	406	regs_buff[12] = adapter->hw.phy_type; /* PHY type (IGP=1, M88=0) */
371		- if(hw->phy_type == e1000_phy_igp) {
	407	+ if (hw->phy_type == e1000_phy_igp) {
372	408	e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
373	409	IGP01E1000_PHY_AGC_A);
374	410	e1000_read_phy_reg(hw, IGP01E1000_PHY_AGC_A &

		@@ -404,12 +440,12 @@ e1000_get_regs(struct net_device *netdev,
404	440	regs_buff[23] = regs_buff[18]; /* mdix mode */
405	441	e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0);
406	442	} else {
407		- e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
	443	+ e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
408	444	regs_buff[13] = (uint32_t)phy_data; /* cable length */
409	445	regs_buff[14] = 0; /* Dummy (to align w/ IGP phy reg dump) */
410	446	regs_buff[15] = 0; /* Dummy (to align w/ IGP phy reg dump) */
411	447	regs_buff[16] = 0; /* Dummy (to align w/ IGP phy reg dump) */
412		- e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
	448	+ e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
413	449	regs_buff[17] = (uint32_t)phy_data; /* extended 10bt distance */
414	450	regs_buff[18] = regs_buff[13]; /* cable polarity */
415	451	regs_buff[19] = 0; /* Dummy (to align w/ IGP phy reg dump) */

		@@ -422,8 +458,9 @@ e1000_get_regs(struct net_device *netdev,
422	458	e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
423	459	regs_buff[24] = (uint32_t)phy_data; /* phy local receiver status */
424	460	regs_buff[25] = regs_buff[24]; /* phy remote receiver status */
425		- if(hw->mac_type >= e1000_82540 &&
426		- hw->media_type == e1000_media_type_copper) {
	461	+ if (hw->mac_type >= e1000_82540 &&
	462	+ hw->mac_type < e1000_82571 &&
	463	+ hw->media_type == e1000_media_type_copper) {
427	464	regs_buff[26] = E1000_READ_REG(hw, MANC);
428	465	}
429	466	}

		@@ -431,7 +468,7 @@ e1000_get_regs(struct net_device *netdev,
431	468	static int
432	469	e1000_get_eeprom_len(struct net_device *netdev)
433	470	{
434		- struct e1000_adapter *adapter = netdev->priv;
	471	+ struct e1000_adapter *adapter = netdev_priv(netdev);
435	472	return adapter->hw.eeprom.word_size * 2;
436	473	}
437	474

		@@ -439,14 +476,14 @@ static int
439	476	e1000_get_eeprom(struct net_device *netdev,
440	477	struct ethtool_eeprom eeprom, uint8_t bytes)
441	478	{
442		- struct e1000_adapter *adapter = netdev->priv;
	479	+ struct e1000_adapter *adapter = netdev_priv(netdev);
443	480	struct e1000_hw *hw = &adapter->hw;
444	481	uint16_t *eeprom_buff;
445	482	int first_word, last_word;
446	483	int ret_val = 0;
447	484	uint16_t i;
448	485
449		- if(eeprom->len == 0)
	486	+ if (eeprom->len == 0)
450	487	return -EINVAL;
451	488
452	489	eeprom->magic = hw->vendor_id \| (hw->device_id << 16);

		@@ -456,16 +493,16 @@ e1000_get_eeprom(struct net_device *netdev,
456	493
457	494	eeprom_buff = kmalloc(sizeof(uint16_t) *
458	495	(last_word - first_word + 1), GFP_KERNEL);
459		- if(!eeprom_buff)
	496	+ if (!eeprom_buff)
460	497	return -ENOMEM;
461	498
462		- if(hw->eeprom.type == e1000_eeprom_spi)
	499	+ if (hw->eeprom.type == e1000_eeprom_spi)
463	500	ret_val = e1000_read_eeprom(hw, first_word,
464	501	last_word - first_word + 1,
465	502	eeprom_buff);
466	503	else {
467	504	for (i = 0; i < last_word - first_word + 1; i++)
468		- if((ret_val = e1000_read_eeprom(hw, first_word + i, 1,
	505	+ if ((ret_val = e1000_read_eeprom(hw, first_word + i, 1,
469	506	&eeprom_buff[i])))
470	507	break;
471	508	}

		@@ -485,17 +522,17 @@ static int
485	522	e1000_set_eeprom(struct net_device *netdev,
486	523	struct ethtool_eeprom eeprom, uint8_t bytes)
487	524	{
488		- struct e1000_adapter *adapter = netdev->priv;
	525	+ struct e1000_adapter *adapter = netdev_priv(netdev);
489	526	struct e1000_hw *hw = &adapter->hw;
490	527	uint16_t *eeprom_buff;
491	528	void *ptr;
492	529	int max_len, first_word, last_word, ret_val = 0;
493	530	uint16_t i;
494	531
495		- if(eeprom->len == 0)
	532	+ if (eeprom->len == 0)
496	533	return -EOPNOTSUPP;
497	534
498		- if(eeprom->magic != (hw->vendor_id \| (hw->device_id << 16)))
	535	+ if (eeprom->magic != (hw->vendor_id \| (hw->device_id << 16)))
499	536	return -EFAULT;
500	537
501	538	max_len = hw->eeprom.word_size * 2;

		@@ -503,19 +540,19 @@ e1000_set_eeprom(struct net_device *netdev,
503	540	first_word = eeprom->offset >> 1;
504	541	last_word = (eeprom->offset + eeprom->len - 1) >> 1;
505	542	eeprom_buff = kmalloc(max_len, GFP_KERNEL);
506		- if(!eeprom_buff)
	543	+ if (!eeprom_buff)
507	544	return -ENOMEM;
508	545
509	546	ptr = (void *)eeprom_buff;
510	547
511		- if(eeprom->offset & 1) {
	548	+ if (eeprom->offset & 1) {
512	549	/* need read/modify/write of first changed EEPROM word */
513	550	/* only the second byte of the word is being modified */
514	551	ret_val = e1000_read_eeprom(hw, first_word, 1,
515	552	&eeprom_buff[0]);
516	553	ptr++;
517	554	}
518		- if(((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
	555	+ if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
519	556	/* need read/modify/write of last changed EEPROM word */
520	557	/* only the first byte of the word is being modified */
521	558	ret_val = e1000_read_eeprom(hw, last_word, 1,

		@@ -534,8 +571,10 @@ e1000_set_eeprom(struct net_device *netdev,
534	571	ret_val = e1000_write_eeprom(hw, first_word,
535	572	last_word - first_word + 1, eeprom_buff);
536	573
537		- /* Update the checksum over the first part of the EEPROM if needed */
538		- if((ret_val == 0) && first_word <= EEPROM_CHECKSUM_REG)
	574	+ /* Update the checksum over the first part of the EEPROM if needed
	575	+ * and flush shadow RAM for 82573 conrollers */
	576	+ if ((ret_val == 0) && ((first_word <= EEPROM_CHECKSUM_REG) \|\|
	577	+ (hw->mac_type == e1000_82573)))
539	578	e1000_update_eeprom_checksum(hw);
540	579
541	580	kfree(eeprom_buff);

		@@ -546,11 +585,32 @@ static void
546	585	e1000_get_drvinfo(struct net_device *netdev,
547	586	struct ethtool_drvinfo *drvinfo)
548	587	{
549		- struct e1000_adapter *adapter = netdev->priv;
	588	+ struct e1000_adapter *adapter = netdev_priv(netdev);
	589	+ char firmware_version[32];
	590	+ uint16_t eeprom_data;
550	591
551	592	strncpy(drvinfo->driver, e1000_driver_name, 32);
552	593	strncpy(drvinfo->version, e1000_driver_version, 32);
553		- strncpy(drvinfo->fw_version, "N/A", 32);
	594	+
	595	+ /* EEPROM image version # is reported as firmware version # for
	596	+ * 8257{1\|2\|3} controllers */
	597	+ e1000_read_eeprom(&adapter->hw, 5, 1, &eeprom_data);
	598	+ switch (adapter->hw.mac_type) {
	599	+ case e1000_82571:
	600	+ case e1000_82572:
	601	+ case e1000_82573:
	602	+ case e1000_80003es2lan:
	603	+ case e1000_ich8lan:
	604	+ sprintf(firmware_version, "%d.%d-%d",
	605	+ (eeprom_data & 0xF000) >> 12,
	606	+ (eeprom_data & 0x0FF0) >> 4,
	607	+ eeprom_data & 0x000F);
	608	+ break;
	609	+ default:
	610	+ sprintf(firmware_version, "N/A");
	611	+ }
	612	+
	613	+ strncpy(drvinfo->fw_version, firmware_version, 32);
554	614	strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
555	615	drvinfo->n_stats = E1000_STATS_LEN;
556	616	drvinfo->testinfo_len = E1000_TEST_LEN;

		@@ -562,10 +622,10 @@ static void
562	622	e1000_get_ringparam(struct net_device *netdev,
563	623	struct ethtool_ringparam *ring)
564	624	{
565		- struct e1000_adapter *adapter = netdev->priv;
	625	+ struct e1000_adapter *adapter = netdev_priv(netdev);
566	626	e1000_mac_type mac_type = adapter->hw.mac_type;
567		- struct e1000_desc_ring *txdr = &adapter->tx_ring;
568		- struct e1000_desc_ring *rxdr = &adapter->rx_ring;
	627	+ struct e1000_tx_ring *txdr = adapter->tx_ring;
	628	+ struct e1000_rx_ring *rxdr = adapter->rx_ring;
569	629
570	630	ring->rx_max_pending = (mac_type < e1000_82544) ? E1000_MAX_RXD :
571	631	E1000_MAX_82544_RXD;

		@@ -579,65 +639,94 @@ e1000_get_ringparam(struct net_device *netdev,
579	639	ring->rx_jumbo_pending = 0;
580	640	}
581	641
582		-static int
	642	+static int
583	643	e1000_set_ringparam(struct net_device *netdev,
584	644	struct ethtool_ringparam *ring)
585	645	{
586		- struct e1000_adapter *adapter = netdev->priv;
	646	+ struct e1000_adapter *adapter = netdev_priv(netdev);
587	647	e1000_mac_type mac_type = adapter->hw.mac_type;
588		- struct e1000_desc_ring *txdr = &adapter->tx_ring;
589		- struct e1000_desc_ring *rxdr = &adapter->rx_ring;
590		- struct e1000_desc_ring tx_old, tx_new, rx_old, rx_new;
591		- int err;
	648	+ struct e1000_tx_ring txdr, tx_old;
	649	+ struct e1000_rx_ring rxdr, rx_old;
	650	+ int i, err, tx_ring_size, rx_ring_size;
	651	+
	652	+ if ((ring->rx_mini_pending) \|\| (ring->rx_jumbo_pending))
	653	+ return -EINVAL;
	654	+
	655	+ tx_ring_size = sizeof(struct e1000_tx_ring) * adapter->num_tx_queues;
	656	+ rx_ring_size = sizeof(struct e1000_rx_ring) * adapter->num_rx_queues;
	657	+
	658	+ while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
	659	+ msleep(1);
	660	+
	661	+ if (netif_running(adapter->netdev))
	662	+ e1000_down(adapter);
592	663
593	664	tx_old = adapter->tx_ring;
594	665	rx_old = adapter->rx_ring;
595	666
596		- if ((ring->rx_mini_pending) \|\| (ring->rx_jumbo_pending))
597		- return -EINVAL;
	667	+ err = -ENOMEM;
	668	+ txdr = kzalloc(tx_ring_size, GFP_KERNEL);
	669	+ if (!txdr)
	670	+ goto err_alloc_tx;
598	671
599		- if(netif_running(adapter->netdev))
600		- e1000_down(adapter);
	672	+ rxdr = kzalloc(rx_ring_size, GFP_KERNEL);
	673	+ if (!rxdr)
	674	+ goto err_alloc_rx;
	675	+
	676	+ adapter->tx_ring = txdr;
	677	+ adapter->rx_ring = rxdr;
601	678
602	679	rxdr->count = max(ring->rx_pending,(uint32_t)E1000_MIN_RXD);
603	680	rxdr->count = min(rxdr->count,(uint32_t)(mac_type < e1000_82544 ?
604	681	E1000_MAX_RXD : E1000_MAX_82544_RXD));
605		- E1000_ROUNDUP(rxdr->count, REQ_RX_DESCRIPTOR_MULTIPLE);
	682	+ E1000_ROUNDUP(rxdr->count, REQ_RX_DESCRIPTOR_MULTIPLE);
606	683
607	684	txdr->count = max(ring->tx_pending,(uint32_t)E1000_MIN_TXD);
608	685	txdr->count = min(txdr->count,(uint32_t)(mac_type < e1000_82544 ?
609	686	E1000_MAX_TXD : E1000_MAX_82544_TXD));
610		- E1000_ROUNDUP(txdr->count, REQ_TX_DESCRIPTOR_MULTIPLE);
	687	+ E1000_ROUNDUP(txdr->count, REQ_TX_DESCRIPTOR_MULTIPLE);
611	688
612		- if(netif_running(adapter->netdev)) {
	689	+ for (i = 0; i < adapter->num_tx_queues; i++)
	690	+ txdr[i].count = txdr->count;
	691	+ for (i = 0; i < adapter->num_rx_queues; i++)
	692	+ rxdr[i].count = rxdr->count;
	693	+
	694	+ if (netif_running(adapter->netdev)) {
613	695	/* Try to get new resources before deleting old */
614		- if((err = e1000_setup_rx_resources(adapter)))
	696	+ if ((err = e1000_setup_all_rx_resources(adapter)))
615	697	goto err_setup_rx;
616		- if((err = e1000_setup_tx_resources(adapter)))
	698	+ if ((err = e1000_setup_all_tx_resources(adapter)))
617	699	goto err_setup_tx;
618	700
619	701	/* save the new, restore the old in order to free it,
620	702	* then restore the new back again */
621	703
622		- rx_new = adapter->rx_ring;
623		- tx_new = adapter->tx_ring;
624	704	adapter->rx_ring = rx_old;
625	705	adapter->tx_ring = tx_old;
626		- e1000_free_rx_resources(adapter);
627		- e1000_free_tx_resources(adapter);
628		- adapter->rx_ring = rx_new;
629		- adapter->tx_ring = tx_new;
630		- if((err = e1000_up(adapter)))
631		- return err;
	706	+ e1000_free_all_rx_resources(adapter);
	707	+ e1000_free_all_tx_resources(adapter);
	708	+ kfree(tx_old);
	709	+ kfree(rx_old);
	710	+ adapter->rx_ring = rxdr;
	711	+ adapter->tx_ring = txdr;
	712	+ if ((err = e1000_up(adapter)))
	713	+ goto err_setup;
632	714	}
633	715
	716	+ clear_bit(__E1000_RESETTING, &adapter->flags);
634	717	return 0;
635	718	err_setup_tx:
636		- e1000_free_rx_resources(adapter);
	719	+ e1000_free_all_rx_resources(adapter);
637	720	err_setup_rx:
638	721	adapter->rx_ring = rx_old;
639	722	adapter->tx_ring = tx_old;
	723	+ kfree(rxdr);
	724	+err_alloc_rx:
	725	+ kfree(txdr);
	726	+err_alloc_tx:
640	727	e1000_up(adapter);
	728	+err_setup:
	729	+ clear_bit(__E1000_RESETTING, &adapter->flags);
641	730	return err;
642	731	}
643	732

		@@ -646,10 +735,13 @@ err_setup_rx:
646	735	uint32_t pat, value; \
647	736	uint32_t test[] = \
648	737	{0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \
649		- for(pat = 0; pat < sizeof(test)/sizeof(test[0]); pat++) { \
	738	+ for (pat = 0; pat < sizeof(test)/sizeof(test[0]); pat++) { \
650	739	E1000_WRITE_REG(&adapter->hw, R, (test[pat] & W)); \
651	740	value = E1000_READ_REG(&adapter->hw, R); \
652		- if(value != (test[pat] & W & M)) { \
	741	+ if (value != (test[pat] & W & M)) { \
	742	+ DPRINTK(DRV, ERR, "pattern test reg %04X failed: got " \
	743	+ "0x%08X expected 0x%08X\n", \
	744	+ E1000_##R, value, (test[pat] & W & M)); \
653	745	*data = (adapter->hw.mac_type < e1000_82543) ? \
654	746	E1000_82542_##R : E1000_##R; \
655	747	return 1; \

		@@ -663,6 +755,8 @@ err_setup_rx:
663	755	E1000_WRITE_REG(&adapter->hw, R, W & M); \
664	756	value = E1000_READ_REG(&adapter->hw, R); \
665	757	if ((W & M) != (value & M)) { \
	758	+ DPRINTK(DRV, ERR, "set/check reg %04X test failed: got 0x%08X "\
	759	+ "expected 0x%08X\n", E1000_##R, (value & M), (W & M)); \
666	760	*data = (adapter->hw.mac_type < e1000_82543) ? \
667	761	E1000_82542_##R : E1000_##R; \
668	762	return 1; \

		@@ -672,23 +766,48 @@ err_setup_rx:
672	766	static int
673	767	e1000_reg_test(struct e1000_adapter adapter, uint64_t data)
674	768	{
675		- uint32_t value;
676		- uint32_t i;
	769	+ uint32_t value, before, after;
	770	+ uint32_t i, toggle;
677	771
678	772	/* The status register is Read Only, so a write should fail.
679	773	* Some bits that get toggled are ignored.
680	774	*/
681		- value = (E1000_READ_REG(&adapter->hw, STATUS) & (0xFFFFF833));
682		- E1000_WRITE_REG(&adapter->hw, STATUS, (0xFFFFFFFF));
683		- if(value != (E1000_READ_REG(&adapter->hw, STATUS) & (0xFFFFF833))) {
	775	+ switch (adapter->hw.mac_type) {
	776	+ /* there are several bits on newer hardware that are r/w */
	777	+ case e1000_82571:
	778	+ case e1000_82572:
	779	+ case e1000_80003es2lan:
	780	+ toggle = 0x7FFFF3FF;
	781	+ break;
	782	+ case e1000_82573:
	783	+ case e1000_ich8lan:
	784	+ toggle = 0x7FFFF033;
	785	+ break;
	786	+ default:
	787	+ toggle = 0xFFFFF833;
	788	+ break;
	789	+ }
	790	+
	791	+ before = E1000_READ_REG(&adapter->hw, STATUS);
	792	+ value = (E1000_READ_REG(&adapter->hw, STATUS) & toggle);
	793	+ E1000_WRITE_REG(&adapter->hw, STATUS, toggle);
	794	+ after = E1000_READ_REG(&adapter->hw, STATUS) & toggle;
	795	+ if (value != after) {
	796	+ DPRINTK(DRV, ERR, "failed STATUS register test got: "
	797	+ "0x%08X expected: 0x%08X\n", after, value);
684	798	*data = 1;
685	799	return 1;
686	800	}
	801	+ /* restore previous status */
	802	+ E1000_WRITE_REG(&adapter->hw, STATUS, before);
	803	+
	804	+ if (adapter->hw.mac_type != e1000_ich8lan) {
	805	+ REG_PATTERN_TEST(FCAL, 0xFFFFFFFF, 0xFFFFFFFF);
	806	+ REG_PATTERN_TEST(FCAH, 0x0000FFFF, 0xFFFFFFFF);
	807	+ REG_PATTERN_TEST(FCT, 0x0000FFFF, 0xFFFFFFFF);
	808	+ REG_PATTERN_TEST(VET, 0x0000FFFF, 0xFFFFFFFF);
	809	+ }
687	810
688		- REG_PATTERN_TEST(FCAL, 0xFFFFFFFF, 0xFFFFFFFF);
689		- REG_PATTERN_TEST(FCAH, 0x0000FFFF, 0xFFFFFFFF);
690		- REG_PATTERN_TEST(FCT, 0x0000FFFF, 0xFFFFFFFF);
691		- REG_PATTERN_TEST(VET, 0x0000FFFF, 0xFFFFFFFF);
692	811	REG_PATTERN_TEST(RDTR, 0x0000FFFF, 0xFFFFFFFF);
693	812	REG_PATTERN_TEST(RDBAH, 0xFFFFFFFF, 0xFFFFFFFF);
694	813	REG_PATTERN_TEST(RDLEN, 0x000FFF80, 0x000FFFFF);

		@@ -701,22 +820,25 @@ e1000_reg_test(struct e1000_adapter adapter, uint64_t data)
701	820	REG_PATTERN_TEST(TDLEN, 0x000FFF80, 0x000FFFFF);
702	821
703	822	REG_SET_AND_CHECK(RCTL, 0xFFFFFFFF, 0x00000000);
704		- REG_SET_AND_CHECK(RCTL, 0x06DFB3FE, 0x003FFFFB);
	823	+
	824	+ before = (adapter->hw.mac_type == e1000_ich8lan ?
	825	+ 0x06C3B33E : 0x06DFB3FE);
	826	+ REG_SET_AND_CHECK(RCTL, before, 0x003FFFFB);
705	827	REG_SET_AND_CHECK(TCTL, 0xFFFFFFFF, 0x00000000);
706	828
707		- if(adapter->hw.mac_type >= e1000_82543) {
	829	+ if (adapter->hw.mac_type >= e1000_82543) {
708	830
709		- REG_SET_AND_CHECK(RCTL, 0x06DFB3FE, 0xFFFFFFFF);
	831	+ REG_SET_AND_CHECK(RCTL, before, 0xFFFFFFFF);
710	832	REG_PATTERN_TEST(RDBAL, 0xFFFFFFF0, 0xFFFFFFFF);
711		- REG_PATTERN_TEST(TXCW, 0xC000FFFF, 0x0000FFFF);
	833	+ if (adapter->hw.mac_type != e1000_ich8lan)
	834	+ REG_PATTERN_TEST(TXCW, 0xC000FFFF, 0x0000FFFF);
712	835	REG_PATTERN_TEST(TDBAL, 0xFFFFFFF0, 0xFFFFFFFF);
713	836	REG_PATTERN_TEST(TIDV, 0x0000FFFF, 0x0000FFFF);
714		-
715		- for(i = 0; i < E1000_RAR_ENTRIES; i++) {
716		- REG_PATTERN_TEST(RA + ((i << 1) << 2), 0xFFFFFFFF,
717		- 0xFFFFFFFF);
	837	+ value = (adapter->hw.mac_type == e1000_ich8lan ?
	838	+ E1000_RAR_ENTRIES_ICH8LAN : E1000_RAR_ENTRIES);
	839	+ for (i = 0; i < value; i++) {
718	840	REG_PATTERN_TEST(RA + (((i << 1) + 1) << 2), 0x8003FFFF,
719		- 0xFFFFFFFF);
	841	+ 0xFFFFFFFF);
720	842	}
721	843
722	844	} else {

		@@ -728,7 +850,9 @@ e1000_reg_test(struct e1000_adapter adapter, uint64_t data)
728	850
729	851	}
730	852
731		- for(i = 0; i < E1000_MC_TBL_SIZE; i++)
	853	+ value = (adapter->hw.mac_type == e1000_ich8lan ?
	854	+ E1000_MC_TBL_SIZE_ICHXLAN : E1000_MC_TBL_SIZE);
	855	+ for (i = 0; i < value; i++)
732	856	REG_PATTERN_TEST(MTA + (i << 2), 0xFFFFFFFF, 0xFFFFFFFF);
733	857
734	858	*data = 0;

		@@ -744,8 +868,8 @@ e1000_eeprom_test(struct e1000_adapter adapter, uint64_t data)
744	868
745	869	*data = 0;
746	870	/* Read and add up the contents of the EEPROM */
747		- for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
748		- if((e1000_read_eeprom(&adapter->hw, i, 1, &temp)) < 0) {
	871	+ for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
	872	+ if ((e1000_read_eeprom(&adapter->hw, i, 1, &temp)) < 0) {
749	873	*data = 1;
750	874	break;
751	875	}

		@@ -753,19 +877,17 @@ e1000_eeprom_test(struct e1000_adapter adapter, uint64_t data)
753	877	}
754	878
755	879	/* If Checksum is not Correct return error else test passed */
756		- if((checksum != (uint16_t) EEPROM_SUM) && !(*data))
	880	+ if ((checksum != (uint16_t) EEPROM_SUM) && !(*data))
757	881	*data = 2;
758	882
759	883	return *data;
760	884	}
761	885
762	886	static irqreturn_t
763		-e1000_test_intr(int irq,
764		- void *data,
765		- struct pt_regs *regs)
	887	+e1000_test_intr(int irq, void *data)
766	888	{
767	889	struct net_device netdev = (struct net_device ) data;
768		- struct e1000_adapter *adapter = netdev->priv;
	890	+ struct e1000_adapter *adapter = netdev_priv(netdev);
769	891
770	892	adapter->test_icr \|= E1000_READ_REG(&adapter->hw, ICR);
771	893

		@@ -776,46 +898,53 @@ static int
776	898	e1000_intr_test(struct e1000_adapter adapter, uint64_t data)
777	899	{
778	900	struct net_device *netdev = adapter->netdev;
779		- uint32_t mask, i=0, shared_int = TRUE;
780		- uint32_t irq = adapter->pdev->irq;
	901	+ uint32_t mask, i=0, shared_int = TRUE;
	902	+ uint32_t irq = adapter->pdev->irq;
781	903
782	904	*data = 0;
783	905
	906	+ /* NOTE: we don't test MSI interrupts here, yet */
784	907	/* Hook up test interrupt handler just for this test */
785		- if(!request_irq(irq, &e1000_test_intr, 0, netdev->name, netdev)) {
786		- shared_int = FALSE;
787		- } else if(request_irq(irq, &e1000_test_intr, SA_SHIRQ,
788		- netdev->name, netdev)){
	908	+ if (!request_irq(irq, &e1000_test_intr, IRQF_PROBE_SHARED, netdev->name,
	909	+ netdev))
	910	+ shared_int = FALSE;
	911	+ else if (request_irq(irq, &e1000_test_intr, IRQF_SHARED,
	912	+ netdev->name, netdev)) {
789	913	*data = 1;
790	914	return -1;
791	915	}
	916	+ DPRINTK(HW, INFO, "testing %s interrupt\n",
	917	+ (shared_int ? "shared" : "unshared"));
792	918
793	919	/* Disable all the interrupts */
794	920	E1000_WRITE_REG(&adapter->hw, IMC, 0xFFFFFFFF);
795		- msec_delay(10);
	921	+ msleep(10);
796	922
797	923	/* Test each interrupt */
798		- for(; i < 10; i++) {
	924	+ for (; i < 10; i++) {
	925	+
	926	+ if (adapter->hw.mac_type == e1000_ich8lan && i == 8)
	927	+ continue;
799	928
800	929	/* Interrupt to test */
801	930	mask = 1 << i;
802	931
803		- if(!shared_int) {
804		- /* Disable the interrupt to be reported in
805		- * the cause register and then force the same
806		- * interrupt and see if one gets posted. If
807		- * an interrupt was posted to the bus, the
808		- * test failed.
809		- */
810		- adapter->test_icr = 0;
811		- E1000_WRITE_REG(&adapter->hw, IMC, mask);
812		- E1000_WRITE_REG(&adapter->hw, ICS, mask);
813		- msec_delay(10);
814		-
815		- if(adapter->test_icr & mask) {
816		- *data = 3;
817		- break;
818		- }
	932	+ if (!shared_int) {
	933	+ /* Disable the interrupt to be reported in
	934	+ * the cause register and then force the same
	935	+ * interrupt and see if one gets posted. If
	936	+ * an interrupt was posted to the bus, the
	937	+ * test failed.
	938	+ */
	939	+ adapter->test_icr = 0;
	940	+ E1000_WRITE_REG(&adapter->hw, IMC, mask);
	941	+ E1000_WRITE_REG(&adapter->hw, ICS, mask);
	942	+ msleep(10);
	943	+
	944	+ if (adapter->test_icr & mask) {
	945	+ *data = 3;
	946	+ break;
	947	+ }
819	948	}
820	949
821	950	/* Enable the interrupt to be reported in

		@@ -827,14 +956,14 @@ e1000_intr_test(struct e1000_adapter adapter, uint64_t data)
827	956	adapter->test_icr = 0;
828	957	E1000_WRITE_REG(&adapter->hw, IMS, mask);
829	958	E1000_WRITE_REG(&adapter->hw, ICS, mask);
830		- msec_delay(10);
	959	+ msleep(10);
831	960
832		- if(!(adapter->test_icr & mask)) {
	961	+ if (!(adapter->test_icr & mask)) {
833	962	*data = 4;
834	963	break;
835	964	}
836	965
837		- if(!shared_int) {
	966	+ if (!shared_int) {
838	967	/* Disable the other interrupts to be reported in
839	968	* the cause register and then force the other
840	969	* interrupts and see if any get posted. If

		@@ -842,13 +971,11 @@ e1000_intr_test(struct e1000_adapter adapter, uint64_t data)
842	971	* test failed.
843	972	*/
844	973	adapter->test_icr = 0;
845		- E1000_WRITE_REG(&adapter->hw, IMC,
846		- (~mask & 0x00007FFF));
847		- E1000_WRITE_REG(&adapter->hw, ICS,
848		- (~mask & 0x00007FFF));
849		- msec_delay(10);
	974	+ E1000_WRITE_REG(&adapter->hw, IMC, ~mask & 0x00007FFF);
	975	+ E1000_WRITE_REG(&adapter->hw, ICS, ~mask & 0x00007FFF);
	976	+ msleep(10);
850	977
851		- if(adapter->test_icr) {
	978	+ if (adapter->test_icr) {
852	979	*data = 5;
853	980	break;
854	981	}

		@@ -857,7 +984,7 @@ e1000_intr_test(struct e1000_adapter adapter, uint64_t data)
857	984
858	985	/* Disable all the interrupts */
859	986	E1000_WRITE_REG(&adapter->hw, IMC, 0xFFFFFFFF);
860		- msec_delay(10);
	987	+ msleep(10);
861	988
862	989	/* Unhook test interrupt handler */
863	990	free_irq(irq, netdev);

		@@ -868,42 +995,46 @@ e1000_intr_test(struct e1000_adapter adapter, uint64_t data)
868	995	static void
869	996	e1000_free_desc_rings(struct e1000_adapter *adapter)
870	997	{
871		- struct e1000_desc_ring *txdr = &adapter->test_tx_ring;
872		- struct e1000_desc_ring *rxdr = &adapter->test_rx_ring;
	998	+ struct e1000_tx_ring *txdr = &adapter->test_tx_ring;
	999	+ struct e1000_rx_ring *rxdr = &adapter->test_rx_ring;
873	1000	struct pci_dev *pdev = adapter->pdev;
874	1001	int i;
875	1002
876		- if(txdr->desc && txdr->buffer_info) {
877		- for(i = 0; i < txdr->count; i++) {
878		- if(txdr->buffer_info[i].dma)
	1003	+ if (txdr->desc && txdr->buffer_info) {
	1004	+ for (i = 0; i < txdr->count; i++) {
	1005	+ if (txdr->buffer_info[i].dma)
879	1006	pci_unmap_single(pdev, txdr->buffer_info[i].dma,
880	1007	txdr->buffer_info[i].length,
881	1008	PCI_DMA_TODEVICE);
882		- if(txdr->buffer_info[i].skb)
	1009	+ if (txdr->buffer_info[i].skb)
883	1010	dev_kfree_skb(txdr->buffer_info[i].skb);
884	1011	}
885	1012	}
886	1013
887		- if(rxdr->desc && rxdr->buffer_info) {
888		- for(i = 0; i < rxdr->count; i++) {
889		- if(rxdr->buffer_info[i].dma)
	1014	+ if (rxdr->desc && rxdr->buffer_info) {
	1015	+ for (i = 0; i < rxdr->count; i++) {
	1016	+ if (rxdr->buffer_info[i].dma)
890	1017	pci_unmap_single(pdev, rxdr->buffer_info[i].dma,
891	1018	rxdr->buffer_info[i].length,
892	1019	PCI_DMA_FROMDEVICE);
893		- if(rxdr->buffer_info[i].skb)
	1020	+ if (rxdr->buffer_info[i].skb)
894	1021	dev_kfree_skb(rxdr->buffer_info[i].skb);
895	1022	}
896	1023	}
897	1024
898		- if(txdr->desc)
	1025	+ if (txdr->desc) {
899	1026	pci_free_consistent(pdev, txdr->size, txdr->desc, txdr->dma);
900		- if(rxdr->desc)
	1027	+ txdr->desc = NULL;
	1028	+ }
	1029	+ if (rxdr->desc) {
901	1030	pci_free_consistent(pdev, rxdr->size, rxdr->desc, rxdr->dma);
	1031	+ rxdr->desc = NULL;
	1032	+ }
902	1033
903		- if(txdr->buffer_info)
904		- kfree(txdr->buffer_info);
905		- if(rxdr->buffer_info)
906		- kfree(rxdr->buffer_info);
	1034	+ kfree(txdr->buffer_info);
	1035	+ txdr->buffer_info = NULL;
	1036	+ kfree(rxdr->buffer_info);
	1037	+ rxdr->buffer_info = NULL;
907	1038
908	1039	return;
909	1040	}

		@@ -911,18 +1042,19 @@ e1000_free_desc_rings(struct e1000_adapter *adapter)
911	1042	static int
912	1043	e1000_setup_desc_rings(struct e1000_adapter *adapter)
913	1044	{
914		- struct e1000_desc_ring *txdr = &adapter->test_tx_ring;
915		- struct e1000_desc_ring *rxdr = &adapter->test_rx_ring;
	1045	+ struct e1000_tx_ring *txdr = &adapter->test_tx_ring;
	1046	+ struct e1000_rx_ring *rxdr = &adapter->test_rx_ring;
916	1047	struct pci_dev *pdev = adapter->pdev;
917	1048	uint32_t rctl;
918	1049	int size, i, ret_val;
919	1050
920	1051	/* Setup Tx descriptor ring and Tx buffers */
921	1052
922		- txdr->count = 80;
	1053	+ if (!txdr->count)
	1054	+ txdr->count = E1000_DEFAULT_TXD;
923	1055
924	1056	size = txdr->count * sizeof(struct e1000_buffer);
925		- if(!(txdr->buffer_info = kmalloc(size, GFP_KERNEL))) {
	1057	+ if (!(txdr->buffer_info = kmalloc(size, GFP_KERNEL))) {
926	1058	ret_val = 1;
927	1059	goto err_nomem;
928	1060	}

		@@ -930,7 +1062,7 @@ e1000_setup_desc_rings(struct e1000_adapter *adapter)
930	1062
931	1063	txdr->size = txdr->count * sizeof(struct e1000_tx_desc);
932	1064	E1000_ROUNDUP(txdr->size, 4096);
933		- if(!(txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma))) {
	1065	+ if (!(txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma))) {
934	1066	ret_val = 2;
935	1067	goto err_nomem;
936	1068	}

		@@ -949,12 +1081,12 @@ e1000_setup_desc_rings(struct e1000_adapter *adapter)
949	1081	E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT \|
950	1082	E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT);
951	1083
952		- for(i = 0; i < txdr->count; i++) {
	1084	+ for (i = 0; i < txdr->count; i++) {
953	1085	struct e1000_tx_desc tx_desc = E1000_TX_DESC(txdr, i);
954	1086	struct sk_buff *skb;
955	1087	unsigned int size = 1024;
956	1088
957		- if(!(skb = alloc_skb(size, GFP_KERNEL))) {
	1089	+ if (!(skb = alloc_skb(size, GFP_KERNEL))) {
958	1090	ret_val = 3;
959	1091	goto err_nomem;
960	1092	}

		@@ -974,17 +1106,18 @@ e1000_setup_desc_rings(struct e1000_adapter *adapter)
974	1106
975	1107	/* Setup Rx descriptor ring and Rx buffers */
976	1108
977		- rxdr->count = 80;
	1109	+ if (!rxdr->count)
	1110	+ rxdr->count = E1000_DEFAULT_RXD;
978	1111
979	1112	size = rxdr->count * sizeof(struct e1000_buffer);
980		- if(!(rxdr->buffer_info = kmalloc(size, GFP_KERNEL))) {
	1113	+ if (!(rxdr->buffer_info = kmalloc(size, GFP_KERNEL))) {
981	1114	ret_val = 4;
982	1115	goto err_nomem;
983	1116	}
984	1117	memset(rxdr->buffer_info, 0, size);
985	1118
986	1119	rxdr->size = rxdr->count * sizeof(struct e1000_rx_desc);
987		- if(!(rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma))) {
	1120	+ if (!(rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma))) {
988	1121	ret_val = 5;
989	1122	goto err_nomem;
990	1123	}

		@@ -1004,15 +1137,16 @@ e1000_setup_desc_rings(struct e1000_adapter *adapter)
1004	1137	(adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
1005	1138	E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1006	1139
1007		- for(i = 0; i < rxdr->count; i++) {
	1140	+ for (i = 0; i < rxdr->count; i++) {
1008	1141	struct e1000_rx_desc rx_desc = E1000_RX_DESC(rxdr, i);
1009	1142	struct sk_buff *skb;
1010	1143
1011		- if(!(skb = alloc_skb(E1000_RXBUFFER_2048 + 2, GFP_KERNEL))) {
	1144	+ if (!(skb = alloc_skb(E1000_RXBUFFER_2048 + NET_IP_ALIGN,
	1145	+ GFP_KERNEL))) {
1012	1146	ret_val = 6;
1013	1147	goto err_nomem;
1014	1148	}
1015		- skb_reserve(skb, 2);
	1149	+ skb_reserve(skb, NET_IP_ALIGN);
1016	1150	rxdr->buffer_info[i].skb = skb;
1017	1151	rxdr->buffer_info[i].length = E1000_RXBUFFER_2048;
1018	1152	rxdr->buffer_info[i].dma =

		@@ -1116,15 +1250,15 @@ e1000_nonintegrated_phy_loopback(struct e1000_adapter *adapter)
1116	1250
1117	1251	/* Check Phy Configuration */
1118	1252	e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_reg);
1119		- if(phy_reg != 0x4100)
	1253	+ if (phy_reg != 0x4100)
1120	1254	return 9;
1121	1255
1122	1256	e1000_read_phy_reg(&adapter->hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_reg);
1123		- if(phy_reg != 0x0070)
	1257	+ if (phy_reg != 0x0070)
1124	1258	return 10;
1125	1259
1126	1260	e1000_read_phy_reg(&adapter->hw, 29, &phy_reg);
1127		- if(phy_reg != 0x001A)
	1261	+ if (phy_reg != 0x001A)
1128	1262	return 11;
1129	1263
1130	1264	return 0;

		@@ -1138,7 +1272,7 @@ e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
1138	1272
1139	1273	adapter->hw.autoneg = FALSE;
1140	1274
1141		- if(adapter->hw.phy_type == e1000_phy_m88) {
	1275	+ if (adapter->hw.phy_type == e1000_phy_m88) {
1142	1276	/* Auto-MDI/MDIX Off */
1143	1277	e1000_write_phy_reg(&adapter->hw,
1144	1278	M88E1000_PHY_SPEC_CTRL, 0x0808);

		@@ -1146,26 +1280,44 @@ e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
1146	1280	e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x9140);
1147	1281	/* autoneg off */
1148	1282	e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x8140);
1149		- }
1150		- /* force 1000, set loopback */
1151		- e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x4140);
	1283	+ } else if (adapter->hw.phy_type == e1000_phy_gg82563)
	1284	+ e1000_write_phy_reg(&adapter->hw,
	1285	+ GG82563_PHY_KMRN_MODE_CTRL,
	1286	+ 0x1CC);
1152	1287
1153		- /* Now set up the MAC to the same speed/duplex as the PHY. */
1154	1288	ctrl_reg = E1000_READ_REG(&adapter->hw, CTRL);
1155		- ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1156		- ctrl_reg \|= (E1000_CTRL_FRCSPD \| /* Set the Force Speed Bit */
1157		- E1000_CTRL_FRCDPX \| /* Set the Force Duplex Bit */
1158		- E1000_CTRL_SPD_1000 \|/* Force Speed to 1000 */
1159		- E1000_CTRL_FD); /* Force Duplex to FULL */
1160		-
1161		- if(adapter->hw.media_type == e1000_media_type_copper &&
1162		- adapter->hw.phy_type == e1000_phy_m88) {
1163		- ctrl_reg \|= E1000_CTRL_ILOS; /* Invert Loss of Signal */
	1289	+
	1290	+ if (adapter->hw.phy_type == e1000_phy_ife) {
	1291	+ /* force 100, set loopback */
	1292	+ e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x6100);
	1293	+
	1294	+ /* Now set up the MAC to the same speed/duplex as the PHY. */
	1295	+ ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
	1296	+ ctrl_reg \|= (E1000_CTRL_FRCSPD \| /* Set the Force Speed Bit */
	1297	+ E1000_CTRL_FRCDPX \| /* Set the Force Duplex Bit */
	1298	+ E1000_CTRL_SPD_100 \|/* Force Speed to 100 */
	1299	+ E1000_CTRL_FD); /* Force Duplex to FULL */
1164	1300	} else {
	1301	+ /* force 1000, set loopback */
	1302	+ e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x4140);
	1303	+
	1304	+ /* Now set up the MAC to the same speed/duplex as the PHY. */
	1305	+ ctrl_reg = E1000_READ_REG(&adapter->hw, CTRL);
	1306	+ ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
	1307	+ ctrl_reg \|= (E1000_CTRL_FRCSPD \| /* Set the Force Speed Bit */
	1308	+ E1000_CTRL_FRCDPX \| /* Set the Force Duplex Bit */
	1309	+ E1000_CTRL_SPD_1000 \|/* Force Speed to 1000 */
	1310	+ E1000_CTRL_FD); /* Force Duplex to FULL */
	1311	+ }
	1312	+
	1313	+ if (adapter->hw.media_type == e1000_media_type_copper &&
	1314	+ adapter->hw.phy_type == e1000_phy_m88)
	1315	+ ctrl_reg \|= E1000_CTRL_ILOS; /* Invert Loss of Signal */
	1316	+ else {
1165	1317	/* Set the ILOS bit on the fiber Nic is half
1166	1318	* duplex link is detected. */
1167	1319	stat_reg = E1000_READ_REG(&adapter->hw, STATUS);
1168		- if((stat_reg & E1000_STATUS_FD) == 0)
	1320	+ if ((stat_reg & E1000_STATUS_FD) == 0)
1169	1321	ctrl_reg \|= (E1000_CTRL_ILOS \| E1000_CTRL_SLU);
1170	1322	}
1171	1323

		@@ -1174,7 +1326,7 @@ e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
1174	1326	/* Disable the receiver on the PHY so when a cable is plugged in, the
1175	1327	* PHY does not begin to autoneg when a cable is reconnected to the NIC.
1176	1328	*/
1177		- if(adapter->hw.phy_type == e1000_phy_m88)
	1329	+ if (adapter->hw.phy_type == e1000_phy_m88)
1178	1330	e1000_phy_disable_receiver(adapter);
1179	1331
1180	1332	udelay(500);

		@@ -1190,14 +1342,14 @@ e1000_set_phy_loopback(struct e1000_adapter *adapter)
1190	1342
1191	1343	switch (adapter->hw.mac_type) {
1192	1344	case e1000_82543:
1193		- if(adapter->hw.media_type == e1000_media_type_copper) {
	1345	+ if (adapter->hw.media_type == e1000_media_type_copper) {
1194	1346	/* Attempt to setup Loopback mode on Non-integrated PHY.
1195	1347	* Some PHY registers get corrupted at random, so
1196	1348	* attempt this 10 times.
1197	1349	*/
1198		- while(e1000_nonintegrated_phy_loopback(adapter) &&
	1350	+ while (e1000_nonintegrated_phy_loopback(adapter) &&
1199	1351	count++ < 10);
1200		- if(count < 11)
	1352	+ if (count < 11)
1201	1353	return 0;
1202	1354	}
1203	1355	break;

		@@ -1212,6 +1364,11 @@ e1000_set_phy_loopback(struct e1000_adapter *adapter)
1212	1364	case e1000_82541_rev_2:
1213	1365	case e1000_82547:
1214	1366	case e1000_82547_rev_2:
	1367	+ case e1000_82571:
	1368	+ case e1000_82572:
	1369	+ case e1000_82573:
	1370	+ case e1000_80003es2lan:
	1371	+ case e1000_ich8lan:
1215	1372	return e1000_integrated_phy_loopback(adapter);
1216	1373	break;
1217	1374

		@@ -1232,22 +1389,33 @@ e1000_set_phy_loopback(struct e1000_adapter *adapter)
1232	1389	static int
1233	1390	e1000_setup_loopback_test(struct e1000_adapter *adapter)
1234	1391	{
	1392	+ struct e1000_hw *hw = &adapter->hw;
1235	1393	uint32_t rctl;
1236	1394
1237		- if(adapter->hw.media_type == e1000_media_type_fiber \|\|
1238		- adapter->hw.media_type == e1000_media_type_internal_serdes) {
1239		- if(adapter->hw.mac_type == e1000_82545 \|\|
1240		- adapter->hw.mac_type == e1000_82546 \|\|
1241		- adapter->hw.mac_type == e1000_82545_rev_3 \|\|
1242		- adapter->hw.mac_type == e1000_82546_rev_3)
	1395	+ if (hw->media_type == e1000_media_type_fiber \|\|
	1396	+ hw->media_type == e1000_media_type_internal_serdes) {
	1397	+ switch (hw->mac_type) {
	1398	+ case e1000_82545:
	1399	+ case e1000_82546:
	1400	+ case e1000_82545_rev_3:
	1401	+ case e1000_82546_rev_3:
1243	1402	return e1000_set_phy_loopback(adapter);
1244		- else {
1245		- rctl = E1000_READ_REG(&adapter->hw, RCTL);
	1403	+ break;
	1404	+ case e1000_82571:
	1405	+ case e1000_82572:
	1406	+#define E1000_SERDES_LB_ON 0x410
	1407	+ e1000_set_phy_loopback(adapter);
	1408	+ E1000_WRITE_REG(hw, SCTL, E1000_SERDES_LB_ON);
	1409	+ msleep(10);
	1410	+ return 0;
	1411	+ break;
	1412	+ default:
	1413	+ rctl = E1000_READ_REG(hw, RCTL);
1246	1414	rctl \|= E1000_RCTL_LBM_TCVR;
1247		- E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
	1415	+ E1000_WRITE_REG(hw, RCTL, rctl);
1248	1416	return 0;
1249	1417	}
1250		- } else if(adapter->hw.media_type == e1000_media_type_copper)
	1418	+ } else if (hw->media_type == e1000_media_type_copper)
1251	1419	return e1000_set_phy_loopback(adapter);
1252	1420
1253	1421	return 7;

		@@ -1256,27 +1424,42 @@ e1000_setup_loopback_test(struct e1000_adapter *adapter)
1256	1424	static void
1257	1425	e1000_loopback_cleanup(struct e1000_adapter *adapter)
1258	1426	{
	1427	+ struct e1000_hw *hw = &adapter->hw;
1259	1428	uint32_t rctl;
1260	1429	uint16_t phy_reg;
1261	1430
1262		- rctl = E1000_READ_REG(&adapter->hw, RCTL);
	1431	+ rctl = E1000_READ_REG(hw, RCTL);
1263	1432	rctl &= ~(E1000_RCTL_LBM_TCVR \| E1000_RCTL_LBM_MAC);
1264		- E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1265		-
1266		- if(adapter->hw.media_type == e1000_media_type_copper \|\|
1267		- ((adapter->hw.media_type == e1000_media_type_fiber \|\|
1268		- adapter->hw.media_type == e1000_media_type_internal_serdes) &&
1269		- (adapter->hw.mac_type == e1000_82545 \|\|
1270		- adapter->hw.mac_type == e1000_82546 \|\|
1271		- adapter->hw.mac_type == e1000_82545_rev_3 \|\|
1272		- adapter->hw.mac_type == e1000_82546_rev_3))) {
1273		- adapter->hw.autoneg = TRUE;
1274		- e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_reg);
1275		- if(phy_reg & MII_CR_LOOPBACK) {
	1433	+ E1000_WRITE_REG(hw, RCTL, rctl);
	1434	+
	1435	+ switch (hw->mac_type) {
	1436	+ case e1000_82571:
	1437	+ case e1000_82572:
	1438	+ if (hw->media_type == e1000_media_type_fiber \|\|
	1439	+ hw->media_type == e1000_media_type_internal_serdes) {
	1440	+#define E1000_SERDES_LB_OFF 0x400
	1441	+ E1000_WRITE_REG(hw, SCTL, E1000_SERDES_LB_OFF);
	1442	+ msleep(10);
	1443	+ break;
	1444	+ }
	1445	+ /* Fall Through */
	1446	+ case e1000_82545:
	1447	+ case e1000_82546:
	1448	+ case e1000_82545_rev_3:
	1449	+ case e1000_82546_rev_3:
	1450	+ default:
	1451	+ hw->autoneg = TRUE;
	1452	+ if (hw->phy_type == e1000_phy_gg82563)
	1453	+ e1000_write_phy_reg(hw,
	1454	+ GG82563_PHY_KMRN_MODE_CTRL,
	1455	+ 0x180);
	1456	+ e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg);
	1457	+ if (phy_reg & MII_CR_LOOPBACK) {
1276	1458	phy_reg &= ~MII_CR_LOOPBACK;
1277		- e1000_write_phy_reg(&adapter->hw, PHY_CTRL, phy_reg);
1278		- e1000_phy_reset(&adapter->hw);
	1459	+ e1000_write_phy_reg(hw, PHY_CTRL, phy_reg);
	1460	+ e1000_phy_reset(hw);
1279	1461	}
	1462	+ break;
1280	1463	}
1281	1464	}
1282	1465

		@@ -1284,7 +1467,7 @@ static void
1284	1467	e1000_create_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
1285	1468	{
1286	1469	memset(skb->data, 0xFF, frame_size);
1287		- frame_size = (frame_size % 2) ? (frame_size - 1) : frame_size;
	1470	+ frame_size &= ~1;
1288	1471	memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1289	1472	memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1290	1473	memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);

		@@ -1293,9 +1476,9 @@ e1000_create_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
1293	1476	static int
1294	1477	e1000_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
1295	1478	{
1296		- frame_size = (frame_size % 2) ? (frame_size - 1) : frame_size;
1297		- if(*(skb->data + 3) == 0xFF) {
1298		- if((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
	1479	+ frame_size &= ~1;
	1480	+ if (*(skb->data + 3) == 0xFF) {
	1481	+ if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1299	1482	(*(skb->data + frame_size / 2 + 12) == 0xAF)) {
1300	1483	return 0;
1301	1484	}

		@@ -1306,46 +1489,90 @@ e1000_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
1306	1489	static int
1307	1490	e1000_run_loopback_test(struct e1000_adapter *adapter)
1308	1491	{
1309		- struct e1000_desc_ring *txdr = &adapter->test_tx_ring;
1310		- struct e1000_desc_ring *rxdr = &adapter->test_rx_ring;
	1492	+ struct e1000_tx_ring *txdr = &adapter->test_tx_ring;
	1493	+ struct e1000_rx_ring *rxdr = &adapter->test_rx_ring;
1311	1494	struct pci_dev *pdev = adapter->pdev;
1312		- int i, ret_val;
	1495	+ int i, j, k, l, lc, good_cnt, ret_val=0;
	1496	+ unsigned long time;
1313	1497
1314	1498	E1000_WRITE_REG(&adapter->hw, RDT, rxdr->count - 1);
1315	1499
1316		- for(i = 0; i < 64; i++) {
1317		- e1000_create_lbtest_frame(txdr->buffer_info[i].skb, 1024);
1318		- pci_dma_sync_single(pdev, txdr->buffer_info[i].dma,
1319		- txdr->buffer_info[i].length,
1320		- PCI_DMA_TODEVICE);
1321		- }
1322		- E1000_WRITE_REG(&adapter->hw, TDT, i);
1323		-
1324		- msec_delay(200);
1325		-
1326		- i = 0;
1327		- do {
1328		- pci_dma_sync_single(pdev, rxdr->buffer_info[i].dma,
1329		- rxdr->buffer_info[i].length,
1330		- PCI_DMA_FROMDEVICE);
1331		-
1332		- ret_val = e1000_check_lbtest_frame(rxdr->buffer_info[i].skb,
1333		- 1024);
1334		- i++;
1335		- } while (ret_val != 0 && i < 64);
	1500	+ /* Calculate the loop count based on the largest descriptor ring
	1501	+ * The idea is to wrap the largest ring a number of times using 64
	1502	+ * send/receive pairs during each loop
	1503	+ */
1336	1504
	1505	+ if (rxdr->count <= txdr->count)
	1506	+ lc = ((txdr->count / 64) * 2) + 1;
	1507	+ else
	1508	+ lc = ((rxdr->count / 64) * 2) + 1;
	1509	+
	1510	+ k = l = 0;
	1511	+ for (j = 0; j <= lc; j++) { /* loop count loop */
	1512	+ for (i = 0; i < 64; i++) { /* send the packets */
	1513	+ e1000_create_lbtest_frame(txdr->buffer_info[i].skb,
	1514	+ 1024);
	1515	+ pci_dma_sync_single_for_device(pdev,
	1516	+ txdr->buffer_info[k].dma,
	1517	+ txdr->buffer_info[k].length,
	1518	+ PCI_DMA_TODEVICE);
	1519	+ if (unlikely(++k == txdr->count)) k = 0;
	1520	+ }
	1521	+ E1000_WRITE_REG(&adapter->hw, TDT, k);
	1522	+ msleep(200);
	1523	+ time = jiffies; /* set the start time for the receive */
	1524	+ good_cnt = 0;
	1525	+ do { /* receive the sent packets */
	1526	+ pci_dma_sync_single_for_cpu(pdev,
	1527	+ rxdr->buffer_info[l].dma,
	1528	+ rxdr->buffer_info[l].length,
	1529	+ PCI_DMA_FROMDEVICE);
	1530	+
	1531	+ ret_val = e1000_check_lbtest_frame(
	1532	+ rxdr->buffer_info[l].skb,
	1533	+ 1024);
	1534	+ if (!ret_val)
	1535	+ good_cnt++;
	1536	+ if (unlikely(++l == rxdr->count)) l = 0;
	1537	+ /* time + 20 msecs (200 msecs on 2.4) is more than
	1538	+ * enough time to complete the receives, if it's
	1539	+ * exceeded, break and error off
	1540	+ */
	1541	+ } while (good_cnt < 64 && jiffies < (time + 20));
	1542	+ if (good_cnt != 64) {
	1543	+ ret_val = 13; /* ret_val is the same as mis-compare */
	1544	+ break;
	1545	+ }
	1546	+ if (jiffies >= (time + 2)) {
	1547	+ ret_val = 14; /* error code for time out error */
	1548	+ break;
	1549	+ }
	1550	+ } /* end loop count loop */
1337	1551	return ret_val;
1338	1552	}
1339	1553
1340	1554	static int
1341	1555	e1000_loopback_test(struct e1000_adapter adapter, uint64_t data)
1342	1556	{
1343		- if((*data = e1000_setup_desc_rings(adapter))) goto err_loopback;
1344		- if((*data = e1000_setup_loopback_test(adapter))) goto err_loopback;
	1557	+ /* PHY loopback cannot be performed if SoL/IDER
	1558	+ * sessions are active */
	1559	+ if (e1000_check_phy_reset_block(&adapter->hw)) {
	1560	+ DPRINTK(DRV, ERR, "Cannot do PHY loopback test "
	1561	+ "when SoL/IDER is active.\n");
	1562	+ *data = 0;
	1563	+ goto out;
	1564	+ }
	1565	+
	1566	+ if ((*data = e1000_setup_desc_rings(adapter)))
	1567	+ goto out;
	1568	+ if ((*data = e1000_setup_loopback_test(adapter)))
	1569	+ goto err_loopback;
1345	1570	*data = e1000_run_loopback_test(adapter);
1346	1571	e1000_loopback_cleanup(adapter);
1347		- e1000_free_desc_rings(adapter);
	1572	+
1348	1573	err_loopback:
	1574	+ e1000_free_desc_rings(adapter);
	1575	+out:
1349	1576	return *data;
1350	1577	}
1351	1578

		@@ -1353,45 +1580,49 @@ static int
1353	1580	e1000_link_test(struct e1000_adapter adapter, uint64_t data)
1354	1581	{
1355	1582	*data = 0;
1356		-
1357	1583	if (adapter->hw.media_type == e1000_media_type_internal_serdes) {
1358	1584	int i = 0;
1359	1585	adapter->hw.serdes_link_down = TRUE;
1360	1586
1361		- /* on some blade server designs link establishment */
1362		- /* could take as long as 2-3 minutes. */
	1587	+ /* On some blade server designs, link establishment
	1588	+ * could take as long as 2-3 minutes */
1363	1589	do {
1364	1590	e1000_check_for_link(&adapter->hw);
1365	1591	if (adapter->hw.serdes_link_down == FALSE)
1366	1592	return *data;
1367		- msec_delay(20);
	1593	+ msleep(20);
1368	1594	} while (i++ < 3750);
1369	1595
1370		- *data = 1;
	1596	+ *data = 1;
1371	1597	} else {
1372	1598	e1000_check_for_link(&adapter->hw);
	1599	+ if (adapter->hw.autoneg) /* if auto_neg is set wait for it */
	1600	+ msleep(4000);
1373	1601
1374		- if(!(E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU)) {
	1602	+ if (!(E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU)) {
1375	1603	*data = 1;
1376	1604	}
1377	1605	}
1378	1606	return *data;
1379	1607	}
1380	1608
1381		-static int
	1609	+static int
1382	1610	e1000_diag_test_count(struct net_device *netdev)
1383	1611	{
1384	1612	return E1000_TEST_LEN;
1385	1613	}
1386	1614
	1615	+extern void e1000_power_up_phy(struct e1000_adapter *);
	1616	+
1387	1617	static void
1388	1618	e1000_diag_test(struct net_device *netdev,
1389	1619	struct ethtool_test eth_test, uint64_t data)
1390	1620	{
1391		- struct e1000_adapter *adapter = netdev->priv;
	1621	+ struct e1000_adapter *adapter = netdev_priv(netdev);
1392	1622	boolean_t if_running = netif_running(netdev);
1393	1623
1394		- if(eth_test->flags == ETH_TEST_FL_OFFLINE) {
	1624	+ set_bit(__E1000_TESTING, &adapter->flags);
	1625	+ if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1395	1626	/* Offline tests */
1396	1627
1397	1628	/* save speed, duplex, autoneg settings */

		@@ -1399,29 +1630,34 @@ e1000_diag_test(struct net_device *netdev,
1399	1630	uint8_t forced_speed_duplex = adapter->hw.forced_speed_duplex;
1400	1631	uint8_t autoneg = adapter->hw.autoneg;
1401	1632
	1633	+ DPRINTK(HW, INFO, "offline testing starting\n");
	1634	+
1402	1635	/* Link test performed before hardware reset so autoneg doesn't
1403	1636	* interfere with test result */
1404		- if(e1000_link_test(adapter, &data[4]))
	1637	+ if (e1000_link_test(adapter, &data[4]))
1405	1638	eth_test->flags \|= ETH_TEST_FL_FAILED;
1406	1639
1407		- if(if_running)
1408		- e1000_down(adapter);
	1640	+ if (if_running)
	1641	+ /* indicate we're in test mode */
	1642	+ dev_close(netdev);
1409	1643	else
1410	1644	e1000_reset(adapter);
1411	1645
1412		- if(e1000_reg_test(adapter, &data[0]))
	1646	+ if (e1000_reg_test(adapter, &data[0]))
1413	1647	eth_test->flags \|= ETH_TEST_FL_FAILED;
1414	1648
1415	1649	e1000_reset(adapter);
1416		- if(e1000_eeprom_test(adapter, &data[1]))
	1650	+ if (e1000_eeprom_test(adapter, &data[1]))
1417	1651	eth_test->flags \|= ETH_TEST_FL_FAILED;
1418	1652
1419	1653	e1000_reset(adapter);
1420		- if(e1000_intr_test(adapter, &data[2]))
	1654	+ if (e1000_intr_test(adapter, &data[2]))
1421	1655	eth_test->flags \|= ETH_TEST_FL_FAILED;
1422	1656
1423	1657	e1000_reset(adapter);
1424		- if(e1000_loopback_test(adapter, &data[3]))
	1658	+ /* make sure the phy is powered up */
	1659	+ e1000_power_up_phy(adapter);
	1660	+ if (e1000_loopback_test(adapter, &data[3]))
1425	1661	eth_test->flags \|= ETH_TEST_FL_FAILED;
1426	1662
1427	1663	/* restore speed, duplex, autoneg settings */

		@@ -1430,28 +1666,32 @@ e1000_diag_test(struct net_device *netdev,
1430	1666	adapter->hw.autoneg = autoneg;
1431	1667
1432	1668	e1000_reset(adapter);
1433		- if(if_running)
1434		- e1000_up(adapter);
	1669	+ clear_bit(__E1000_TESTING, &adapter->flags);
	1670	+ if (if_running)
	1671	+ dev_open(netdev);
1435	1672	} else {
	1673	+ DPRINTK(HW, INFO, "online testing starting\n");
1436	1674	/* Online tests */
1437		- if(e1000_link_test(adapter, &data[4]))
	1675	+ if (e1000_link_test(adapter, &data[4]))
1438	1676	eth_test->flags \|= ETH_TEST_FL_FAILED;
1439	1677
1440		- /* Offline tests aren't run; pass by default */
	1678	+ /* Online tests aren't run; pass by default */
1441	1679	data[0] = 0;
1442	1680	data[1] = 0;
1443	1681	data[2] = 0;
1444	1682	data[3] = 0;
	1683	+
	1684	+ clear_bit(__E1000_TESTING, &adapter->flags);
1445	1685	}
	1686	+ msleep_interruptible(4 * 1000);
1446	1687	}
1447	1688
1448		-static void
1449		-e1000_get_wol(struct net_device netdev, struct ethtool_wolinfo wol)
	1689	+static int e1000_wol_exclusion(struct e1000_adapter adapter, struct ethtool_wolinfo wol)
1450	1690	{
1451		- struct e1000_adapter *adapter = netdev->priv;
1452	1691	struct e1000_hw *hw = &adapter->hw;
	1692	+ int retval = 1; /* fail by default */
1453	1693
1454		- switch(adapter->hw.device_id) {
	1694	+ switch (hw->device_id) {
1455	1695	case E1000_DEV_ID_82542:
1456	1696	case E1000_DEV_ID_82543GC_FIBER:
1457	1697	case E1000_DEV_ID_82543GC_COPPER:

		@@ -1459,75 +1699,126 @@ e1000_get_wol(struct net_device netdev, struct ethtool_wolinfo wol)
1459	1699	case E1000_DEV_ID_82546EB_QUAD_COPPER:
1460	1700	case E1000_DEV_ID_82545EM_FIBER:
1461	1701	case E1000_DEV_ID_82545EM_COPPER:
	1702	+ case E1000_DEV_ID_82546GB_QUAD_COPPER:
	1703	+ case E1000_DEV_ID_82546GB_PCIE:
	1704	+ /* these don't support WoL at all */
1462	1705	wol->supported = 0;
1463		- wol->wolopts = 0;
1464		- return;
1465		-
	1706	+ break;
1466	1707	case E1000_DEV_ID_82546EB_FIBER:
1467	1708	case E1000_DEV_ID_82546GB_FIBER:
1468		- /* Wake events only supported on port A for dual fiber */
1469		- if(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) {
	1709	+ case E1000_DEV_ID_82571EB_FIBER:
	1710	+ case E1000_DEV_ID_82571EB_SERDES:
	1711	+ case E1000_DEV_ID_82571EB_COPPER:
	1712	+ /* Wake events not supported on port B */
	1713	+ if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) {
	1714	+ wol->supported = 0;
	1715	+ break;
	1716	+ }
	1717	+ /* return success for non excluded adapter ports */
	1718	+ retval = 0;
	1719	+ break;
	1720	+ case E1000_DEV_ID_82571EB_QUAD_COPPER:
	1721	+ case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
	1722	+ case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
	1723	+ /* quad port adapters only support WoL on port A */
	1724	+ if (!adapter->quad_port_a) {
1470	1725	wol->supported = 0;
1471		- wol->wolopts = 0;
1472		- return;
	1726	+ break;
1473	1727	}
1474		- /* Fall Through */
1475		-
	1728	+ /* return success for non excluded adapter ports */
	1729	+ retval = 0;
	1730	+ break;
1476	1731	default:
1477		- wol->supported = WAKE_UCAST \| WAKE_MCAST \|
1478		- WAKE_BCAST \| WAKE_MAGIC;
1479		-
1480		- wol->wolopts = 0;
1481		- if(adapter->wol & E1000_WUFC_EX)
1482		- wol->wolopts \|= WAKE_UCAST;
1483		- if(adapter->wol & E1000_WUFC_MC)
1484		- wol->wolopts \|= WAKE_MCAST;
1485		- if(adapter->wol & E1000_WUFC_BC)
1486		- wol->wolopts \|= WAKE_BCAST;
1487		- if(adapter->wol & E1000_WUFC_MAG)
1488		- wol->wolopts \|= WAKE_MAGIC;
	1732	+ /* dual port cards only support WoL on port A from now on
	1733	+ * unless it was enabled in the eeprom for port B
	1734	+ * so exclude FUNC_1 ports from having WoL enabled */
	1735	+ if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1 &&
	1736	+ !adapter->eeprom_wol) {
	1737	+ wol->supported = 0;
	1738	+ break;
	1739	+ }
	1740	+
	1741	+ retval = 0;
	1742	+ }
	1743	+
	1744	+ return retval;
	1745	+}
	1746	+
	1747	+static void
	1748	+e1000_get_wol(struct net_device netdev, struct ethtool_wolinfo wol)
	1749	+{
	1750	+ struct e1000_adapter *adapter = netdev_priv(netdev);
	1751	+
	1752	+ wol->supported = WAKE_UCAST \| WAKE_MCAST \|
	1753	+ WAKE_BCAST \| WAKE_MAGIC;
	1754	+ wol->wolopts = 0;
	1755	+
	1756	+ /* this function will set ->supported = 0 and return 1 if wol is not
	1757	+ * supported by this hardware */
	1758	+ if (e1000_wol_exclusion(adapter, wol))
1489	1759	return;
	1760	+
	1761	+ /* apply any specific unsupported masks here */
	1762	+ switch (adapter->hw.device_id) {
	1763	+ case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
	1764	+ /* KSP3 does not suppport UCAST wake-ups */
	1765	+ wol->supported &= ~WAKE_UCAST;
	1766	+
	1767	+ if (adapter->wol & E1000_WUFC_EX)
	1768	+ DPRINTK(DRV, ERR, "Interface does not support "
	1769	+ "directed (unicast) frame wake-up packets\n");
	1770	+ break;
	1771	+ default:
	1772	+ break;
1490	1773	}
	1774	+
	1775	+ if (adapter->wol & E1000_WUFC_EX)
	1776	+ wol->wolopts \|= WAKE_UCAST;
	1777	+ if (adapter->wol & E1000_WUFC_MC)
	1778	+ wol->wolopts \|= WAKE_MCAST;
	1779	+ if (adapter->wol & E1000_WUFC_BC)
	1780	+ wol->wolopts \|= WAKE_BCAST;
	1781	+ if (adapter->wol & E1000_WUFC_MAG)
	1782	+ wol->wolopts \|= WAKE_MAGIC;
	1783	+
	1784	+ return;
1491	1785	}
1492	1786
1493	1787	static int
1494	1788	e1000_set_wol(struct net_device netdev, struct ethtool_wolinfo wol)
1495	1789	{
1496		- struct e1000_adapter *adapter = netdev->priv;
	1790	+ struct e1000_adapter *adapter = netdev_priv(netdev);
1497	1791	struct e1000_hw *hw = &adapter->hw;
1498	1792
1499		- switch(adapter->hw.device_id) {
1500		- case E1000_DEV_ID_82542:
1501		- case E1000_DEV_ID_82543GC_FIBER:
1502		- case E1000_DEV_ID_82543GC_COPPER:
1503		- case E1000_DEV_ID_82544EI_FIBER:
1504		- case E1000_DEV_ID_82546EB_QUAD_COPPER:
1505		- case E1000_DEV_ID_82545EM_FIBER:
1506		- case E1000_DEV_ID_82545EM_COPPER:
1507		- return wol->wolopts ? -EOPNOTSUPP : 0;
	1793	+ if (wol->wolopts & (WAKE_PHY \| WAKE_ARP \| WAKE_MAGICSECURE))
	1794	+ return -EOPNOTSUPP;
1508	1795
1509		- case E1000_DEV_ID_82546EB_FIBER:
1510		- case E1000_DEV_ID_82546GB_FIBER:
1511		- /* Wake events only supported on port A for dual fiber */
1512		- if(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
1513		- return wol->wolopts ? -EOPNOTSUPP : 0;
1514		- /* Fall Through */
	1796	+ if (e1000_wol_exclusion(adapter, wol))
	1797	+ return wol->wolopts ? -EOPNOTSUPP : 0;
1515	1798
1516		- default:
1517		- if(wol->wolopts & (WAKE_PHY \| WAKE_ARP \| WAKE_MAGICSECURE))
	1799	+ switch (hw->device_id) {
	1800	+ case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
	1801	+ if (wol->wolopts & WAKE_UCAST) {
	1802	+ DPRINTK(DRV, ERR, "Interface does not support "
	1803	+ "directed (unicast) frame wake-up packets\n");
1518	1804	return -EOPNOTSUPP;
	1805	+ }
	1806	+ break;
	1807	+ default:
	1808	+ break;
	1809	+ }
1519	1810
1520		- adapter->wol = 0;
	1811	+ /* these settings will always override what we currently have */
	1812	+ adapter->wol = 0;
1521	1813
1522		- if(wol->wolopts & WAKE_UCAST)
1523		- adapter->wol \|= E1000_WUFC_EX;
1524		- if(wol->wolopts & WAKE_MCAST)
1525		- adapter->wol \|= E1000_WUFC_MC;
1526		- if(wol->wolopts & WAKE_BCAST)
1527		- adapter->wol \|= E1000_WUFC_BC;
1528		- if(wol->wolopts & WAKE_MAGIC)
1529		- adapter->wol \|= E1000_WUFC_MAG;
1530		- }
	1814	+ if (wol->wolopts & WAKE_UCAST)
	1815	+ adapter->wol \|= E1000_WUFC_EX;
	1816	+ if (wol->wolopts & WAKE_MCAST)
	1817	+ adapter->wol \|= E1000_WUFC_MC;
	1818	+ if (wol->wolopts & WAKE_BCAST)
	1819	+ adapter->wol \|= E1000_WUFC_BC;
	1820	+ if (wol->wolopts & WAKE_MAGIC)
	1821	+ adapter->wol \|= E1000_WUFC_MAG;
1531	1822
1532	1823	return 0;
1533	1824	}

		@@ -1543,7 +1834,7 @@ e1000_led_blink_callback(unsigned long data)
1543	1834	{
1544	1835	struct e1000_adapter adapter = (struct e1000_adapter ) data;
1545	1836
1546		- if(test_and_change_bit(E1000_LED_ON, &adapter->led_status))
	1837	+ if (test_and_change_bit(E1000_LED_ON, &adapter->led_status))
1547	1838	e1000_led_off(&adapter->hw);
1548	1839	else
1549	1840	e1000_led_on(&adapter->hw);

		@@ -1554,24 +1845,36 @@ e1000_led_blink_callback(unsigned long data)
1554	1845	static int
1555	1846	e1000_phys_id(struct net_device *netdev, uint32_t data)
1556	1847	{
1557		- struct e1000_adapter *adapter = netdev->priv;
	1848	+ struct e1000_adapter *adapter = netdev_priv(netdev);
1558	1849
1559		- if(!data \|\| data > (uint32_t)(MAX_SCHEDULE_TIMEOUT / HZ))
	1850	+ if (!data \|\| data > (uint32_t)(MAX_SCHEDULE_TIMEOUT / HZ))
1560	1851	data = (uint32_t)(MAX_SCHEDULE_TIMEOUT / HZ);
1561	1852
1562		- if(!adapter->blink_timer.function) {
1563		- init_timer(&adapter->blink_timer);
1564		- adapter->blink_timer.function = e1000_led_blink_callback;
1565		- adapter->blink_timer.data = (unsigned long) adapter;
	1853	+ if (adapter->hw.mac_type < e1000_82571) {
	1854	+ if (!adapter->blink_timer.function) {
	1855	+ init_timer(&adapter->blink_timer);
	1856	+ adapter->blink_timer.function = e1000_led_blink_callback;
	1857	+ adapter->blink_timer.data = (unsigned long) adapter;
	1858	+ }
	1859	+ e1000_setup_led(&adapter->hw);
	1860	+ mod_timer(&adapter->blink_timer, jiffies);
	1861	+ msleep_interruptible(data * 1000);
	1862	+ del_timer_sync(&adapter->blink_timer);
	1863	+ } else if (adapter->hw.phy_type == e1000_phy_ife) {
	1864	+ if (!adapter->blink_timer.function) {
	1865	+ init_timer(&adapter->blink_timer);
	1866	+ adapter->blink_timer.function = e1000_led_blink_callback;
	1867	+ adapter->blink_timer.data = (unsigned long) adapter;
	1868	+ }
	1869	+ mod_timer(&adapter->blink_timer, jiffies);
	1870	+ msleep_interruptible(data * 1000);
	1871	+ del_timer_sync(&adapter->blink_timer);
	1872	+ e1000_write_phy_reg(&(adapter->hw), IFE_PHY_SPECIAL_CONTROL_LED, 0);
	1873	+ } else {
	1874	+ e1000_blink_led_start(&adapter->hw);
	1875	+ msleep_interruptible(data * 1000);
1566	1876	}
1567	1877
1568		- e1000_setup_led(&adapter->hw);
1569		- mod_timer(&adapter->blink_timer, jiffies);
1570		-
1571		- set_current_state(TASK_INTERRUPTIBLE);
1572		-
1573		- schedule_timeout(data * HZ);
1574		- del_timer_sync(&adapter->blink_timer);
1575	1878	e1000_led_off(&adapter->hw);
1576	1879	clear_bit(E1000_LED_ON, &adapter->led_status);
1577	1880	e1000_cleanup_led(&adapter->hw);

		@@ -1582,56 +1885,57 @@ e1000_phys_id(struct net_device *netdev, uint32_t data)
1582	1885	static int
1583	1886	e1000_nway_reset(struct net_device *netdev)
1584	1887	{
1585		- struct e1000_adapter *adapter = netdev->priv;
1586		- if(netif_running(netdev)) {
1587		- e1000_down(adapter);
1588		- e1000_up(adapter);
1589		- }
	1888	+ struct e1000_adapter *adapter = netdev_priv(netdev);
	1889	+ if (netif_running(netdev))
	1890	+ e1000_reinit_locked(adapter);
1590	1891	return 0;
1591	1892	}
1592	1893
1593		-static int
	1894	+static int
1594	1895	e1000_get_stats_count(struct net_device *netdev)
1595	1896	{
1596	1897	return E1000_STATS_LEN;
1597	1898	}
1598	1899
1599		-static void
1600		-e1000_get_ethtool_stats(struct net_device *netdev,
	1900	+static void
	1901	+e1000_get_ethtool_stats(struct net_device *netdev,
1601	1902	struct ethtool_stats stats, uint64_t data)
1602	1903	{
1603		- struct e1000_adapter *adapter = netdev->priv;
	1904	+ struct e1000_adapter *adapter = netdev_priv(netdev);
1604	1905	int i;
1605	1906
1606	1907	e1000_update_stats(adapter);
1607		- for(i = 0; i < E1000_STATS_LEN; i++) {
1608		- char p = (char )adapter+e1000_gstrings_stats[i].stat_offset;
1609		- data[i] = (e1000_gstrings_stats[i].sizeof_stat ==
	1908	+ for (i = 0; i < E1000_GLOBAL_STATS_LEN; i++) {
	1909	+ char p = (char )adapter+e1000_gstrings_stats[i].stat_offset;
	1910	+ data[i] = (e1000_gstrings_stats[i].sizeof_stat ==
1610	1911	sizeof(uint64_t)) ? (uint64_t )p : (uint32_t )p;
1611	1912	}
	1913	+/* BUG_ON(i != E1000_STATS_LEN); */
1612	1914	}
1613	1915
1614		-static void
	1916	+static void
1615	1917	e1000_get_strings(struct net_device netdev, uint32_t stringset, uint8_t data)
1616	1918	{
	1919	+ uint8_t *p = data;
1617	1920	int i;
1618	1921
1619		- switch(stringset) {
	1922	+ switch (stringset) {
1620	1923	case ETH_SS_TEST:
1621		- memcpy(data, *e1000_gstrings_test,
	1924	+ memcpy(data, *e1000_gstrings_test,
1622	1925	E1000_TEST_LEN*ETH_GSTRING_LEN);
1623	1926	break;
1624	1927	case ETH_SS_STATS:
1625		- for (i=0; i < E1000_STATS_LEN; i++) {
1626		- memcpy(data + i * ETH_GSTRING_LEN,
1627		- e1000_gstrings_stats[i].stat_string,
1628		- ETH_GSTRING_LEN);
	1928	+ for (i = 0; i < E1000_GLOBAL_STATS_LEN; i++) {
	1929	+ memcpy(p, e1000_gstrings_stats[i].stat_string,
	1930	+ ETH_GSTRING_LEN);
	1931	+ p += ETH_GSTRING_LEN;
1629	1932	}
	1933	+/* BUG_ON(p - data != E1000_STATS_LEN * ETH_GSTRING_LEN); */
1630	1934	break;
1631	1935	}
1632	1936	}
1633	1937
1634		-struct ethtool_ops e1000_ethtool_ops = {
	1938	+static struct ethtool_ops e1000_ethtool_ops = {
1635	1939	.get_settings = e1000_get_settings,
1636	1940	.set_settings = e1000_set_settings,
1637	1941	.get_drvinfo = e1000_get_drvinfo,

		@@ -1639,8 +1943,8 @@ struct ethtool_ops e1000_ethtool_ops = {
1639	1943	.get_regs = e1000_get_regs,
1640	1944	.get_wol = e1000_get_wol,
1641	1945	.set_wol = e1000_set_wol,
1642		- .get_msglevel = e1000_get_msglevel,
1643		- .set_msglevel = e1000_set_msglevel,
	1946	+ .get_msglevel = e1000_get_msglevel,
	1947	+ .set_msglevel = e1000_set_msglevel,
1644	1948	.nway_reset = e1000_nway_reset,
1645	1949	.get_link = ethtool_op_get_link,
1646	1950	.get_eeprom_len = e1000_get_eeprom_len,

		@@ -1648,27 +1952,27 @@ struct ethtool_ops e1000_ethtool_ops = {
1648	1952	.set_eeprom = e1000_set_eeprom,
1649	1953	.get_ringparam = e1000_get_ringparam,
1650	1954	.set_ringparam = e1000_set_ringparam,
1651		- .get_pauseparam = e1000_get_pauseparam,
1652		- .set_pauseparam = e1000_set_pauseparam,
1653		- .get_rx_csum = e1000_get_rx_csum,
1654		- .set_rx_csum = e1000_set_rx_csum,
1655		- .get_tx_csum = e1000_get_tx_csum,
1656		- .set_tx_csum = e1000_set_tx_csum,
1657		- .get_sg = ethtool_op_get_sg,
1658		- .set_sg = ethtool_op_set_sg,
1659		-#ifdef NETIF_F_TSO
1660		- .get_tso = ethtool_op_get_tso,
1661		- .set_tso = e1000_set_tso,
1662		-#endif
	1955	+ .get_pauseparam = e1000_get_pauseparam,
	1956	+ .set_pauseparam = e1000_set_pauseparam,
	1957	+ .get_rx_csum = e1000_get_rx_csum,
	1958	+ .set_rx_csum = e1000_set_rx_csum,
	1959	+ .get_tx_csum = e1000_get_tx_csum,
	1960	+ .set_tx_csum = e1000_set_tx_csum,
	1961	+ .get_sg = ethtool_op_get_sg,
	1962	+ .set_sg = ethtool_op_set_sg,
1663	1963	.self_test_count = e1000_diag_test_count,
1664	1964	.self_test = e1000_diag_test,
1665	1965	.get_strings = e1000_get_strings,
1666	1966	.phys_id = e1000_phys_id,
1667	1967	.get_stats_count = e1000_get_stats_count,
1668	1968	.get_ethtool_stats = e1000_get_ethtool_stats,
	1969	+#ifdef ETHTOOL_GPERMADDR
	1970	+ .get_perm_addr = ethtool_op_get_perm_addr,
	1971	+#endif
1669	1972	};
1670	1973
1671		-void set_ethtool_ops(struct net_device *netdev)
	1974	+void e1000_set_ethtool_ops(struct net_device *netdev)
1672	1975	{
1673	1976	SET_ETHTOOL_OPS(netdev, &e1000_ethtool_ops);
1674	1977	}
	1978	+#endif /* SIOCETHTOOL */

--- a/drivers/net/e1000/e1000_hw.c

+++ b/drivers/net/e1000/e1000_hw.c

		@@ -1,27 +1,27 @@
1	1	/*******************************************************************************
2	2
3		-
4		- Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
5		-
6		- This program is free software; you can redistribute it and/or modify it
7		- under the terms of the GNU General Public License as published by the Free
8		- Software Foundation; either version 2 of the License, or (at your option)
9		- any later version.
10		-
11		- This program is distributed in the hope that it will be useful, but WITHOUT
12		- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13		- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	3	+ Intel PRO/1000 Linux driver
	4	+ Copyright(c) 1999 - 2006 Intel Corporation.
	5	+
	6	+ This program is free software; you can redistribute it and/or modify it
	7	+ under the terms and conditions of the GNU General Public License,
	8	+ version 2, as published by the Free Software Foundation.
	9	+
	10	+ This program is distributed in the hope it will be useful, but WITHOUT
	11	+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14	13	more details.
15		-
	14	+
16	15	You should have received a copy of the GNU General Public License along with
17		- this program; if not, write to the Free Software Foundation, Inc., 59
18		- Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19		-
20		- The full GNU General Public License is included in this distribution in the
21		- file called LICENSE.
22		-
	16	+ this program; if not, write to the Free Software Foundation, Inc.,
	17	+ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18	+
	19	+ The full GNU General Public License is included in this distribution in
	20	+ the file called "COPYING".
	21	+
23	22	Contact Information:
24	23	Linux NICS <linux.nics@intel.com>
	24	+ e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25	25	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26	26
27	27	*******************************************************************************/

		@@ -30,8 +30,66 @@
30	30	* Shared functions for accessing and configuring the MAC
31	31	*/
32	32
	33	+
	34	+
33	35	#include "e1000_hw.h"
34	36
	37	+static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
	38	+static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
	39	+static int32_t e1000_read_kmrn_reg(struct e1000_hw hw, uint32_t reg_addr, uint16_t data);
	40	+static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
	41	+static int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
	42	+static void e1000_release_software_semaphore(struct e1000_hw *hw);
	43	+
	44	+static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw);
	45	+static int32_t e1000_check_downshift(struct e1000_hw *hw);
	46	+static int32_t e1000_check_polarity(struct e1000_hw hw, e1000_rev_polarity polarity);
	47	+static void e1000_clear_vfta(struct e1000_hw *hw);
	48	+static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw);
	49	+static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up);
	50	+static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
	51	+static int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
	52	+static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank);
	53	+static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw);
	54	+static int32_t e1000_get_cable_length(struct e1000_hw hw, uint16_t min_length, uint16_t *max_length);
	55	+static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
	56	+static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw);
	57	+static int32_t e1000_get_software_flag(struct e1000_hw *hw);
	58	+static int32_t e1000_ich8_cycle_init(struct e1000_hw *hw);
	59	+static int32_t e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout);
	60	+static int32_t e1000_id_led_init(struct e1000_hw *hw);
	61	+static int32_t e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size);
	62	+static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw);
	63	+static void e1000_init_rx_addrs(struct e1000_hw *hw);
	64	+static void e1000_initialize_hardware_bits(struct e1000_hw *hw);
	65	+static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
	66	+static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
	67	+static int32_t e1000_mng_enable_host_if(struct e1000_hw *hw);
	68	+static int32_t e1000_mng_host_if_write(struct e1000_hw hw, uint8_t buffer, uint16_t length, uint16_t offset, uint8_t *sum);
	69	+static int32_t e1000_mng_write_cmd_header(struct e1000_hw* hw, struct e1000_host_mng_command_header* hdr);
	70	+static int32_t e1000_mng_write_commit(struct e1000_hw *hw);
	71	+static int32_t e1000_phy_ife_get_info(struct e1000_hw hw, struct e1000_phy_info phy_info);
	72	+static int32_t e1000_phy_igp_get_info(struct e1000_hw hw, struct e1000_phy_info phy_info);
	73	+static int32_t e1000_read_eeprom_eerd(struct e1000_hw hw, uint16_t offset, uint16_t words, uint16_t data);
	74	+static int32_t e1000_write_eeprom_eewr(struct e1000_hw hw, uint16_t offset, uint16_t words, uint16_t data);
	75	+static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
	76	+static int32_t e1000_phy_m88_get_info(struct e1000_hw hw, struct e1000_phy_info phy_info);
	77	+static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
	78	+static int32_t e1000_read_ich8_byte(struct e1000_hw hw, uint32_t index, uint8_t data);
	79	+static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte);
	80	+static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte);
	81	+static int32_t e1000_read_ich8_word(struct e1000_hw hw, uint32_t index, uint16_t data);
	82	+static int32_t e1000_read_ich8_data(struct e1000_hw hw, uint32_t index, uint32_t size, uint16_t data);
	83	+static int32_t e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t data);
	84	+static int32_t e1000_read_eeprom_ich8(struct e1000_hw hw, uint16_t offset, uint16_t words, uint16_t data);
	85	+static int32_t e1000_write_eeprom_ich8(struct e1000_hw hw, uint16_t offset, uint16_t words, uint16_t data);
	86	+static void e1000_release_software_flag(struct e1000_hw *hw);
	87	+static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
	88	+static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active);
	89	+static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop);
	90	+static void e1000_set_pci_express_master_disable(struct e1000_hw *hw);
	91	+static int32_t e1000_wait_autoneg(struct e1000_hw *hw);
	92	+static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value);
35	93	static int32_t e1000_set_phy_type(struct e1000_hw *hw);
36	94	static void e1000_phy_init_script(struct e1000_hw *hw);
37	95	static int32_t e1000_setup_copper_link(struct e1000_hw *hw);

		@@ -63,10 +121,15 @@ static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);
63	121	static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
64	122	static void e1000_release_eeprom(struct e1000_hw *hw);
65	123	static void e1000_standby_eeprom(struct e1000_hw *hw);
66		-static int32_t e1000_id_led_init(struct e1000_hw * hw);
67	124	static int32_t e1000_set_vco_speed(struct e1000_hw *hw);
68	125	static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw);
69	126	static int32_t e1000_set_phy_mode(struct e1000_hw *hw);
	127	+static int32_t e1000_host_if_read_cookie(struct e1000_hw hw, uint8_t buffer);
	128	+static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length);
	129	+static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw,
	130	+ uint16_t duplex);
	131	+static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
	132	+static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
70	133
71	134	/* IGP cable length table */
72	135	static const

		@@ -80,31 +143,58 @@ uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
80	143	100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
81	144	110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
82	145
	146	+static const
	147	+uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
	148	+ { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
	149	+ 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
	150	+ 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
	151	+ 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
	152	+ 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
	153	+ 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
	154	+ 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
	155	+ 104, 109, 114, 118, 121, 124};
83	156
84	157	/******************************************************************************
85	158	* Set the phy type member in the hw struct.
86	159	*
87	160	* hw - Struct containing variables accessed by shared code
88	161	*****************************************************************************/
89		-int32_t
	162	+static int32_t
90	163	e1000_set_phy_type(struct e1000_hw *hw)
91	164	{
92	165	DEBUGFUNC("e1000_set_phy_type");
93	166
94		- switch(hw->phy_id) {
	167	+ if (hw->mac_type == e1000_undefined)
	168	+ return -E1000_ERR_PHY_TYPE;
	169	+
	170	+ switch (hw->phy_id) {
95	171	case M88E1000_E_PHY_ID:
96	172	case M88E1000_I_PHY_ID:
97	173	case M88E1011_I_PHY_ID:
	174	+ case M88E1111_I_PHY_ID:
98	175	hw->phy_type = e1000_phy_m88;
99	176	break;
100	177	case IGP01E1000_I_PHY_ID:
101		- if(hw->mac_type == e1000_82541 \|\|
102		- hw->mac_type == e1000_82541_rev_2 \|\|
103		- hw->mac_type == e1000_82547 \|\|
104		- hw->mac_type == e1000_82547_rev_2) {
	178	+ if (hw->mac_type == e1000_82541 \|\|
	179	+ hw->mac_type == e1000_82541_rev_2 \|\|
	180	+ hw->mac_type == e1000_82547 \|\|
	181	+ hw->mac_type == e1000_82547_rev_2) {
105	182	hw->phy_type = e1000_phy_igp;
106	183	break;
107	184	}
	185	+ case IGP03E1000_E_PHY_ID:
	186	+ hw->phy_type = e1000_phy_igp_3;
	187	+ break;
	188	+ case IFE_E_PHY_ID:
	189	+ case IFE_PLUS_E_PHY_ID:
	190	+ case IFE_C_E_PHY_ID:
	191	+ hw->phy_type = e1000_phy_ife;
	192	+ break;
	193	+ case GG82563_E_PHY_ID:
	194	+ if (hw->mac_type == e1000_80003es2lan) {
	195	+ hw->phy_type = e1000_phy_gg82563;
	196	+ break;
	197	+ }
108	198	/* Fall Through */
109	199	default:
110	200	/* Should never have loaded on this device */

		@@ -128,8 +218,7 @@ e1000_phy_init_script(struct e1000_hw *hw)
128	218
129	219	DEBUGFUNC("e1000_phy_init_script");
130	220
131		-
132		- if(hw->phy_init_script) {
	221	+ if (hw->phy_init_script) {
133	222	msec_delay(20);
134	223
135	224	/* Save off the current value of register 0x2F5B to be restored at

		@@ -145,7 +234,7 @@ e1000_phy_init_script(struct e1000_hw *hw)
145	234
146	235	msec_delay(5);
147	236
148		- switch(hw->mac_type) {
	237	+ switch (hw->mac_type) {
149	238	case e1000_82541:
150	239	case e1000_82547:
151	240	e1000_write_phy_reg(hw, 0x1F95, 0x0001);

		@@ -182,22 +271,22 @@ e1000_phy_init_script(struct e1000_hw *hw)
182	271	/* Now enable the transmitter */
183	272	e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
184	273
185		- if(hw->mac_type == e1000_82547) {
	274	+ if (hw->mac_type == e1000_82547) {
186	275	uint16_t fused, fine, coarse;
187	276
188	277	/* Move to analog registers page */
189	278	e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
190	279
191		- if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
	280	+ if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
192	281	e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
193	282
194	283	fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
195	284	coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
196	285
197		- if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
	286	+ if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
198	287	coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
199	288	fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
200		- } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
	289	+ } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
201	290	fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
202	291
203	292	fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) \|

		@@ -271,10 +360,13 @@ e1000_set_mac_type(struct e1000_hw *hw)
271	360	case E1000_DEV_ID_82546GB_FIBER:
272	361	case E1000_DEV_ID_82546GB_SERDES:
273	362	case E1000_DEV_ID_82546GB_PCIE:
	363	+ case E1000_DEV_ID_82546GB_QUAD_COPPER:
	364	+ case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
274	365	hw->mac_type = e1000_82546_rev_3;
275	366	break;
276	367	case E1000_DEV_ID_82541EI:
277	368	case E1000_DEV_ID_82541EI_MOBILE:
	369	+ case E1000_DEV_ID_82541ER_LOM:
278	370	hw->mac_type = e1000_82541;
279	371	break;
280	372	case E1000_DEV_ID_82541ER:

		@@ -284,17 +376,66 @@ e1000_set_mac_type(struct e1000_hw *hw)
284	376	hw->mac_type = e1000_82541_rev_2;
285	377	break;
286	378	case E1000_DEV_ID_82547EI:
	379	+ case E1000_DEV_ID_82547EI_MOBILE:
287	380	hw->mac_type = e1000_82547;
288	381	break;
289	382	case E1000_DEV_ID_82547GI:
290	383	hw->mac_type = e1000_82547_rev_2;
291	384	break;
	385	+ case E1000_DEV_ID_82571EB_COPPER:
	386	+ case E1000_DEV_ID_82571EB_FIBER:
	387	+ case E1000_DEV_ID_82571EB_SERDES:
	388	+ case E1000_DEV_ID_82571EB_QUAD_COPPER:
	389	+ case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
	390	+ hw->mac_type = e1000_82571;
	391	+ break;
	392	+ case E1000_DEV_ID_82572EI_COPPER:
	393	+ case E1000_DEV_ID_82572EI_FIBER:
	394	+ case E1000_DEV_ID_82572EI_SERDES:
	395	+ case E1000_DEV_ID_82572EI:
	396	+ hw->mac_type = e1000_82572;
	397	+ break;
	398	+ case E1000_DEV_ID_82573E:
	399	+ case E1000_DEV_ID_82573E_IAMT:
	400	+ case E1000_DEV_ID_82573L:
	401	+ hw->mac_type = e1000_82573;
	402	+ break;
	403	+ case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
	404	+ case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
	405	+ case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
	406	+ case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
	407	+ hw->mac_type = e1000_80003es2lan;
	408	+ break;
	409	+ case E1000_DEV_ID_ICH8_IGP_M_AMT:
	410	+ case E1000_DEV_ID_ICH8_IGP_AMT:
	411	+ case E1000_DEV_ID_ICH8_IGP_C:
	412	+ case E1000_DEV_ID_ICH8_IFE:
	413	+ case E1000_DEV_ID_ICH8_IFE_GT:
	414	+ case E1000_DEV_ID_ICH8_IFE_G:
	415	+ case E1000_DEV_ID_ICH8_IGP_M:
	416	+ hw->mac_type = e1000_ich8lan;
	417	+ hw->is_ich = TRUE;
	418	+ break;
	419	+
	420	+
292	421	default:
293	422	/* Should never have loaded on this device */
294	423	return -E1000_ERR_MAC_TYPE;
295	424	}
296	425
297		- switch(hw->mac_type) {
	426	+ switch (hw->mac_type) {
	427	+ case e1000_ich8lan:
	428	+ hw->swfwhw_semaphore_present = TRUE;
	429	+ hw->asf_firmware_present = TRUE;
	430	+ break;
	431	+ case e1000_80003es2lan:
	432	+ hw->swfw_sync_present = TRUE;
	433	+ /* fall through */
	434	+ case e1000_82571:
	435	+ case e1000_82572:
	436	+ case e1000_82573:
	437	+ hw->eeprom_semaphore_present = TRUE;
	438	+ /* fall through */
298	439	case e1000_82541:
299	440	case e1000_82547:
300	441	case e1000_82541_rev_2:

		@@ -320,7 +461,7 @@ e1000_set_media_type(struct e1000_hw *hw)
320	461
321	462	DEBUGFUNC("e1000_set_media_type");
322	463
323		- if(hw->mac_type != e1000_82543) {
	464	+ if (hw->mac_type != e1000_82543) {
324	465	/* tbi_compatibility is only valid on 82543 */
325	466	hw->tbi_compatibility_en = FALSE;
326	467	}

		@@ -328,21 +469,34 @@ e1000_set_media_type(struct e1000_hw *hw)
328	469	switch (hw->device_id) {
329	470	case E1000_DEV_ID_82545GM_SERDES:
330	471	case E1000_DEV_ID_82546GB_SERDES:
	472	+ case E1000_DEV_ID_82571EB_SERDES:
	473	+ case E1000_DEV_ID_82572EI_SERDES:
	474	+ case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
331	475	hw->media_type = e1000_media_type_internal_serdes;
332	476	break;
333	477	default:
334		- if(hw->mac_type >= e1000_82543) {
	478	+ switch (hw->mac_type) {
	479	+ case e1000_82542_rev2_0:
	480	+ case e1000_82542_rev2_1:
	481	+ hw->media_type = e1000_media_type_fiber;
	482	+ break;
	483	+ case e1000_ich8lan:
	484	+ case e1000_82573:
	485	+ /* The STATUS_TBIMODE bit is reserved or reused for the this
	486	+ * device.
	487	+ */
	488	+ hw->media_type = e1000_media_type_copper;
	489	+ break;
	490	+ default:
335	491	status = E1000_READ_REG(hw, STATUS);
336		- if(status & E1000_STATUS_TBIMODE) {
	492	+ if (status & E1000_STATUS_TBIMODE) {
337	493	hw->media_type = e1000_media_type_fiber;
338	494	/* tbi_compatibility not valid on fiber */
339	495	hw->tbi_compatibility_en = FALSE;
340	496	} else {
341	497	hw->media_type = e1000_media_type_copper;
342	498	}
343		- } else {
344		- /* This is an 82542 (fiber only) */
345		- hw->media_type = e1000_media_type_fiber;
	499	+ break;
346	500	}
347	501	}
348	502	}

		@@ -360,15 +514,27 @@ e1000_reset_hw(struct e1000_hw *hw)
360	514	uint32_t icr;
361	515	uint32_t manc;
362	516	uint32_t led_ctrl;
	517	+ uint32_t timeout;
	518	+ uint32_t extcnf_ctrl;
	519	+ int32_t ret_val;
363	520
364	521	DEBUGFUNC("e1000_reset_hw");
365	522
366	523	/* For 82542 (rev 2.0), disable MWI before issuing a device reset */
367		- if(hw->mac_type == e1000_82542_rev2_0) {
	524	+ if (hw->mac_type == e1000_82542_rev2_0) {
368	525	DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
369	526	e1000_pci_clear_mwi(hw);
370	527	}
371	528
	529	+ if (hw->bus_type == e1000_bus_type_pci_express) {
	530	+ /* Prevent the PCI-E bus from sticking if there is no TLP connection
	531	+ * on the last TLP read/write transaction when MAC is reset.
	532	+ */
	533	+ if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
	534	+ DEBUGOUT("PCI-E Master disable polling has failed.\n");
	535	+ }
	536	+ }
	537	+
372	538	/* Clear interrupt mask to stop board from generating interrupts */
373	539	DEBUGOUT("Masking off all interrupts\n");
374	540	E1000_WRITE_REG(hw, IMC, 0xffffffff);

		@@ -392,11 +558,42 @@ e1000_reset_hw(struct e1000_hw *hw)
392	558	ctrl = E1000_READ_REG(hw, CTRL);
393	559
394	560	/* Must reset the PHY before resetting the MAC */
395		- if((hw->mac_type == e1000_82541) \|\| (hw->mac_type == e1000_82547)) {
396		- E1000_WRITE_REG_IO(hw, CTRL, (ctrl \| E1000_CTRL_PHY_RST));
	561	+ if ((hw->mac_type == e1000_82541) \|\| (hw->mac_type == e1000_82547)) {
	562	+ E1000_WRITE_REG(hw, CTRL, (ctrl \| E1000_CTRL_PHY_RST));
397	563	msec_delay(5);
398	564	}
399	565
	566	+ /* Must acquire the MDIO ownership before MAC reset.
	567	+ * Ownership defaults to firmware after a reset. */
	568	+ if (hw->mac_type == e1000_82573) {
	569	+ timeout = 10;
	570	+
	571	+ extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
	572	+ extcnf_ctrl \|= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
	573	+
	574	+ do {
	575	+ E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
	576	+ extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
	577	+
	578	+ if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
	579	+ break;
	580	+ else
	581	+ extcnf_ctrl \|= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
	582	+
	583	+ msec_delay(2);
	584	+ timeout--;
	585	+ } while (timeout);
	586	+ }
	587	+
	588	+ /* Workaround for ICH8 bit corruption issue in FIFO memory */
	589	+ if (hw->mac_type == e1000_ich8lan)
	590	+ {
	591	+ /* Set Tx and Rx buffer allocation to 8k apiece. */
	592	+ E1000_WRITE_REG(hw, PBA, E1000_PBA_8K);
	593	+ /* Set Packet Buffer Size to 16k. */
	594	+ E1000_WRITE_REG(hw, PBS, E1000_PBS_16K);
	595	+ }
	596	+
400	597	/* Issue a global reset to the MAC. This will reset the chip's
401	598	* transmit, receive, DMA, and link units. It will not effect
402	599	* the current PCI configuration. The global reset bit is self-

		@@ -404,7 +601,7 @@ e1000_reset_hw(struct e1000_hw *hw)
404	601	*/
405	602	DEBUGOUT("Issuing a global reset to MAC\n");
406	603
407		- switch(hw->mac_type) {
	604	+ switch (hw->mac_type) {
408	605	case e1000_82544:
409	606	case e1000_82540:
410	607	case e1000_82545:

		@@ -420,6 +617,20 @@ e1000_reset_hw(struct e1000_hw *hw)
420	617	/* Reset is performed on a shadow of the control register */
421	618	E1000_WRITE_REG(hw, CTRL_DUP, (ctrl \| E1000_CTRL_RST));
422	619	break;
	620	+ case e1000_ich8lan:
	621	+ if (!hw->phy_reset_disable &&
	622	+ e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {
	623	+ /* e1000_ich8lan PHY HW reset requires MAC CORE reset
	624	+ * at the same time to make sure the interface between
	625	+ * MAC and the external PHY is reset.
	626	+ */
	627	+ ctrl \|= E1000_CTRL_PHY_RST;
	628	+ }
	629	+
	630	+ e1000_get_software_flag(hw);
	631	+ E1000_WRITE_REG(hw, CTRL, (ctrl \| E1000_CTRL_RST));
	632	+ msec_delay(5);
	633	+ break;
423	634	default:
424	635	E1000_WRITE_REG(hw, CTRL, (ctrl \| E1000_CTRL_RST));
425	636	break;

		@@ -429,13 +640,13 @@ e1000_reset_hw(struct e1000_hw *hw)
429	640	* device. Later controllers reload the EEPROM automatically, so just wait
430	641	* for reload to complete.
431	642	*/
432		- switch(hw->mac_type) {
	643	+ switch (hw->mac_type) {
433	644	case e1000_82542_rev2_0:
434	645	case e1000_82542_rev2_1:
435	646	case e1000_82543:
436	647	case e1000_82544:
437	648	/* Wait for reset to complete */
438		- udelay(10);
	649	+ usec_delay(10);
439	650	ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
440	651	ctrl_ext \|= E1000_CTRL_EXT_EE_RST;
441	652	E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);

		@@ -450,20 +661,31 @@ e1000_reset_hw(struct e1000_hw *hw)
450	661	/* Wait for EEPROM reload */
451	662	msec_delay(20);
452	663	break;
	664	+ case e1000_82573:
	665	+ if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
	666	+ usec_delay(10);
	667	+ ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
	668	+ ctrl_ext \|= E1000_CTRL_EXT_EE_RST;
	669	+ E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
	670	+ E1000_WRITE_FLUSH(hw);
	671	+ }
	672	+ /* fall through */
453	673	default:
454		- /* Wait for EEPROM reload (it happens automatically) */
455		- msec_delay(5);
	674	+ /* Auto read done will delay 5ms or poll based on mac type */
	675	+ ret_val = e1000_get_auto_rd_done(hw);
	676	+ if (ret_val)
	677	+ return ret_val;
456	678	break;
457	679	}
458	680
459	681	/* Disable HW ARPs on ASF enabled adapters */
460		- if(hw->mac_type >= e1000_82540) {
	682	+ if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
461	683	manc = E1000_READ_REG(hw, MANC);
462	684	manc &= ~(E1000_MANC_ARP_EN);
463	685	E1000_WRITE_REG(hw, MANC, manc);
464	686	}
465	687
466		- if((hw->mac_type == e1000_82541) \|\| (hw->mac_type == e1000_82547)) {
	688	+ if ((hw->mac_type == e1000_82541) \|\| (hw->mac_type == e1000_82547)) {
467	689	e1000_phy_init_script(hw);
468	690
469	691	/* Configure activity LED after PHY reset */

		@@ -481,15 +703,137 @@ e1000_reset_hw(struct e1000_hw *hw)
481	703	icr = E1000_READ_REG(hw, ICR);
482	704
483	705	/* If MWI was previously enabled, reenable it. */
484		- if(hw->mac_type == e1000_82542_rev2_0) {
485		- if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
	706	+ if (hw->mac_type == e1000_82542_rev2_0) {
	707	+ if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
486	708	e1000_pci_set_mwi(hw);
487	709	}
488	710
	711	+ if (hw->is_ich) {
	712	+ uint32_t kab = E1000_READ_REG(hw, KABGTXD);
	713	+ kab \|= E1000_KABGTXD_BGSQLBIAS;
	714	+ E1000_WRITE_REG(hw, KABGTXD, kab);
	715	+ }
	716	+
489	717	return E1000_SUCCESS;
490	718	}
491	719
492	720	/******************************************************************************
	721	+ *
	722	+ * Initialize a number of hardware-dependent bits
	723	+ *
	724	+ * hw: Struct containing variables accessed by shared code
	725	+ *
	726	+ *****************************************************************************/
	727	+static void
	728	+e1000_initialize_hardware_bits(struct e1000_hw *hw)
	729	+{
	730	+ if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) {
	731	+ /* Settings common to all PCI-express silicon */
	732	+ uint32_t reg_ctrl, reg_ctrl_ext;
	733	+ uint32_t reg_tarc0, reg_tarc1;
	734	+ uint32_t reg_tctl;
	735	+ uint32_t reg_txdctl, reg_txdctl1;
	736	+
	737	+ reg_tarc0 = E1000_READ_REG(hw, TARC0);
	738	+ /* link autonegotiation/sync workarounds */
	739	+ reg_tarc0 &= ~((1 << 30)\|(1 << 29)\|(1 << 28)\|(1 << 27));
	740	+
	741	+ reg_txdctl = E1000_READ_REG(hw, TXDCTL);
	742	+ /* Enable not-done TX descriptor counting */
	743	+ reg_txdctl \|= E1000_TXDCTL_COUNT_DESC;
	744	+ E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
	745	+
	746	+ reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
	747	+ reg_txdctl1 \|= E1000_TXDCTL_COUNT_DESC;
	748	+ E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
	749	+
	750	+ switch (hw->mac_type) {
	751	+ case e1000_82571:
	752	+ case e1000_82572:
	753	+ reg_tarc1 = E1000_READ_REG(hw, TARC1);
	754	+ reg_tctl = E1000_READ_REG(hw, TCTL);
	755	+
	756	+ /* Clear PHY TX compatible mode bits */
	757	+ reg_tarc1 &= ~((1 << 30)\|(1 << 29));
	758	+
	759	+ /* link autonegotiation/sync workarounds */
	760	+ reg_tarc0 \|= ((1 << 26)\|(1 << 25)\|(1 << 24)\|(1 << 23));
	761	+ /* TX ring control fixes */
	762	+ reg_tarc1 \|= ((1 << 26)\|(1 << 25)\|(1 << 24));
	763	+
	764	+ /* Multiple read bit is reversed polarity */
	765	+ if (reg_tctl & E1000_TCTL_MULR)
	766	+ reg_tarc1 &= ~(1 << 28);
	767	+ else
	768	+ reg_tarc1 \|= (1 << 28);
	769	+
	770	+ E1000_WRITE_REG(hw, TARC1, reg_tarc1);
	771	+ break;
	772	+ case e1000_82573:
	773	+ reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
	774	+ reg_ctrl = E1000_READ_REG(hw, CTRL);
	775	+
	776	+ reg_ctrl_ext &= ~(1 << 23);
	777	+ reg_ctrl_ext \|= (1 << 22);
	778	+ /* TX byte count fix */
	779	+ reg_ctrl &= ~(1 << 29);
	780	+
	781	+ E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
	782	+ E1000_WRITE_REG(hw, CTRL, reg_ctrl);
	783	+ break;
	784	+ case e1000_80003es2lan:
	785	+ /* improve small packet performance for fiber/serdes */
	786	+ if ((hw->media_type == e1000_media_type_fiber) \|\|
	787	+ (hw->media_type == e1000_media_type_internal_serdes)) {
	788	+ reg_tarc0 &= ~(1 << 20);
	789	+ }
	790	+
	791	+ /* Multiple read bit is reversed polarity */
	792	+ reg_tctl = E1000_READ_REG(hw, TCTL);
	793	+ reg_tarc1 = E1000_READ_REG(hw, TARC1);
	794	+ if (reg_tctl & E1000_TCTL_MULR)
	795	+ reg_tarc1 &= ~(1 << 28);
	796	+ else
	797	+ reg_tarc1 \|= (1 << 28);
	798	+
	799	+ E1000_WRITE_REG(hw, TARC1, reg_tarc1);
	800	+ break;
	801	+ case e1000_ich8lan:
	802	+ /* Reduce concurrent DMA requests to 3 from 4 */
	803	+ if ((hw->revision_id < 3) \|\|
	804	+ ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
	805	+ (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
	806	+ reg_tarc0 \|= ((1 << 29)\|(1 << 28));
	807	+ reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
	808	+ reg_ctrl_ext \|= (1 << 22);
	809	+ E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
	810	+
	811	+ /* workaround TX hang with TSO=on */
	812	+ reg_tarc0 \|= ((1 << 27)\|(1 << 26)\|(1 << 24)\|(1 << 23));
	813	+
	814	+ reg_tarc1 = E1000_READ_REG(hw, TARC1);
	815	+ reg_tctl = E1000_READ_REG(hw, TCTL);
	816	+
	817	+ /* Multiple read bit is reversed polarity */
	818	+ if (reg_tctl & E1000_TCTL_MULR)
	819	+ reg_tarc1 &= ~(1 << 28);
	820	+ else
	821	+ reg_tarc1 \|= (1 << 28);
	822	+
	823	+ /* workaround TX hang and TSO=on */
	824	+ reg_tarc1 \|= ((1 << 30)\|(1 << 26)\|(1 << 24));
	825	+
	826	+ E1000_WRITE_REG(hw, TARC1, reg_tarc1);
	827	+ break;
	828	+ default:
	829	+ break;
	830	+ }
	831	+
	832	+ E1000_WRITE_REG(hw, TARC0, reg_tarc0);
	833	+ }
	834	+}
	835	+
	836	+/******************************************************************************
493	837	* Performs basic configuration of the adapter.
494	838	*
495	839	* hw - Struct containing variables accessed by shared code

		@@ -510,11 +854,25 @@ e1000_init_hw(struct e1000_hw *hw)
510	854	uint16_t pcix_stat_hi_word;
511	855	uint16_t cmd_mmrbc;
512	856	uint16_t stat_mmrbc;
	857	+ uint32_t mta_size;
	858	+ uint32_t reg_data;
	859	+ uint32_t ctrl_ext;
	860	+
513	861	DEBUGFUNC("e1000_init_hw");
514	862
	863	+ /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
	864	+ if ((hw->mac_type == e1000_ich8lan) &&
	865	+ ((hw->revision_id < 3) \|\|
	866	+ ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
	867	+ (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
	868	+ reg_data = E1000_READ_REG(hw, STATUS);
	869	+ reg_data &= ~0x80000000;
	870	+ E1000_WRITE_REG(hw, STATUS, reg_data);
	871	+ }
	872	+
515	873	/* Initialize Identification LED */
516	874	ret_val = e1000_id_led_init(hw);
517		- if(ret_val) {
	875	+ if (ret_val) {
518	876	DEBUGOUT("Error Initializing Identification LED\n");
519	877	return ret_val;
520	878	}

		@@ -522,14 +880,19 @@ e1000_init_hw(struct e1000_hw *hw)
522	880	/* Set the media type and TBI compatibility */
523	881	e1000_set_media_type(hw);
524	882
	883	+ /* Must be called after e1000_set_media_type because media_type is used */
	884	+ e1000_initialize_hardware_bits(hw);
525	885	/* Disabling VLAN filtering. */
526	886	DEBUGOUT("Initializing the IEEE VLAN\n");
527		- E1000_WRITE_REG(hw, VET, 0);
528		-
529		- e1000_clear_vfta(hw);
	887	+ /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
	888	+ if (hw->is_ich == FALSE) {
	889	+ if (hw->mac_type < e1000_82545_rev_3)
	890	+ E1000_WRITE_REG(hw, VET, 0);
	891	+ e1000_clear_vfta(hw);
	892	+ }
530	893
531	894	/* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
532		- if(hw->mac_type == e1000_82542_rev2_0) {
	895	+ if (hw->mac_type == e1000_82542_rev2_0) {
533	896	DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
534	897	e1000_pci_clear_mwi(hw);
535	898	E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);

		@@ -543,35 +906,43 @@ e1000_init_hw(struct e1000_hw *hw)
543	906	e1000_init_rx_addrs(hw);
544	907
545	908	/* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
546		- if(hw->mac_type == e1000_82542_rev2_0) {
	909	+ if (hw->mac_type == e1000_82542_rev2_0) {
547	910	E1000_WRITE_REG(hw, RCTL, 0);
548	911	E1000_WRITE_FLUSH(hw);
549	912	msec_delay(1);
550		- if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
	913	+ if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
551	914	e1000_pci_set_mwi(hw);
552	915	}
553	916
554	917	/* Zero out the Multicast HASH table */
555	918	DEBUGOUT("Zeroing the MTA\n");
556		- for(i = 0; i < E1000_MC_TBL_SIZE; i++)
	919	+ mta_size = E1000_MC_TBL_SIZE;
	920	+ if (hw->is_ich == TRUE)
	921	+ mta_size = E1000_MC_TBL_SIZE_ICHXLAN;
	922	+ for (i = 0; i < mta_size; i++) {
557	923	E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
	924	+ /* use write flush to prevent Memory Write Block (MWB) from
	925	+ * occuring when accessing our register space */
	926	+ E1000_WRITE_FLUSH(hw);
	927	+ }
558	928
559	929	/* Set the PCI priority bit correctly in the CTRL register. This
560	930	* determines if the adapter gives priority to receives, or if it
561		- * gives equal priority to transmits and receives.
	931	+ * gives equal priority to transmits and receives. Valid only on
	932	+ * 82542 and 82543 silicon.
562	933	*/
563		- if(hw->dma_fairness) {
	934	+ if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
564	935	ctrl = E1000_READ_REG(hw, CTRL);
565	936	E1000_WRITE_REG(hw, CTRL, ctrl \| E1000_CTRL_PRIOR);
566	937	}
567	938
568		- switch(hw->mac_type) {
	939	+ switch (hw->mac_type) {
569	940	case e1000_82545_rev_3:
570	941	case e1000_82546_rev_3:
571	942	break;
572	943	default:
573	944	/* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
574		- if(hw->bus_type == e1000_bus_type_pcix) {
	945	+ if (hw->bus_type == e1000_bus_type_pcix) {
575	946	e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
576	947	e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
577	948	&pcix_stat_hi_word);

		@@ -579,9 +950,9 @@ e1000_init_hw(struct e1000_hw *hw)
579	950	PCIX_COMMAND_MMRBC_SHIFT;
580	951	stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
581	952	PCIX_STATUS_HI_MMRBC_SHIFT;
582		- if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
	953	+ if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
583	954	stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
584		- if(cmd_mmrbc > stat_mmrbc) {
	955	+ if (cmd_mmrbc > stat_mmrbc) {
585	956	pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
586	957	pcix_cmd_word \|= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
587	958	e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,

		@@ -591,16 +962,65 @@ e1000_init_hw(struct e1000_hw *hw)
591	962	break;
592	963	}
593	964
	965	+ /* More time needed for PHY to initialize */
	966	+ if (hw->is_ich == TRUE)
	967	+ msec_delay(15);
	968	+
594	969	/* Call a subroutine to configure the link and setup flow control. */
595	970	ret_val = e1000_setup_link(hw);
596	971
597	972	/* Set the transmit descriptor write-back policy */
598		- if(hw->mac_type > e1000_82544) {
	973	+ if (hw->mac_type > e1000_82544) {
599	974	ctrl = E1000_READ_REG(hw, TXDCTL);
600	975	ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) \| E1000_TXDCTL_FULL_TX_DESC_WB;
601	976	E1000_WRITE_REG(hw, TXDCTL, ctrl);
602	977	}
603	978
	979	+ if (hw->mac_type == e1000_82573) {
	980	+ e1000_enable_tx_pkt_filtering(hw);
	981	+ }
	982	+
	983	+ switch (hw->mac_type) {
	984	+ default:
	985	+ break;
	986	+ case e1000_80003es2lan:
	987	+ /* Enable retransmit on late collisions */
	988	+ reg_data = E1000_READ_REG(hw, TCTL);
	989	+ reg_data \|= E1000_TCTL_RTLC;
	990	+ E1000_WRITE_REG(hw, TCTL, reg_data);
	991	+
	992	+ /* Configure Gigabit Carry Extend Padding */
	993	+ reg_data = E1000_READ_REG(hw, TCTL_EXT);
	994	+ reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
	995	+ reg_data \|= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
	996	+ E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
	997	+
	998	+ /* Configure Transmit Inter-Packet Gap */
	999	+ reg_data = E1000_READ_REG(hw, TIPG);
	1000	+ reg_data &= ~E1000_TIPG_IPGT_MASK;
	1001	+ reg_data \|= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
	1002	+ E1000_WRITE_REG(hw, TIPG, reg_data);
	1003	+
	1004	+ reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
	1005	+ reg_data &= ~0x00100000;
	1006	+ E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
	1007	+ /* Fall through */
	1008	+ case e1000_82571:
	1009	+ case e1000_82572:
	1010	+ case e1000_ich8lan:
	1011	+ ctrl = E1000_READ_REG(hw, TXDCTL1);
	1012	+ ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) \| E1000_TXDCTL_FULL_TX_DESC_WB;
	1013	+ E1000_WRITE_REG(hw, TXDCTL1, ctrl);
	1014	+ break;
	1015	+ }
	1016	+
	1017	+
	1018	+ if (hw->mac_type == e1000_82573) {
	1019	+ uint32_t gcr = E1000_READ_REG(hw, GCR);
	1020	+ gcr \|= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
	1021	+ E1000_WRITE_REG(hw, GCR, gcr);
	1022	+ }
	1023	+
604	1024	/* Clear all of the statistics registers (clear on read). It is
605	1025	* important that we do this after we have tried to establish link
606	1026	* because the symbol error count will increment wildly if there

		@@ -608,6 +1028,20 @@ e1000_init_hw(struct e1000_hw *hw)
608	1028	*/
609	1029	e1000_clear_hw_cntrs(hw);
610	1030
	1031	+ /* ICH8 No-snoop bits are opposite polarity.
	1032	+ * Set to snoop by default after reset. */
	1033	+ if (hw->mac_type == e1000_ich8lan)
	1034	+ e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
	1035	+
	1036	+ if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER \|\|
	1037	+ hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
	1038	+ ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
	1039	+ /* Relaxed ordering must be disabled to avoid a parity
	1040	+ * error crash in a PCI slot. */
	1041	+ ctrl_ext \|= E1000_CTRL_EXT_RO_DIS;
	1042	+ E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
	1043	+ }
	1044	+
611	1045	return ret_val;
612	1046	}
613	1047

		@@ -624,10 +1058,10 @@ e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
624	1058
625	1059	DEBUGFUNC("e1000_adjust_serdes_amplitude");
626	1060
627		- if(hw->media_type != e1000_media_type_internal_serdes)
	1061	+ if (hw->media_type != e1000_media_type_internal_serdes)
628	1062	return E1000_SUCCESS;
629	1063
630		- switch(hw->mac_type) {
	1064	+ switch (hw->mac_type) {
631	1065	case e1000_82545_rev_3:
632	1066	case e1000_82546_rev_3:
633	1067	break;

		@@ -640,11 +1074,11 @@ e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
640	1074	return ret_val;
641	1075	}
642	1076
643		- if(eeprom_data != EEPROM_RESERVED_WORD) {
	1077	+ if (eeprom_data != EEPROM_RESERVED_WORD) {
644	1078	/* Adjust SERDES output amplitude only. */
645		- eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
	1079	+ eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
646	1080	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
647		- if(ret_val)
	1081	+ if (ret_val)
648	1082	return ret_val;
649	1083	}
650	1084

		@@ -671,6 +1105,11 @@ e1000_setup_link(struct e1000_hw *hw)
671	1105
672	1106	DEBUGFUNC("e1000_setup_link");
673	1107
	1108	+ /* In the case of the phy reset being blocked, we already have a link.
	1109	+ * We do not have to set it up again. */
	1110	+ if (e1000_check_phy_reset_block(hw))
	1111	+ return E1000_SUCCESS;
	1112	+
674	1113	/* Read and store word 0x0F of the EEPROM. This word contains bits
675	1114	* that determine the hardware's default PAUSE (flow control) mode,
676	1115	* a bit that determines whether the HW defaults to enabling or

		@@ -679,30 +1118,39 @@ e1000_setup_link(struct e1000_hw *hw)
679	1118	* control setting, then the variable hw->fc will
680	1119	* be initialized based on a value in the EEPROM.
681	1120	*/
682		- if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) {
683		- DEBUGOUT("EEPROM Read Error\n");
684		- return -E1000_ERR_EEPROM;
685		- }
686		-
687		- if(hw->fc == e1000_fc_default) {
688		- if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
689		- hw->fc = e1000_fc_none;
690		- else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
691		- EEPROM_WORD0F_ASM_DIR)
692		- hw->fc = e1000_fc_tx_pause;
693		- else
694		- hw->fc = e1000_fc_full;
	1121	+ if (hw->fc == E1000_FC_DEFAULT) {
	1122	+ switch (hw->mac_type) {
	1123	+ case e1000_ich8lan:
	1124	+ case e1000_82573:
	1125	+ hw->fc = E1000_FC_FULL;
	1126	+ break;
	1127	+ default:
	1128	+ ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
	1129	+ 1, &eeprom_data);
	1130	+ if (ret_val) {
	1131	+ DEBUGOUT("EEPROM Read Error\n");
	1132	+ return -E1000_ERR_EEPROM;
	1133	+ }
	1134	+ if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
	1135	+ hw->fc = E1000_FC_NONE;
	1136	+ else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
	1137	+ EEPROM_WORD0F_ASM_DIR)
	1138	+ hw->fc = E1000_FC_TX_PAUSE;
	1139	+ else
	1140	+ hw->fc = E1000_FC_FULL;
	1141	+ break;
	1142	+ }
695	1143	}
696	1144
697	1145	/* We want to save off the original Flow Control configuration just
698	1146	* in case we get disconnected and then reconnected into a different
699	1147	* hub or switch with different Flow Control capabilities.
700	1148	*/
701		- if(hw->mac_type == e1000_82542_rev2_0)
702		- hw->fc &= (~e1000_fc_tx_pause);
	1149	+ if (hw->mac_type == e1000_82542_rev2_0)
	1150	+ hw->fc &= (~E1000_FC_TX_PAUSE);
703	1151
704		- if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
705		- hw->fc &= (~e1000_fc_rx_pause);
	1152	+ if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
	1153	+ hw->fc &= (~E1000_FC_RX_PAUSE);
706	1154
707	1155	hw->original_fc = hw->fc;
708	1156

		@@ -715,7 +1163,13 @@ e1000_setup_link(struct e1000_hw *hw)
715	1163	* signal detection. So this should be done before e1000_setup_pcs_link()
716	1164	* or e1000_phy_setup() is called.
717	1165	*/
718		- if(hw->mac_type == e1000_82543) {
	1166	+ if (hw->mac_type == e1000_82543) {
	1167	+ ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
	1168	+ 1, &eeprom_data);
	1169	+ if (ret_val) {
	1170	+ DEBUGOUT("EEPROM Read Error\n");
	1171	+ return -E1000_ERR_EEPROM;
	1172	+ }
719	1173	ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
720	1174	SWDPIO__EXT_SHIFT);
721	1175	E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);

		@@ -733,9 +1187,13 @@ e1000_setup_link(struct e1000_hw *hw)
733	1187	*/
734	1188	DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
735	1189
736		- E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
737		- E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
738		- E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
	1190	+ /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
	1191	+ if (hw->is_ich == FALSE) {
	1192	+ E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
	1193	+ E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
	1194	+ E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
	1195	+ }
	1196	+
739	1197	E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
740	1198
741	1199	/* Set the flow control receive threshold registers. Normally,

		@@ -744,14 +1202,14 @@ e1000_setup_link(struct e1000_hw *hw)
744	1202	* ability to transmit pause frames in not enabled, then these
745	1203	* registers will be set to 0.
746	1204	*/
747		- if(!(hw->fc & e1000_fc_tx_pause)) {
	1205	+ if (!(hw->fc & E1000_FC_TX_PAUSE)) {
748	1206	E1000_WRITE_REG(hw, FCRTL, 0);
749	1207	E1000_WRITE_REG(hw, FCRTH, 0);
750	1208	} else {
751	1209	/* We need to set up the Receive Threshold high and low water marks
752	1210	* as well as (optionally) enabling the transmission of XON frames.
753	1211	*/
754		- if(hw->fc_send_xon) {
	1212	+ if (hw->fc_send_xon) {
755	1213	E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water \| E1000_FCRTL_XONE));
756	1214	E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
757	1215	} else {

		@@ -783,18 +1241,26 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
783	1241
784	1242	DEBUGFUNC("e1000_setup_fiber_serdes_link");
785	1243
786		- /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
	1244	+ /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
	1245	+ * until explicitly turned off or a power cycle is performed. A read to
	1246	+ * the register does not indicate its status. Therefore, we ensure
	1247	+ * loopback mode is disabled during initialization.
	1248	+ */
	1249	+ if (hw->mac_type == e1000_82571 \|\| hw->mac_type == e1000_82572)
	1250	+ E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK);
	1251	+
	1252	+ /* On adapters with a MAC newer than 82544, SWDP 1 will be
787	1253	* set when the optics detect a signal. On older adapters, it will be
788	1254	* cleared when there is a signal. This applies to fiber media only.
789		- * If we're on serdes media, adjust the output amplitude to value set in
790		- * the EEPROM.
	1255	+ * If we're on serdes media, adjust the output amplitude to value
	1256	+ * set in the EEPROM.
791	1257	*/
792	1258	ctrl = E1000_READ_REG(hw, CTRL);
793		- if(hw->media_type == e1000_media_type_fiber)
	1259	+ if (hw->media_type == e1000_media_type_fiber)
794	1260	signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
795	1261
796	1262	ret_val = e1000_adjust_serdes_amplitude(hw);
797		- if(ret_val)
	1263	+ if (ret_val)
798	1264	return ret_val;
799	1265
800	1266	/* Take the link out of reset */

		@@ -802,7 +1268,7 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
802	1268
803	1269	/* Adjust VCO speed to improve BER performance */
804	1270	ret_val = e1000_set_vco_speed(hw);
805		- if(ret_val)
	1271	+ if (ret_val)
806	1272	return ret_val;
807	1273
808	1274	e1000_config_collision_dist(hw);

		@@ -823,11 +1289,11 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
823	1289	* 3: Both Rx and TX flow control (symmetric) are enabled.
824	1290	*/
825	1291	switch (hw->fc) {
826		- case e1000_fc_none:
	1292	+ case E1000_FC_NONE:
827	1293	/* Flow control is completely disabled by a software over-ride. */
828	1294	txcw = (E1000_TXCW_ANE \| E1000_TXCW_FD);
829	1295	break;
830		- case e1000_fc_rx_pause:
	1296	+ case E1000_FC_RX_PAUSE:
831	1297	/* RX Flow control is enabled and TX Flow control is disabled by a
832	1298	* software over-ride. Since there really isn't a way to advertise
833	1299	* that we are capable of RX Pause ONLY, we will advertise that we

		@@ -836,13 +1302,13 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
836	1302	*/
837	1303	txcw = (E1000_TXCW_ANE \| E1000_TXCW_FD \| E1000_TXCW_PAUSE_MASK);
838	1304	break;
839		- case e1000_fc_tx_pause:
	1305	+ case E1000_FC_TX_PAUSE:
840	1306	/* TX Flow control is enabled, and RX Flow control is disabled, by a
841	1307	* software over-ride.
842	1308	*/
843	1309	txcw = (E1000_TXCW_ANE \| E1000_TXCW_FD \| E1000_TXCW_ASM_DIR);
844	1310	break;
845		- case e1000_fc_full:
	1311	+ case E1000_FC_FULL:
846	1312	/* Flow control (both RX and TX) is enabled by a software over-ride. */
847	1313	txcw = (E1000_TXCW_ANE \| E1000_TXCW_FD \| E1000_TXCW_PAUSE_MASK);
848	1314	break;

		@@ -873,15 +1339,15 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
873	1339	* less than 500 milliseconds even if the other end is doing it in SW).
874	1340	* For internal serdes, we just assume a signal is present, then poll.
875	1341	*/
876		- if(hw->media_type == e1000_media_type_internal_serdes \|\|
	1342	+ if (hw->media_type == e1000_media_type_internal_serdes \|\|
877	1343	(E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
878	1344	DEBUGOUT("Looking for Link\n");
879		- for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
	1345	+ for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
880	1346	msec_delay(10);
881	1347	status = E1000_READ_REG(hw, STATUS);
882		- if(status & E1000_STATUS_LU) break;
	1348	+ if (status & E1000_STATUS_LU) break;
883	1349	}
884		- if(i == (LINK_UP_TIMEOUT / 10)) {
	1350	+ if (i == (LINK_UP_TIMEOUT / 10)) {
885	1351	DEBUGOUT("Never got a valid link from auto-neg!!!\n");
886	1352	hw->autoneg_failed = 1;
887	1353	/* AutoNeg failed to achieve a link, so we'll call

		@@ -890,7 +1356,7 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
890	1356	* non-autonegotiating link partners.
891	1357	*/
892	1358	ret_val = e1000_check_for_link(hw);
893		- if(ret_val) {
	1359	+ if (ret_val) {
894	1360	DEBUGOUT("Error while checking for link\n");
895	1361	return ret_val;
896	1362	}

		@@ -906,39 +1372,39 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
906	1372	}
907	1373
908	1374	/******************************************************************************
909		-* Detects which PHY is present and the speed and duplex
	1375	+* Make sure we have a valid PHY and change PHY mode before link setup.
910	1376	*
911	1377	* hw - Struct containing variables accessed by shared code
912	1378	******************************************************************************/
913	1379	static int32_t
914		-e1000_setup_copper_link(struct e1000_hw *hw)
	1380	+e1000_copper_link_preconfig(struct e1000_hw *hw)
915	1381	{
916	1382	uint32_t ctrl;
917		- uint32_t led_ctrl;
918	1383	int32_t ret_val;
919		- uint16_t i;
920	1384	uint16_t phy_data;
921	1385
922		- DEBUGFUNC("e1000_setup_copper_link");
	1386	+ DEBUGFUNC("e1000_copper_link_preconfig");
923	1387
924	1388	ctrl = E1000_READ_REG(hw, CTRL);
925	1389	/* With 82543, we need to force speed and duplex on the MAC equal to what
926	1390	* the PHY speed and duplex configuration is. In addition, we need to
927	1391	* perform a hardware reset on the PHY to take it out of reset.
928	1392	*/
929		- if(hw->mac_type > e1000_82543) {
	1393	+ if (hw->mac_type > e1000_82543) {
930	1394	ctrl \|= E1000_CTRL_SLU;
931	1395	ctrl &= ~(E1000_CTRL_FRCSPD \| E1000_CTRL_FRCDPX);
932	1396	E1000_WRITE_REG(hw, CTRL, ctrl);
933	1397	} else {
934	1398	ctrl \|= (E1000_CTRL_FRCSPD \| E1000_CTRL_FRCDPX \| E1000_CTRL_SLU);
935	1399	E1000_WRITE_REG(hw, CTRL, ctrl);
936		- e1000_phy_hw_reset(hw);
	1400	+ ret_val = e1000_phy_hw_reset(hw);
	1401	+ if (ret_val)
	1402	+ return ret_val;
937	1403	}
938	1404
939	1405	/* Make sure we have a valid PHY */
940	1406	ret_val = e1000_detect_gig_phy(hw);
941		- if(ret_val) {
	1407	+ if (ret_val) {
942	1408	DEBUGOUT("Error, did not detect valid phy.\n");
943	1409	return ret_val;
944	1410	}

		@@ -946,520 +1412,904 @@ e1000_setup_copper_link(struct e1000_hw *hw)
946	1412
947	1413	/* Set PHY to class A mode (if necessary) */
948	1414	ret_val = e1000_set_phy_mode(hw);
949		- if(ret_val)
	1415	+ if (ret_val)
950	1416	return ret_val;
951	1417
952		- if((hw->mac_type == e1000_82545_rev_3) \|\|
	1418	+ if ((hw->mac_type == e1000_82545_rev_3) \|\|
953	1419	(hw->mac_type == e1000_82546_rev_3)) {
954	1420	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
955	1421	phy_data \|= 0x00000008;
956	1422	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
957	1423	}
958	1424
959		- if(hw->mac_type <= e1000_82543 \|\|
960		- hw->mac_type == e1000_82541 \|\| hw->mac_type == e1000_82547 \|\|
961		- hw->mac_type == e1000_82541_rev_2 \|\| hw->mac_type == e1000_82547_rev_2)
	1425	+ if (hw->mac_type <= e1000_82543 \|\|
	1426	+ hw->mac_type == e1000_82541 \|\| hw->mac_type == e1000_82547 \|\|
	1427	+ hw->mac_type == e1000_82541_rev_2 \|\| hw->mac_type == e1000_82547_rev_2)
962	1428	hw->phy_reset_disable = FALSE;
963	1429
964		- if(!hw->phy_reset_disable) {
965		- if (hw->phy_type == e1000_phy_igp) {
	1430	+ return E1000_SUCCESS;
	1431	+}
966	1432
967		- ret_val = e1000_phy_reset(hw);
968		- if(ret_val) {
969		- DEBUGOUT("Error Resetting the PHY\n");
970		- return ret_val;
971		- }
972	1433
973		- /* Wait 10ms for MAC to configure PHY from eeprom settings */
974		- msec_delay(15);
	1434	+/********************************************************************
	1435	+* Copper link setup for e1000_phy_igp series.
	1436	+*
	1437	+* hw - Struct containing variables accessed by shared code
	1438	+*********************************************************************/
	1439	+static int32_t
	1440	+e1000_copper_link_igp_setup(struct e1000_hw *hw)
	1441	+{
	1442	+ uint32_t led_ctrl;
	1443	+ int32_t ret_val;
	1444	+ uint16_t phy_data;
975	1445
976		- /* Configure activity LED after PHY reset */
977		- led_ctrl = E1000_READ_REG(hw, LEDCTL);
978		- led_ctrl &= IGP_ACTIVITY_LED_MASK;
979		- led_ctrl \|= (IGP_ACTIVITY_LED_ENABLE \| IGP_LED3_MODE);
980		- E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
	1446	+ DEBUGFUNC("e1000_copper_link_igp_setup");
981	1447
982		- /* disable lplu d3 during driver init */
983		- ret_val = e1000_set_d3_lplu_state(hw, FALSE);
984		- if(ret_val) {
985		- DEBUGOUT("Error Disabling LPLU D3\n");
986		- return ret_val;
987		- }
	1448	+ if (hw->phy_reset_disable)
	1449	+ return E1000_SUCCESS;
988	1450
989		- /* Configure mdi-mdix settings */
990		- ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
991		- &phy_data);
992		- if(ret_val)
993		- return ret_val;
	1451	+ ret_val = e1000_phy_reset(hw);
	1452	+ if (ret_val) {
	1453	+ DEBUGOUT("Error Resetting the PHY\n");
	1454	+ return ret_val;
	1455	+ }
994	1456
995		- if((hw->mac_type == e1000_82541) \|\| (hw->mac_type == e1000_82547)) {
996		- hw->dsp_config_state = e1000_dsp_config_disabled;
997		- /* Force MDI for earlier revs of the IGP PHY */
998		- phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX \|
999		- IGP01E1000_PSCR_FORCE_MDI_MDIX);
1000		- hw->mdix = 1;
	1457	+ /* Wait 15ms for MAC to configure PHY from eeprom settings */
	1458	+ msec_delay(15);
	1459	+ if (hw->is_ich == FALSE) {
	1460	+ /* Configure activity LED after PHY reset */
	1461	+ led_ctrl = E1000_READ_REG(hw, LEDCTL);
	1462	+ led_ctrl &= IGP_ACTIVITY_LED_MASK;
	1463	+ led_ctrl \|= (IGP_ACTIVITY_LED_ENABLE \| IGP_LED3_MODE);
	1464	+ E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
	1465	+ }
1001	1466
1002		- } else {
1003		- hw->dsp_config_state = e1000_dsp_config_enabled;
1004		- phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
	1467	+ /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
	1468	+ if (hw->phy_type == e1000_phy_igp) {
	1469	+ /* disable lplu d3 during driver init */
	1470	+ ret_val = e1000_set_d3_lplu_state(hw, FALSE);
	1471	+ if (ret_val) {
	1472	+ DEBUGOUT("Error Disabling LPLU D3\n");
	1473	+ return ret_val;
	1474	+ }
	1475	+ }
1005	1476
1006		- switch (hw->mdix) {
1007		- case 1:
1008		- phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1009		- break;
1010		- case 2:
1011		- phy_data \|= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1012		- break;
1013		- case 0:
1014		- default:
1015		- phy_data \|= IGP01E1000_PSCR_AUTO_MDIX;
1016		- break;
1017		- }
1018		- }
1019		- ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1020		- phy_data);
1021		- if(ret_val)
1022		- return ret_val;
	1477	+ /* disable lplu d0 during driver init */
	1478	+ ret_val = e1000_set_d0_lplu_state(hw, FALSE);
	1479	+ if (ret_val) {
	1480	+ DEBUGOUT("Error Disabling LPLU D0\n");
	1481	+ return ret_val;
	1482	+ }
	1483	+ /* Configure mdi-mdix settings */
	1484	+ ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
	1485	+ if (ret_val)
	1486	+ return ret_val;
1023	1487
1024		- /* set auto-master slave resolution settings */
1025		- if(hw->autoneg) {
1026		- e1000_ms_type phy_ms_setting = hw->master_slave;
	1488	+ if ((hw->mac_type == e1000_82541) \|\| (hw->mac_type == e1000_82547)) {
	1489	+ hw->dsp_config_state = e1000_dsp_config_disabled;
	1490	+ /* Force MDI for earlier revs of the IGP PHY */
	1491	+ phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX \| IGP01E1000_PSCR_FORCE_MDI_MDIX);
	1492	+ hw->mdix = 1;
1027	1493
1028		- if(hw->ffe_config_state == e1000_ffe_config_active)
1029		- hw->ffe_config_state = e1000_ffe_config_enabled;
	1494	+ } else {
	1495	+ hw->dsp_config_state = e1000_dsp_config_enabled;
	1496	+ phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1030	1497
1031		- if(hw->dsp_config_state == e1000_dsp_config_activated)
1032		- hw->dsp_config_state = e1000_dsp_config_enabled;
	1498	+ switch (hw->mdix) {
	1499	+ case 1:
	1500	+ phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
	1501	+ break;
	1502	+ case 2:
	1503	+ phy_data \|= IGP01E1000_PSCR_FORCE_MDI_MDIX;
	1504	+ break;
	1505	+ case 0:
	1506	+ default:
	1507	+ phy_data \|= IGP01E1000_PSCR_AUTO_MDIX;
	1508	+ break;
	1509	+ }
	1510	+ }
	1511	+ ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
	1512	+ if (ret_val)
	1513	+ return ret_val;
1033	1514
1034		- /* when autonegotiation advertisment is only 1000Mbps then we
1035		- * should disable SmartSpeed and enable Auto MasterSlave
1036		- * resolution as hardware default. */
1037		- if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1038		- /* Disable SmartSpeed */
1039		- ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1040		- &phy_data);
1041		- if(ret_val)
1042		- return ret_val;
1043		- phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1044		- ret_val = e1000_write_phy_reg(hw,
1045		- IGP01E1000_PHY_PORT_CONFIG,
1046		- phy_data);
1047		- if(ret_val)
1048		- return ret_val;
1049		- /* Set auto Master/Slave resolution process */
1050		- ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1051		- if(ret_val)
1052		- return ret_val;
1053		- phy_data &= ~CR_1000T_MS_ENABLE;
1054		- ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1055		- if(ret_val)
1056		- return ret_val;
1057		- }
	1515	+ /* set auto-master slave resolution settings */
	1516	+ if (hw->autoneg) {
	1517	+ e1000_ms_type phy_ms_setting = hw->master_slave;
1058	1518
1059		- ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1060		- if(ret_val)
1061		- return ret_val;
	1519	+ if (hw->ffe_config_state == e1000_ffe_config_active)
	1520	+ hw->ffe_config_state = e1000_ffe_config_enabled;
1062	1521
1063		- /* load defaults for future use */
1064		- hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1065		- ((phy_data & CR_1000T_MS_VALUE) ?
1066		- e1000_ms_force_master :
1067		- e1000_ms_force_slave) :
1068		- e1000_ms_auto;
	1522	+ if (hw->dsp_config_state == e1000_dsp_config_activated)
	1523	+ hw->dsp_config_state = e1000_dsp_config_enabled;
1069	1524
1070		- switch (phy_ms_setting) {
1071		- case e1000_ms_force_master:
1072		- phy_data \|= (CR_1000T_MS_ENABLE \| CR_1000T_MS_VALUE);
1073		- break;
1074		- case e1000_ms_force_slave:
1075		- phy_data \|= CR_1000T_MS_ENABLE;
1076		- phy_data &= ~(CR_1000T_MS_VALUE);
1077		- break;
1078		- case e1000_ms_auto:
1079		- phy_data &= ~CR_1000T_MS_ENABLE;
1080		- default:
1081		- break;
1082		- }
1083		- ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1084		- if(ret_val)
1085		- return ret_val;
1086		- }
1087		- } else {
1088		- /* Enable CRS on TX. This must be set for half-duplex operation. */
1089		- ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
	1525	+ /* when autonegotiation advertisment is only 1000Mbps then we
	1526	+ * should disable SmartSpeed and enable Auto MasterSlave
	1527	+ * resolution as hardware default. */
	1528	+ if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
	1529	+ /* Disable SmartSpeed */
	1530	+ ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1090	1531	&phy_data);
1091		- if(ret_val)
	1532	+ if (ret_val)
1092	1533	return ret_val;
1093		-
1094		- phy_data \|= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1095		-
1096		- /* Options:
1097		- * MDI/MDI-X = 0 (default)
1098		- * 0 - Auto for all speeds
1099		- * 1 - MDI mode
1100		- * 2 - MDI-X mode
1101		- * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1102		- */
1103		- phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1104		-
1105		- switch (hw->mdix) {
1106		- case 1:
1107		- phy_data \|= M88E1000_PSCR_MDI_MANUAL_MODE;
1108		- break;
1109		- case 2:
1110		- phy_data \|= M88E1000_PSCR_MDIX_MANUAL_MODE;
1111		- break;
1112		- case 3:
1113		- phy_data \|= M88E1000_PSCR_AUTO_X_1000T;
1114		- break;
1115		- case 0:
1116		- default:
1117		- phy_data \|= M88E1000_PSCR_AUTO_X_MODE;
1118		- break;
1119		- }
1120		-
1121		- /* Options:
1122		- * disable_polarity_correction = 0 (default)
1123		- * Automatic Correction for Reversed Cable Polarity
1124		- * 0 - Disabled
1125		- * 1 - Enabled
1126		- */
1127		- phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1128		- if(hw->disable_polarity_correction == 1)
1129		- phy_data \|= M88E1000_PSCR_POLARITY_REVERSAL;
1130		- ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
	1534	+ phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
	1535	+ ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1131	1536	phy_data);
1132		- if(ret_val)
	1537	+ if (ret_val)
1133	1538	return ret_val;
1134		-
1135		- /* Force TX_CLK in the Extended PHY Specific Control Register
1136		- * to 25MHz clock.
1137		- */
1138		- ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1139		- &phy_data);
1140		- if(ret_val)
	1539	+ /* Set auto Master/Slave resolution process */
	1540	+ ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
	1541	+ if (ret_val)
1141	1542	return ret_val;
1142		-
1143		- phy_data \|= M88E1000_EPSCR_TX_CLK_25;
1144		-
1145		- if (hw->phy_revision < M88E1011_I_REV_4) {
1146		- /* Configure Master and Slave downshift values */
1147		- phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK \|
1148		- M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1149		- phy_data \|= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X \|
1150		- M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1151		- ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1152		- phy_data);
1153		- if(ret_val)
1154		- return ret_val;
1155		- }
1156		-
1157		- /* SW Reset the PHY so all changes take effect */
1158		- ret_val = e1000_phy_reset(hw);
1159		- if(ret_val) {
1160		- DEBUGOUT("Error Resetting the PHY\n");
	1543	+ phy_data &= ~CR_1000T_MS_ENABLE;
	1544	+ ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
	1545	+ if (ret_val)
1161	1546	return ret_val;
1162		- }
1163	1547	}
1164	1548
1165		- /* Options:
1166		- * autoneg = 1 (default)
1167		- * PHY will advertise value(s) parsed from
1168		- * autoneg_advertised and fc
1169		- * autoneg = 0
1170		- * PHY will be set to 10H, 10F, 100H, or 100F
1171		- * depending on value parsed from forced_speed_duplex.
1172		- */
	1549	+ ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
	1550	+ if (ret_val)
	1551	+ return ret_val;
1173	1552
1174		- /* Is autoneg enabled? This is enabled by default or by software
1175		- * override. If so, call e1000_phy_setup_autoneg routine to parse the
1176		- * autoneg_advertised and fc options. If autoneg is NOT enabled, then
1177		- * the user should have provided a speed/duplex override. If so, then
1178		- * call e1000_phy_force_speed_duplex to parse and set this up.
1179		- */
1180		- if(hw->autoneg) {
1181		- /* Perform some bounds checking on the hw->autoneg_advertised
1182		- * parameter. If this variable is zero, then set it to the default.
1183		- */
1184		- hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
	1553	+ /* load defaults for future use */
	1554	+ hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
	1555	+ ((phy_data & CR_1000T_MS_VALUE) ?
	1556	+ e1000_ms_force_master :
	1557	+ e1000_ms_force_slave) :
	1558	+ e1000_ms_auto;
1185	1559
1186		- /* If autoneg_advertised is zero, we assume it was not defaulted
1187		- * by the calling code so we set to advertise full capability.
1188		- */
1189		- if(hw->autoneg_advertised == 0)
1190		- hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
	1560	+ switch (phy_ms_setting) {
	1561	+ case e1000_ms_force_master:
	1562	+ phy_data \|= (CR_1000T_MS_ENABLE \| CR_1000T_MS_VALUE);
	1563	+ break;
	1564	+ case e1000_ms_force_slave:
	1565	+ phy_data \|= CR_1000T_MS_ENABLE;
	1566	+ phy_data &= ~(CR_1000T_MS_VALUE);
	1567	+ break;
	1568	+ case e1000_ms_auto:
	1569	+ phy_data &= ~CR_1000T_MS_ENABLE;
	1570	+ default:
	1571	+ break;
	1572	+ }
	1573	+ ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
	1574	+ if (ret_val)
	1575	+ return ret_val;
	1576	+ }
1191	1577
1192		- DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1193		- ret_val = e1000_phy_setup_autoneg(hw);
1194		- if(ret_val) {
1195		- DEBUGOUT("Error Setting up Auto-Negotiation\n");
1196		- return ret_val;
1197		- }
1198		- DEBUGOUT("Restarting Auto-Neg\n");
	1578	+ return E1000_SUCCESS;
	1579	+}
1199	1580
1200		- /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1201		- * the Auto Neg Restart bit in the PHY control register.
1202		- */
1203		- ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1204		- if(ret_val)
1205		- return ret_val;
	1581	+/********************************************************************
	1582	+* Copper link setup for e1000_phy_gg82563 series.
	1583	+*
	1584	+* hw - Struct containing variables accessed by shared code
	1585	+*********************************************************************/
	1586	+static int32_t
	1587	+e1000_copper_link_ggp_setup(struct e1000_hw *hw)
	1588	+{
	1589	+ int32_t ret_val;
	1590	+ uint16_t phy_data;
	1591	+ uint32_t reg_data;
1206	1592
1207		- phy_data \|= (MII_CR_AUTO_NEG_EN \| MII_CR_RESTART_AUTO_NEG);
1208		- ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1209		- if(ret_val)
1210		- return ret_val;
	1593	+ DEBUGFUNC("e1000_copper_link_ggp_setup");
1211	1594
1212		- /* Does the user want to wait for Auto-Neg to complete here, or
1213		- * check at a later time (for example, callback routine).
1214		- */
1215		- if(hw->wait_autoneg_complete) {
1216		- ret_val = e1000_wait_autoneg(hw);
1217		- if(ret_val) {
1218		- DEBUGOUT("Error while waiting for autoneg to complete\n");
1219		- return ret_val;
1220		- }
1221		- }
1222		- hw->get_link_status = TRUE;
1223		- } else {
1224		- DEBUGOUT("Forcing speed and duplex\n");
1225		- ret_val = e1000_phy_force_speed_duplex(hw);
1226		- if(ret_val) {
1227		- DEBUGOUT("Error Forcing Speed and Duplex\n");
1228		- return ret_val;
1229		- }
	1595	+ if (!hw->phy_reset_disable) {
	1596	+
	1597	+ /* Enable CRS on TX for half-duplex operation. */
	1598	+ ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
	1599	+ &phy_data);
	1600	+ if (ret_val)
	1601	+ return ret_val;
	1602	+
	1603	+ phy_data \|= GG82563_MSCR_ASSERT_CRS_ON_TX;
	1604	+ /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
	1605	+ phy_data \|= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
	1606	+
	1607	+ ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
	1608	+ phy_data);
	1609	+ if (ret_val)
	1610	+ return ret_val;
	1611	+
	1612	+ /* Options:
	1613	+ * MDI/MDI-X = 0 (default)
	1614	+ * 0 - Auto for all speeds
	1615	+ * 1 - MDI mode
	1616	+ * 2 - MDI-X mode
	1617	+ * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
	1618	+ */
	1619	+ ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
	1620	+ if (ret_val)
	1621	+ return ret_val;
	1622	+
	1623	+ phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
	1624	+
	1625	+ switch (hw->mdix) {
	1626	+ case 1:
	1627	+ phy_data \|= GG82563_PSCR_CROSSOVER_MODE_MDI;
	1628	+ break;
	1629	+ case 2:
	1630	+ phy_data \|= GG82563_PSCR_CROSSOVER_MODE_MDIX;
	1631	+ break;
	1632	+ case 0:
	1633	+ default:
	1634	+ phy_data \|= GG82563_PSCR_CROSSOVER_MODE_AUTO;
	1635	+ break;
1230	1636	}
1231		- } /* !hw->phy_reset_disable */
1232	1637
1233		- /* Check link status. Wait up to 100 microseconds for link to become
1234		- * valid.
1235		- */
1236		- for(i = 0; i < 10; i++) {
1237		- ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1238		- if(ret_val)
	1638	+ /* Options:
	1639	+ * disable_polarity_correction = 0 (default)
	1640	+ * Automatic Correction for Reversed Cable Polarity
	1641	+ * 0 - Disabled
	1642	+ * 1 - Enabled
	1643	+ */
	1644	+ phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
	1645	+ if (hw->disable_polarity_correction == 1)
	1646	+ phy_data \|= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
	1647	+ ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
	1648	+
	1649	+ if (ret_val)
1239	1650	return ret_val;
1240		- ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1241		- if(ret_val)
	1651	+
	1652	+ /* SW Reset the PHY so all changes take effect */
	1653	+ ret_val = e1000_phy_reset(hw);
	1654	+ if (ret_val) {
	1655	+ DEBUGOUT("Error Resetting the PHY\n");
	1656	+ return ret_val;
	1657	+ }
	1658	+ } /* phy_reset_disable */
	1659	+
	1660	+ if (hw->mac_type == e1000_80003es2lan) {
	1661	+ /* Bypass RX and TX FIFO's */
	1662	+ ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
	1663	+ E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS \|
	1664	+ E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
	1665	+ if (ret_val)
1242	1666	return ret_val;
1243	1667
1244		- if(phy_data & MII_SR_LINK_STATUS) {
1245		- /* We have link, so we need to finish the config process:
1246		- * 1) Set up the MAC to the current PHY speed/duplex
1247		- * if we are on 82543. If we
1248		- * are on newer silicon, we only need to configure
1249		- * collision distance in the Transmit Control Register.
1250		- * 2) Set up flow control on the MAC to that established with
1251		- * the link partner.
1252		- */
1253		- if(hw->mac_type >= e1000_82544) {
1254		- e1000_config_collision_dist(hw);
1255		- } else {
1256		- ret_val = e1000_config_mac_to_phy(hw);
1257		- if(ret_val) {
1258		- DEBUGOUT("Error configuring MAC to PHY settings\n");
1259		- return ret_val;
1260		- }
1261		- }
1262		- ret_val = e1000_config_fc_after_link_up(hw);
1263		- if(ret_val) {
1264		- DEBUGOUT("Error Configuring Flow Control\n");
	1668	+ ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
	1669	+ if (ret_val)
	1670	+ return ret_val;
	1671	+
	1672	+ phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
	1673	+ ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
	1674	+
	1675	+ if (ret_val)
	1676	+ return ret_val;
	1677	+
	1678	+ reg_data = E1000_READ_REG(hw, CTRL_EXT);
	1679	+ reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
	1680	+ E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
	1681	+
	1682	+ ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
	1683	+ &phy_data);
	1684	+ if (ret_val)
	1685	+ return ret_val;
	1686	+
	1687	+ /* Do not init these registers when the HW is in IAMT mode, since the
	1688	+ * firmware will have already initialized them. We only initialize
	1689	+ * them if the HW is not in IAMT mode.
	1690	+ */
	1691	+ if (e1000_check_mng_mode(hw) == FALSE) {
	1692	+ /* Enable Electrical Idle on the PHY */
	1693	+ phy_data \|= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
	1694	+ ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
	1695	+ phy_data);
	1696	+ if (ret_val)
1265	1697	return ret_val;
1266		- }
1267		- DEBUGOUT("Valid link established!!!\n");
1268	1698
1269		- if(hw->phy_type == e1000_phy_igp) {
1270		- ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
1271		- if(ret_val) {
1272		- DEBUGOUT("Error Configuring DSP after link up\n");
1273		- return ret_val;
1274		- }
1275		- }
1276		- DEBUGOUT("Valid link established!!!\n");
1277		- return E1000_SUCCESS;
	1699	+ ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
	1700	+ &phy_data);
	1701	+ if (ret_val)
	1702	+ return ret_val;
	1703	+
	1704	+ phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
	1705	+ ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
	1706	+ phy_data);
	1707	+
	1708	+ if (ret_val)
	1709	+ return ret_val;
1278	1710	}
1279		- udelay(10);
	1711	+
	1712	+ /* Workaround: Disable padding in Kumeran interface in the MAC
	1713	+ * and in the PHY to avoid CRC errors.
	1714	+ */
	1715	+ ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
	1716	+ &phy_data);
	1717	+ if (ret_val)
	1718	+ return ret_val;
	1719	+ phy_data \|= GG82563_ICR_DIS_PADDING;
	1720	+ ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
	1721	+ phy_data);
	1722	+ if (ret_val)
	1723	+ return ret_val;
1280	1724	}
1281	1725
1282		- DEBUGOUT("Unable to establish link!!!\n");
1283	1726	return E1000_SUCCESS;
1284	1727	}
1285	1728
1286		-/******************************************************************************
1287		-* Configures PHY autoneg and flow control advertisement settings
	1729	+/********************************************************************
	1730	+* Copper link setup for e1000_phy_m88 series.
1288	1731	*
1289	1732	* hw - Struct containing variables accessed by shared code
1290		-******************************************************************************/
1291		-int32_t
1292		-e1000_phy_setup_autoneg(struct e1000_hw *hw)
	1733	+*********************************************************************/
	1734	+static int32_t
	1735	+e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1293	1736	{
1294	1737	int32_t ret_val;
1295		- uint16_t mii_autoneg_adv_reg;
1296		- uint16_t mii_1000t_ctrl_reg;
	1738	+ uint16_t phy_data;
1297	1739
1298		- DEBUGFUNC("e1000_phy_setup_autoneg");
	1740	+ DEBUGFUNC("e1000_copper_link_mgp_setup");
1299	1741
1300		- /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1301		- ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1302		- if(ret_val)
1303		- return ret_val;
	1742	+ if (hw->phy_reset_disable)
	1743	+ return E1000_SUCCESS;
1304	1744
1305		- /* Read the MII 1000Base-T Control Register (Address 9). */
1306		- ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1307		- if(ret_val)
	1745	+ /* Enable CRS on TX. This must be set for half-duplex operation. */
	1746	+ ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
	1747	+ if (ret_val)
1308	1748	return ret_val;
1309	1749
1310		- /* Need to parse both autoneg_advertised and fc and set up
1311		- * the appropriate PHY registers. First we will parse for
1312		- * autoneg_advertised software override. Since we can advertise
1313		- * a plethora of combinations, we need to check each bit
1314		- * individually.
	1750	+ phy_data \|= M88E1000_PSCR_ASSERT_CRS_ON_TX;
	1751	+
	1752	+ /* Options:
	1753	+ * MDI/MDI-X = 0 (default)
	1754	+ * 0 - Auto for all speeds
	1755	+ * 1 - MDI mode
	1756	+ * 2 - MDI-X mode
	1757	+ * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1315	1758	*/
	1759	+ phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1316	1760
1317		- /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1318		- * Advertisement Register (Address 4) and the 1000 mb speed bits in
1319		- * the 1000Base-T Control Register (Address 9).
	1761	+ switch (hw->mdix) {
	1762	+ case 1:
	1763	+ phy_data \|= M88E1000_PSCR_MDI_MANUAL_MODE;
	1764	+ break;
	1765	+ case 2:
	1766	+ phy_data \|= M88E1000_PSCR_MDIX_MANUAL_MODE;
	1767	+ break;
	1768	+ case 3:
	1769	+ phy_data \|= M88E1000_PSCR_AUTO_X_1000T;
	1770	+ break;
	1771	+ case 0:
	1772	+ default:
	1773	+ phy_data \|= M88E1000_PSCR_AUTO_X_MODE;
	1774	+ break;
	1775	+ }
	1776	+
	1777	+ /* Options:
	1778	+ * disable_polarity_correction = 0 (default)
	1779	+ * Automatic Correction for Reversed Cable Polarity
	1780	+ * 0 - Disabled
	1781	+ * 1 - Enabled
1320	1782	*/
1321		- mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1322		- mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
	1783	+ phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
	1784	+ if (hw->disable_polarity_correction == 1)
	1785	+ phy_data \|= M88E1000_PSCR_POLARITY_REVERSAL;
	1786	+ ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
	1787	+ if (ret_val)
	1788	+ return ret_val;
1323	1789
1324		- DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
	1790	+ if (hw->phy_revision < M88E1011_I_REV_4) {
	1791	+ /* Force TX_CLK in the Extended PHY Specific Control Register
	1792	+ * to 25MHz clock.
	1793	+ */
	1794	+ ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
	1795	+ if (ret_val)
	1796	+ return ret_val;
1325	1797
1326		- /* Do we want to advertise 10 Mb Half Duplex? */
1327		- if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
1328		- DEBUGOUT("Advertise 10mb Half duplex\n");
1329		- mii_autoneg_adv_reg \|= NWAY_AR_10T_HD_CAPS;
1330		- }
	1798	+ phy_data \|= M88E1000_EPSCR_TX_CLK_25;
1331	1799
1332		- /* Do we want to advertise 10 Mb Full Duplex? */
1333		- if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
1334		- DEBUGOUT("Advertise 10mb Full duplex\n");
1335		- mii_autoneg_adv_reg \|= NWAY_AR_10T_FD_CAPS;
	1800	+ if ((hw->phy_revision == E1000_REVISION_2) &&
	1801	+ (hw->phy_id == M88E1111_I_PHY_ID)) {
	1802	+ /* Vidalia Phy, set the downshift counter to 5x */
	1803	+ phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
	1804	+ phy_data \|= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
	1805	+ ret_val = e1000_write_phy_reg(hw,
	1806	+ M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
	1807	+ if (ret_val)
	1808	+ return ret_val;
	1809	+ } else {
	1810	+ /* Configure Master and Slave downshift values */
	1811	+ phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK \|
	1812	+ M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
	1813	+ phy_data \|= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X \|
	1814	+ M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
	1815	+ ret_val = e1000_write_phy_reg(hw,
	1816	+ M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
	1817	+ if (ret_val)
	1818	+ return ret_val;
	1819	+ }
1336	1820	}
1337	1821
1338		- /* Do we want to advertise 100 Mb Half Duplex? */
1339		- if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
1340		- DEBUGOUT("Advertise 100mb Half duplex\n");
1341		- mii_autoneg_adv_reg \|= NWAY_AR_100TX_HD_CAPS;
	1822	+ /* SW Reset the PHY so all changes take effect */
	1823	+ ret_val = e1000_phy_reset(hw);
	1824	+ if (ret_val) {
	1825	+ DEBUGOUT("Error Resetting the PHY\n");
	1826	+ return ret_val;
1342	1827	}
1343	1828
1344		- /* Do we want to advertise 100 Mb Full Duplex? */
1345		- if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
1346		- DEBUGOUT("Advertise 100mb Full duplex\n");
1347		- mii_autoneg_adv_reg \|= NWAY_AR_100TX_FD_CAPS;
1348		- }
	1829	+ return E1000_SUCCESS;
	1830	+}
1349	1831
1350		- /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1351		- if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1352		- DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
1353		- }
	1832	+/********************************************************************
	1833	+* Setup auto-negotiation and flow control advertisements,
	1834	+* and then perform auto-negotiation.
	1835	+*
	1836	+* hw - Struct containing variables accessed by shared code
	1837	+*********************************************************************/
	1838	+static int32_t
	1839	+e1000_copper_link_autoneg(struct e1000_hw *hw)
	1840	+{
	1841	+ int32_t ret_val;
	1842	+ uint16_t phy_data;
1354	1843
1355		- /* Do we want to advertise 1000 Mb Full Duplex? */
1356		- if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1357		- DEBUGOUT("Advertise 1000mb Full duplex\n");
1358		- mii_1000t_ctrl_reg \|= CR_1000T_FD_CAPS;
1359		- }
	1844	+ DEBUGFUNC("e1000_copper_link_autoneg");
1360	1845
1361		- /* Check for a software override of the flow control settings, and
1362		- * setup the PHY advertisement registers accordingly. If
1363		- * auto-negotiation is enabled, then software will have to set the
1364		- * "PAUSE" bits to the correct value in the Auto-Negotiation
1365		- * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1366		- *
1367		- * The possible values of the "fc" parameter are:
1368		- * 0: Flow control is completely disabled
1369		- * 1: Rx flow control is enabled (we can receive pause frames
1370		- * but not send pause frames).
1371		- * 2: Tx flow control is enabled (we can send pause frames
1372		- * but we do not support receiving pause frames).
1373		- * 3: Both Rx and TX flow control (symmetric) are enabled.
1374		- * other: No software override. The flow control configuration
1375		- * in the EEPROM is used.
	1846	+ /* Perform some bounds checking on the hw->autoneg_advertised
	1847	+ * parameter. If this variable is zero, then set it to the default.
1376	1848	*/
1377		- switch (hw->fc) {
1378		- case e1000_fc_none: /* 0 */
1379		- /* Flow control (RX & TX) is completely disabled by a
1380		- * software over-ride.
1381		- */
1382		- mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR \| NWAY_AR_PAUSE);
1383		- break;
1384		- case e1000_fc_rx_pause: /* 1 */
1385		- /* RX Flow control is enabled, and TX Flow control is
1386		- * disabled, by a software over-ride.
1387		- */
1388		- /* Since there really isn't a way to advertise that we are
1389		- * capable of RX Pause ONLY, we will advertise that we
1390		- * support both symmetric and asymmetric RX PAUSE. Later
1391		- * (in e1000_config_fc_after_link_up) we will disable the
1392		- *hw's ability to send PAUSE frames.
1393		- */
1394		- mii_autoneg_adv_reg \|= (NWAY_AR_ASM_DIR \| NWAY_AR_PAUSE);
1395		- break;
1396		- case e1000_fc_tx_pause: /* 2 */
1397		- /* TX Flow control is enabled, and RX Flow control is
1398		- * disabled, by a software over-ride.
1399		- */
1400		- mii_autoneg_adv_reg \|= NWAY_AR_ASM_DIR;
1401		- mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1402		- break;
1403		- case e1000_fc_full: /* 3 */
1404		- /* Flow control (both RX and TX) is enabled by a software
1405		- * over-ride.
1406		- */
1407		- mii_autoneg_adv_reg \|= (NWAY_AR_ASM_DIR \| NWAY_AR_PAUSE);
1408		- break;
1409		- default:
1410		- DEBUGOUT("Flow control param set incorrectly\n");
1411		- return -E1000_ERR_CONFIG;
1412		- }
	1849	+ hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1413	1850
1414		- ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1415		- if(ret_val)
	1851	+ /* If autoneg_advertised is zero, we assume it was not defaulted
	1852	+ * by the calling code so we set to advertise full capability.
	1853	+ */
	1854	+ if (hw->autoneg_advertised == 0)
	1855	+ hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
	1856	+
	1857	+ /* IFE phy only supports 10/100 */
	1858	+ if (hw->phy_type == e1000_phy_ife)
	1859	+ hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
	1860	+
	1861	+ DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
	1862	+ ret_val = e1000_phy_setup_autoneg(hw);
	1863	+ if (ret_val) {
	1864	+ DEBUGOUT("Error Setting up Auto-Negotiation\n");
1416	1865	return ret_val;
	1866	+ }
	1867	+ DEBUGOUT("Restarting Auto-Neg\n");
1417	1868
1418		- DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
	1869	+ /* Restart auto-negotiation by setting the Auto Neg Enable bit and
	1870	+ * the Auto Neg Restart bit in the PHY control register.
	1871	+ */
	1872	+ ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
	1873	+ if (ret_val)
	1874	+ return ret_val;
1419	1875
1420		- ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
1421		-
1422		- if(ret_val)
	1876	+ phy_data \|= (MII_CR_AUTO_NEG_EN \| MII_CR_RESTART_AUTO_NEG);
	1877	+ ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
	1878	+ if (ret_val)
1423	1879	return ret_val;
1424	1880
	1881	+ /* Does the user want to wait for Auto-Neg to complete here, or
	1882	+ * check at a later time (for example, callback routine).
	1883	+ */
	1884	+ if (hw->wait_autoneg_complete) {
	1885	+ ret_val = e1000_wait_autoneg(hw);
	1886	+ if (ret_val) {
	1887	+ DEBUGOUT("Error while waiting for autoneg to complete\n");
	1888	+ return ret_val;
	1889	+ }
	1890	+ }
	1891	+
	1892	+ hw->get_link_status = TRUE;
	1893	+
1425	1894	return E1000_SUCCESS;
1426	1895	}
1427	1896
1428	1897	/******************************************************************************
1429		-* Force PHY speed and duplex settings to hw->forced_speed_duplex
	1898	+* Config the MAC and the PHY after link is up.
	1899	+* 1) Set up the MAC to the current PHY speed/duplex
	1900	+* if we are on 82543. If we
	1901	+* are on newer silicon, we only need to configure
	1902	+* collision distance in the Transmit Control Register.
	1903	+* 2) Set up flow control on the MAC to that established with
	1904	+* the link partner.
	1905	+* 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1430	1906	*
1431	1907	* hw - Struct containing variables accessed by shared code
1432	1908	******************************************************************************/
1433	1909	static int32_t
1434		-e1000_phy_force_speed_duplex(struct e1000_hw *hw)
	1910	+e1000_copper_link_postconfig(struct e1000_hw *hw)
1435	1911	{
1436		- uint32_t ctrl;
1437	1912	int32_t ret_val;
1438		- uint16_t mii_ctrl_reg;
1439		- uint16_t mii_status_reg;
1440		- uint16_t phy_data;
1441		- uint16_t i;
	1913	+ DEBUGFUNC("e1000_copper_link_postconfig");
1442	1914
1443		- DEBUGFUNC("e1000_phy_force_speed_duplex");
	1915	+ if (hw->mac_type >= e1000_82544) {
	1916	+ e1000_config_collision_dist(hw);
	1917	+ } else {
	1918	+ ret_val = e1000_config_mac_to_phy(hw);
	1919	+ if (ret_val) {
	1920	+ DEBUGOUT("Error configuring MAC to PHY settings\n");
	1921	+ return ret_val;
	1922	+ }
	1923	+ }
	1924	+ ret_val = e1000_config_fc_after_link_up(hw);
	1925	+ if (ret_val) {
	1926	+ DEBUGOUT("Error Configuring Flow Control\n");
	1927	+ return ret_val;
	1928	+ }
1444	1929
1445		- /* Turn off Flow control if we are forcing speed and duplex. */
1446		- hw->fc = e1000_fc_none;
	1930	+ /* Config DSP to improve Giga link quality */
	1931	+ if (hw->phy_type == e1000_phy_igp) {
	1932	+ ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
	1933	+ if (ret_val) {
	1934	+ DEBUGOUT("Error Configuring DSP after link up\n");
	1935	+ return ret_val;
	1936	+ }
	1937	+ }
1447	1938
1448		- DEBUGOUT1("hw->fc = %d\n", hw->fc);
	1939	+ return E1000_SUCCESS;
	1940	+}
1449	1941
1450		- /* Read the Device Control Register. */
1451		- ctrl = E1000_READ_REG(hw, CTRL);
	1942	+/******************************************************************************
	1943	+* Detects which PHY is present and setup the speed and duplex
	1944	+*
	1945	+* hw - Struct containing variables accessed by shared code
	1946	+******************************************************************************/
	1947	+static int32_t
	1948	+e1000_setup_copper_link(struct e1000_hw *hw)
	1949	+{
	1950	+ int32_t ret_val;
	1951	+ uint16_t i;
	1952	+ uint16_t phy_data;
	1953	+ uint16_t reg_data;
1452	1954
1453		- /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
1454		- ctrl \|= (E1000_CTRL_FRCSPD \| E1000_CTRL_FRCDPX);
1455		- ctrl &= ~(DEVICE_SPEED_MASK);
	1955	+ DEBUGFUNC("e1000_setup_copper_link");
	1956	+
	1957	+ switch (hw->mac_type) {
	1958	+ case e1000_80003es2lan:
	1959	+ case e1000_ich8lan:
	1960	+ /* Set the mac to wait the maximum time between each
	1961	+ * iteration and increase the max iterations when
	1962	+ * polling the phy; this fixes erroneous timeouts at 10Mbps. */
	1963	+ ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
	1964	+ if (ret_val)
	1965	+ return ret_val;
	1966	+ ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
	1967	+ if (ret_val)
	1968	+ return ret_val;
	1969	+ reg_data \|= 0x3F;
	1970	+ ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
	1971	+ if (ret_val)
	1972	+ return ret_val;
	1973	+ default:
	1974	+ break;
	1975	+ }
	1976	+
	1977	+ /* Check if it is a valid PHY and set PHY mode if necessary. */
	1978	+ ret_val = e1000_copper_link_preconfig(hw);
	1979	+ if (ret_val)
	1980	+ return ret_val;
	1981	+
	1982	+ switch (hw->mac_type) {
	1983	+ case e1000_80003es2lan:
	1984	+ /* Kumeran registers are written-only */
	1985	+ reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
	1986	+ reg_data \|= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
	1987	+ ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
	1988	+ reg_data);
	1989	+ if (ret_val)
	1990	+ return ret_val;
	1991	+ break;
	1992	+ default:
	1993	+ break;
	1994	+ }
	1995	+
	1996	+ if (hw->phy_type == e1000_phy_igp \|\|
	1997	+ hw->phy_type == e1000_phy_igp_3 \|\|
	1998	+ hw->phy_type == e1000_phy_igp_2) {
	1999	+ ret_val = e1000_copper_link_igp_setup(hw);
	2000	+ if (ret_val)
	2001	+ return ret_val;
	2002	+ } else if (hw->phy_type == e1000_phy_m88) {
	2003	+ ret_val = e1000_copper_link_mgp_setup(hw);
	2004	+ if (ret_val)
	2005	+ return ret_val;
	2006	+ } else if (hw->phy_type == e1000_phy_gg82563) {
	2007	+ ret_val = e1000_copper_link_ggp_setup(hw);
	2008	+ if (ret_val)
	2009	+ return ret_val;
	2010	+ }
	2011	+
	2012	+ if (hw->autoneg) {
	2013	+ /* Setup autoneg and flow control advertisement
	2014	+ * and perform autonegotiation */
	2015	+ ret_val = e1000_copper_link_autoneg(hw);
	2016	+ if (ret_val)
	2017	+ return ret_val;
	2018	+ } else {
	2019	+ /* PHY will be set to 10H, 10F, 100H,or 100F
	2020	+ * depending on value from forced_speed_duplex. */
	2021	+ DEBUGOUT("Forcing speed and duplex\n");
	2022	+ ret_val = e1000_phy_force_speed_duplex(hw);
	2023	+ if (ret_val) {
	2024	+ DEBUGOUT("Error Forcing Speed and Duplex\n");
	2025	+ return ret_val;
	2026	+ }
	2027	+ }
	2028	+
	2029	+ /* Check link status. Wait up to 100 microseconds for link to become
	2030	+ * valid.
	2031	+ */
	2032	+ for (i = 0; i < 10; i++) {
	2033	+ ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
	2034	+ if (ret_val)
	2035	+ return ret_val;
	2036	+ ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
	2037	+ if (ret_val)
	2038	+ return ret_val;
	2039	+
	2040	+ if (phy_data & MII_SR_LINK_STATUS) {
	2041	+ /* Config the MAC and PHY after link is up */
	2042	+ ret_val = e1000_copper_link_postconfig(hw);
	2043	+ if (ret_val)
	2044	+ return ret_val;
	2045	+
	2046	+ DEBUGOUT("Valid link established!!!\n");
	2047	+ return E1000_SUCCESS;
	2048	+ }
	2049	+ usec_delay(10);
	2050	+ }
	2051	+
	2052	+ DEBUGOUT("Unable to establish link!!!\n");
	2053	+ return E1000_SUCCESS;
	2054	+}
	2055	+
	2056	+/******************************************************************************
	2057	+* Configure the MAC-to-PHY interface for 10/100Mbps
	2058	+*
	2059	+* hw - Struct containing variables accessed by shared code
	2060	+******************************************************************************/
	2061	+static int32_t
	2062	+e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
	2063	+{
	2064	+ int32_t ret_val = E1000_SUCCESS;
	2065	+ uint32_t tipg;
	2066	+ uint16_t reg_data;
	2067	+
	2068	+ DEBUGFUNC("e1000_configure_kmrn_for_10_100");
	2069	+
	2070	+ reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
	2071	+ ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
	2072	+ reg_data);
	2073	+ if (ret_val)
	2074	+ return ret_val;
	2075	+
	2076	+ /* Configure Transmit Inter-Packet Gap */
	2077	+ tipg = E1000_READ_REG(hw, TIPG);
	2078	+ tipg &= ~E1000_TIPG_IPGT_MASK;
	2079	+ tipg \|= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
	2080	+ E1000_WRITE_REG(hw, TIPG, tipg);
	2081	+
	2082	+ ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
	2083	+
	2084	+ if (ret_val)
	2085	+ return ret_val;
	2086	+
	2087	+ if (duplex == HALF_DUPLEX)
	2088	+ reg_data \|= GG82563_KMCR_PASS_FALSE_CARRIER;
	2089	+ else
	2090	+ reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
	2091	+
	2092	+ ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
	2093	+
	2094	+ return ret_val;
	2095	+}
	2096	+
	2097	+static int32_t
	2098	+e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
	2099	+{
	2100	+ int32_t ret_val = E1000_SUCCESS;
	2101	+ uint16_t reg_data;
	2102	+ uint32_t tipg;
	2103	+
	2104	+ DEBUGFUNC("e1000_configure_kmrn_for_1000");
	2105	+
	2106	+ reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
	2107	+ ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
	2108	+ reg_data);
	2109	+ if (ret_val)
	2110	+ return ret_val;
	2111	+
	2112	+ /* Configure Transmit Inter-Packet Gap */
	2113	+ tipg = E1000_READ_REG(hw, TIPG);
	2114	+ tipg &= ~E1000_TIPG_IPGT_MASK;
	2115	+ tipg \|= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
	2116	+ E1000_WRITE_REG(hw, TIPG, tipg);
	2117	+
	2118	+ ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
	2119	+
	2120	+ if (ret_val)
	2121	+ return ret_val;
	2122	+
	2123	+ reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
	2124	+ ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
	2125	+
	2126	+ return ret_val;
	2127	+}
	2128	+
	2129	+/******************************************************************************
	2130	+* Configures PHY autoneg and flow control advertisement settings
	2131	+*
	2132	+* hw - Struct containing variables accessed by shared code
	2133	+******************************************************************************/
	2134	+int32_t
	2135	+e1000_phy_setup_autoneg(struct e1000_hw *hw)
	2136	+{
	2137	+ int32_t ret_val;
	2138	+ uint16_t mii_autoneg_adv_reg;
	2139	+ uint16_t mii_1000t_ctrl_reg;
	2140	+
	2141	+ DEBUGFUNC("e1000_phy_setup_autoneg");
	2142	+
	2143	+ /* Read the MII Auto-Neg Advertisement Register (Address 4). */
	2144	+ ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
	2145	+ if (ret_val)
	2146	+ return ret_val;
	2147	+
	2148	+ if (hw->phy_type != e1000_phy_ife) {
	2149	+ /* Read the MII 1000Base-T Control Register (Address 9). */
	2150	+ ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
	2151	+ if (ret_val)
	2152	+ return ret_val;
	2153	+ } else
	2154	+ mii_1000t_ctrl_reg=0;
	2155	+
	2156	+ /* Need to parse both autoneg_advertised and fc and set up
	2157	+ * the appropriate PHY registers. First we will parse for
	2158	+ * autoneg_advertised software override. Since we can advertise
	2159	+ * a plethora of combinations, we need to check each bit
	2160	+ * individually.
	2161	+ */
	2162	+
	2163	+ /* First we clear all the 10/100 mb speed bits in the Auto-Neg
	2164	+ * Advertisement Register (Address 4) and the 1000 mb speed bits in
	2165	+ * the 1000Base-T Control Register (Address 9).
	2166	+ */
	2167	+ mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
	2168	+ mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
	2169	+
	2170	+ DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
	2171	+
	2172	+ /* Do we want to advertise 10 Mb Half Duplex? */
	2173	+ if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
	2174	+ DEBUGOUT("Advertise 10mb Half duplex\n");
	2175	+ mii_autoneg_adv_reg \|= NWAY_AR_10T_HD_CAPS;
	2176	+ }
	2177	+
	2178	+ /* Do we want to advertise 10 Mb Full Duplex? */
	2179	+ if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
	2180	+ DEBUGOUT("Advertise 10mb Full duplex\n");
	2181	+ mii_autoneg_adv_reg \|= NWAY_AR_10T_FD_CAPS;
	2182	+ }
	2183	+
	2184	+ /* Do we want to advertise 100 Mb Half Duplex? */
	2185	+ if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
	2186	+ DEBUGOUT("Advertise 100mb Half duplex\n");
	2187	+ mii_autoneg_adv_reg \|= NWAY_AR_100TX_HD_CAPS;
	2188	+ }
	2189	+
	2190	+ /* Do we want to advertise 100 Mb Full Duplex? */
	2191	+ if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
	2192	+ DEBUGOUT("Advertise 100mb Full duplex\n");
	2193	+ mii_autoneg_adv_reg \|= NWAY_AR_100TX_FD_CAPS;
	2194	+ }
	2195	+
	2196	+ /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
	2197	+ if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
	2198	+ DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
	2199	+ }
	2200	+
	2201	+ /* Do we want to advertise 1000 Mb Full Duplex? */
	2202	+ if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
	2203	+ DEBUGOUT("Advertise 1000mb Full duplex\n");
	2204	+ mii_1000t_ctrl_reg \|= CR_1000T_FD_CAPS;
	2205	+ if (hw->phy_type == e1000_phy_ife) {
	2206	+ DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n");
	2207	+ }
	2208	+ }
	2209	+
	2210	+ /* Check for a software override of the flow control settings, and
	2211	+ * setup the PHY advertisement registers accordingly. If
	2212	+ * auto-negotiation is enabled, then software will have to set the
	2213	+ * "PAUSE" bits to the correct value in the Auto-Negotiation
	2214	+ * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
	2215	+ *
	2216	+ * The possible values of the "fc" parameter are:
	2217	+ * 0: Flow control is completely disabled
	2218	+ * 1: Rx flow control is enabled (we can receive pause frames
	2219	+ * but not send pause frames).
	2220	+ * 2: Tx flow control is enabled (we can send pause frames
	2221	+ * but we do not support receiving pause frames).
	2222	+ * 3: Both Rx and TX flow control (symmetric) are enabled.
	2223	+ * other: No software override. The flow control configuration
	2224	+ * in the EEPROM is used.
	2225	+ */
	2226	+ switch (hw->fc) {
	2227	+ case E1000_FC_NONE: /* 0 */
	2228	+ /* Flow control (RX & TX) is completely disabled by a
	2229	+ * software over-ride.
	2230	+ */
	2231	+ mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR \| NWAY_AR_PAUSE);
	2232	+ break;
	2233	+ case E1000_FC_RX_PAUSE: /* 1 */
	2234	+ /* RX Flow control is enabled, and TX Flow control is
	2235	+ * disabled, by a software over-ride.
	2236	+ */
	2237	+ /* Since there really isn't a way to advertise that we are
	2238	+ * capable of RX Pause ONLY, we will advertise that we
	2239	+ * support both symmetric and asymmetric RX PAUSE. Later
	2240	+ * (in e1000_config_fc_after_link_up) we will disable the
	2241	+ *hw's ability to send PAUSE frames.
	2242	+ */
	2243	+ mii_autoneg_adv_reg \|= (NWAY_AR_ASM_DIR \| NWAY_AR_PAUSE);
	2244	+ break;
	2245	+ case E1000_FC_TX_PAUSE: /* 2 */
	2246	+ /* TX Flow control is enabled, and RX Flow control is
	2247	+ * disabled, by a software over-ride.
	2248	+ */
	2249	+ mii_autoneg_adv_reg \|= NWAY_AR_ASM_DIR;
	2250	+ mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
	2251	+ break;
	2252	+ case E1000_FC_FULL: /* 3 */
	2253	+ /* Flow control (both RX and TX) is enabled by a software
	2254	+ * over-ride.
	2255	+ */
	2256	+ mii_autoneg_adv_reg \|= (NWAY_AR_ASM_DIR \| NWAY_AR_PAUSE);
	2257	+ break;
	2258	+ default:
	2259	+ DEBUGOUT("Flow control param set incorrectly\n");
	2260	+ return -E1000_ERR_CONFIG;
	2261	+ }
	2262	+
	2263	+ ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
	2264	+ if (ret_val)
	2265	+ return ret_val;
	2266	+
	2267	+ DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
	2268	+
	2269	+ if (hw->phy_type != e1000_phy_ife) {
	2270	+ ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
	2271	+ if (ret_val)
	2272	+ return ret_val;
	2273	+ }
	2274	+
	2275	+ return E1000_SUCCESS;
	2276	+}
	2277	+
	2278	+/******************************************************************************
	2279	+* Force PHY speed and duplex settings to hw->forced_speed_duplex
	2280	+*
	2281	+* hw - Struct containing variables accessed by shared code
	2282	+******************************************************************************/
	2283	+static int32_t
	2284	+e1000_phy_force_speed_duplex(struct e1000_hw *hw)
	2285	+{
	2286	+ uint32_t ctrl;
	2287	+ int32_t ret_val;
	2288	+ uint16_t mii_ctrl_reg;
	2289	+ uint16_t mii_status_reg;
	2290	+ uint16_t phy_data;
	2291	+ uint16_t i;
	2292	+
	2293	+ DEBUGFUNC("e1000_phy_force_speed_duplex");
	2294	+
	2295	+ /* Turn off Flow control if we are forcing speed and duplex. */
	2296	+ hw->fc = E1000_FC_NONE;
	2297	+
	2298	+ DEBUGOUT1("hw->fc = %d\n", hw->fc);
	2299	+
	2300	+ /* Read the Device Control Register. */
	2301	+ ctrl = E1000_READ_REG(hw, CTRL);
	2302	+
	2303	+ /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
	2304	+ ctrl \|= (E1000_CTRL_FRCSPD \| E1000_CTRL_FRCDPX);
	2305	+ ctrl &= ~(DEVICE_SPEED_MASK);
1456	2306
1457	2307	/* Clear the Auto Speed Detect Enable bit. */
1458	2308	ctrl &= ~E1000_CTRL_ASDE;
1459	2309
1460	2310	/* Read the MII Control Register. */
1461	2311	ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
1462		- if(ret_val)
	2312	+ if (ret_val)
1463	2313	return ret_val;
1464	2314
1465	2315	/* We need to disable autoneg in order to force link and duplex. */

		@@ -1467,8 +2317,8 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1467	2317	mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
1468	2318
1469	2319	/* Are we forcing Full or Half Duplex? */
1470		- if(hw->forced_speed_duplex == e1000_100_full \|\|
1471		- hw->forced_speed_duplex == e1000_10_full) {
	2320	+ if (hw->forced_speed_duplex == e1000_100_full \|\|
	2321	+ hw->forced_speed_duplex == e1000_10_full) {
1472	2322	/* We want to force full duplex so we SET the full duplex bits in the
1473	2323	* Device and MII Control Registers.
1474	2324	*/

		@@ -1485,7 +2335,7 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1485	2335	}
1486	2336
1487	2337	/* Are we forcing 100Mbps??? */
1488		- if(hw->forced_speed_duplex == e1000_100_full \|\|
	2338	+ if (hw->forced_speed_duplex == e1000_100_full \|\|
1489	2339	hw->forced_speed_duplex == e1000_100_half) {
1490	2340	/* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
1491	2341	ctrl \|= E1000_CTRL_SPD_100;

		@@ -1505,9 +2355,10 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1505	2355	/* Write the configured values back to the Device Control Reg. */
1506	2356	E1000_WRITE_REG(hw, CTRL, ctrl);
1507	2357
1508		- if (hw->phy_type == e1000_phy_m88) {
	2358	+ if ((hw->phy_type == e1000_phy_m88) \|\|
	2359	+ (hw->phy_type == e1000_phy_gg82563)) {
1509	2360	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1510		- if(ret_val)
	2361	+ if (ret_val)
1511	2362	return ret_val;
1512	2363
1513	2364	/* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI

		@@ -1515,35 +2366,49 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1515	2366	*/
1516	2367	phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1517	2368	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1518		- if(ret_val)
	2369	+ if (ret_val)
1519	2370	return ret_val;
1520	2371
1521	2372	DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
1522	2373
1523	2374	/* Need to reset the PHY or these changes will be ignored */
1524	2375	mii_ctrl_reg \|= MII_CR_RESET;
	2376	+
	2377	+ /* Disable MDI-X support for 10/100 */
	2378	+ } else if (hw->phy_type == e1000_phy_ife) {
	2379	+ ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
	2380	+ if (ret_val)
	2381	+ return ret_val;
	2382	+
	2383	+ phy_data &= ~IFE_PMC_AUTO_MDIX;
	2384	+ phy_data &= ~IFE_PMC_FORCE_MDIX;
	2385	+
	2386	+ ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
	2387	+ if (ret_val)
	2388	+ return ret_val;
	2389	+
1525	2390	} else {
1526	2391	/* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1527	2392	* forced whenever speed or duplex are forced.
1528	2393	*/
1529	2394	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1530		- if(ret_val)
	2395	+ if (ret_val)
1531	2396	return ret_val;
1532	2397
1533	2398	phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1534	2399	phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1535	2400
1536	2401	ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1537		- if(ret_val)
	2402	+ if (ret_val)
1538	2403	return ret_val;
1539	2404	}
1540	2405
1541	2406	/* Write back the modified PHY MII control register. */
1542	2407	ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
1543		- if(ret_val)
	2408	+ if (ret_val)
1544	2409	return ret_val;
1545	2410
1546		- udelay(1);
	2411	+ usec_delay(1);
1547	2412
1548	2413	/* The wait_autoneg_complete flag may be a little misleading here.
1549	2414	* Since we are forcing speed and duplex, Auto-Neg is not enabled.

		@@ -1552,49 +2417,50 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1552	2417	* only if the user has set wait_autoneg_complete to 1, which is
1553	2418	* the default.
1554	2419	*/
1555		- if(hw->wait_autoneg_complete) {
	2420	+ if (hw->wait_autoneg_complete) {
1556	2421	/* We will wait for autoneg to complete. */
1557	2422	DEBUGOUT("Waiting for forced speed/duplex link.\n");
1558	2423	mii_status_reg = 0;
1559	2424
1560	2425	/* We will wait for autoneg to complete or 4.5 seconds to expire. */
1561		- for(i = PHY_FORCE_TIME; i > 0; i--) {
	2426	+ for (i = PHY_FORCE_TIME; i > 0; i--) {
1562	2427	/* Read the MII Status Register and wait for Auto-Neg Complete bit
1563	2428	* to be set.
1564	2429	*/
1565	2430	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1566		- if(ret_val)
	2431	+ if (ret_val)
1567	2432	return ret_val;
1568	2433
1569	2434	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1570		- if(ret_val)
	2435	+ if (ret_val)
1571	2436	return ret_val;
1572	2437
1573		- if(mii_status_reg & MII_SR_LINK_STATUS) break;
	2438	+ if (mii_status_reg & MII_SR_LINK_STATUS) break;
1574	2439	msec_delay(100);
1575	2440	}
1576		- if((i == 0) &&
1577		- (hw->phy_type == e1000_phy_m88)) {
	2441	+ if ((i == 0) &&
	2442	+ ((hw->phy_type == e1000_phy_m88) \|\|
	2443	+ (hw->phy_type == e1000_phy_gg82563))) {
1578	2444	/* We didn't get link. Reset the DSP and wait again for link. */
1579	2445	ret_val = e1000_phy_reset_dsp(hw);
1580		- if(ret_val) {
	2446	+ if (ret_val) {
1581	2447	DEBUGOUT("Error Resetting PHY DSP\n");
1582	2448	return ret_val;
1583	2449	}
1584	2450	}
1585	2451	/* This loop will early-out if the link condition has been met. */
1586		- for(i = PHY_FORCE_TIME; i > 0; i--) {
1587		- if(mii_status_reg & MII_SR_LINK_STATUS) break;
	2452	+ for (i = PHY_FORCE_TIME; i > 0; i--) {
	2453	+ if (mii_status_reg & MII_SR_LINK_STATUS) break;
1588	2454	msec_delay(100);
1589	2455	/* Read the MII Status Register and wait for Auto-Neg Complete bit
1590	2456	* to be set.
1591	2457	*/
1592	2458	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1593		- if(ret_val)
	2459	+ if (ret_val)
1594	2460	return ret_val;
1595	2461
1596	2462	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1597		- if(ret_val)
	2463	+ if (ret_val)
1598	2464	return ret_val;
1599	2465	}
1600	2466	}

		@@ -1605,34 +2471,54 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1605	2471	* defaults back to a 2.5MHz clock when the PHY is reset.
1606	2472	*/
1607	2473	ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1608		- if(ret_val)
	2474	+ if (ret_val)
1609	2475	return ret_val;
1610	2476
1611	2477	phy_data \|= M88E1000_EPSCR_TX_CLK_25;
1612	2478	ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1613		- if(ret_val)
	2479	+ if (ret_val)
1614	2480	return ret_val;
1615	2481
1616	2482	/* In addition, because of the s/w reset above, we need to enable CRS on
1617	2483	* TX. This must be set for both full and half duplex operation.
1618	2484	*/
1619	2485	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1620		- if(ret_val)
	2486	+ if (ret_val)
1621	2487	return ret_val;
1622	2488
1623	2489	phy_data \|= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1624	2490	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1625		- if(ret_val)
	2491	+ if (ret_val)
1626	2492	return ret_val;
1627	2493
1628		- if((hw->mac_type == e1000_82544 \|\| hw->mac_type == e1000_82543) &&
1629		- (!hw->autoneg) &&
1630		- (hw->forced_speed_duplex == e1000_10_full \|\|
1631		- hw->forced_speed_duplex == e1000_10_half)) {
	2494	+ if ((hw->mac_type == e1000_82544 \|\| hw->mac_type == e1000_82543) &&
	2495	+ (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full \|\|
	2496	+ hw->forced_speed_duplex == e1000_10_half)) {
1632	2497	ret_val = e1000_polarity_reversal_workaround(hw);
1633		- if(ret_val)
	2498	+ if (ret_val)
1634	2499	return ret_val;
1635	2500	}
	2501	+ } else if (hw->phy_type == e1000_phy_gg82563) {
	2502	+ /* The TX_CLK of the Extended PHY Specific Control Register defaults
	2503	+ * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if
	2504	+ * we're not in a forced 10/duplex configuration. */
	2505	+ ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
	2506	+ if (ret_val)
	2507	+ return ret_val;
	2508	+
	2509	+ phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
	2510	+ if ((hw->forced_speed_duplex == e1000_10_full) \|\|
	2511	+ (hw->forced_speed_duplex == e1000_10_half))
	2512	+ phy_data \|= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
	2513	+ else
	2514	+ phy_data \|= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
	2515	+
	2516	+ /* Also due to the reset, we need to enable CRS on Tx. */
	2517	+ phy_data \|= GG82563_MSCR_ASSERT_CRS_ON_TX;
	2518	+
	2519	+ ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
	2520	+ if (ret_val)
	2521	+ return ret_val;
1636	2522	}
1637	2523	return E1000_SUCCESS;
1638	2524	}

		@@ -1648,14 +2534,19 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1648	2534	void
1649	2535	e1000_config_collision_dist(struct e1000_hw *hw)
1650	2536	{
1651		- uint32_t tctl;
	2537	+ uint32_t tctl, coll_dist;
1652	2538
1653	2539	DEBUGFUNC("e1000_config_collision_dist");
1654	2540
	2541	+ if (hw->mac_type < e1000_82543)
	2542	+ coll_dist = E1000_COLLISION_DISTANCE_82542;
	2543	+ else
	2544	+ coll_dist = E1000_COLLISION_DISTANCE;
	2545	+
1655	2546	tctl = E1000_READ_REG(hw, TCTL);
1656	2547
1657	2548	tctl &= ~E1000_TCTL_COLD;
1658		- tctl \|= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
	2549	+ tctl \|= coll_dist << E1000_COLD_SHIFT;
1659	2550
1660	2551	E1000_WRITE_REG(hw, TCTL, tctl);
1661	2552	E1000_WRITE_FLUSH(hw);

		@@ -1679,6 +2570,11 @@ e1000_config_mac_to_phy(struct e1000_hw *hw)
1679	2570
1680	2571	DEBUGFUNC("e1000_config_mac_to_phy");
1681	2572
	2573	+ /* 82544 or newer MAC, Auto Speed Detection takes care of
	2574	+ * MAC speed/duplex configuration.*/
	2575	+ if (hw->mac_type >= e1000_82544)
	2576	+ return E1000_SUCCESS;
	2577	+
1682	2578	/* Read the Device Control Register and set the bits to Force Speed
1683	2579	* and Duplex.
1684	2580	*/

		@@ -1689,45 +2585,25 @@ e1000_config_mac_to_phy(struct e1000_hw *hw)
1689	2585	/* Set up duplex in the Device Control and Transmit Control
1690	2586	* registers depending on negotiated values.
1691	2587	*/
1692		- if (hw->phy_type == e1000_phy_igp) {
1693		- ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
1694		- &phy_data);
1695		- if(ret_val)
1696		- return ret_val;
1697		-
1698		- if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl \|= E1000_CTRL_FD;
1699		- else ctrl &= ~E1000_CTRL_FD;
1700		-
1701		- e1000_config_collision_dist(hw);
	2588	+ ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
	2589	+ if (ret_val)
	2590	+ return ret_val;
1702	2591
1703		- /* Set up speed in the Device Control register depending on
1704		- * negotiated values.
1705		- */
1706		- if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1707		- IGP01E1000_PSSR_SPEED_1000MBPS)
1708		- ctrl \|= E1000_CTRL_SPD_1000;
1709		- else if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1710		- IGP01E1000_PSSR_SPEED_100MBPS)
1711		- ctrl \|= E1000_CTRL_SPD_100;
1712		- } else {
1713		- ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
1714		- &phy_data);
1715		- if(ret_val)
1716		- return ret_val;
	2592	+ if (phy_data & M88E1000_PSSR_DPLX)
	2593	+ ctrl \|= E1000_CTRL_FD;
	2594	+ else
	2595	+ ctrl &= ~E1000_CTRL_FD;
1717	2596
1718		- if(phy_data & M88E1000_PSSR_DPLX) ctrl \|= E1000_CTRL_FD;
1719		- else ctrl &= ~E1000_CTRL_FD;
	2597	+ e1000_config_collision_dist(hw);
1720	2598
1721		- e1000_config_collision_dist(hw);
	2599	+ /* Set up speed in the Device Control register depending on
	2600	+ * negotiated values.
	2601	+ */
	2602	+ if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
	2603	+ ctrl \|= E1000_CTRL_SPD_1000;
	2604	+ else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
	2605	+ ctrl \|= E1000_CTRL_SPD_100;
1722	2606
1723		- /* Set up speed in the Device Control register depending on
1724		- * negotiated values.
1725		- */
1726		- if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1727		- ctrl \|= E1000_CTRL_SPD_1000;
1728		- else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1729		- ctrl \|= E1000_CTRL_SPD_100;
1730		- }
1731	2607	/* Write the configured values back to the Device Control Reg. */
1732	2608	E1000_WRITE_REG(hw, CTRL, ctrl);
1733	2609	return E1000_SUCCESS;

		@@ -1773,18 +2649,18 @@ e1000_force_mac_fc(struct e1000_hw *hw)
1773	2649	*/
1774	2650
1775	2651	switch (hw->fc) {
1776		- case e1000_fc_none:
	2652	+ case E1000_FC_NONE:
1777	2653	ctrl &= (~(E1000_CTRL_TFCE \| E1000_CTRL_RFCE));
1778	2654	break;
1779		- case e1000_fc_rx_pause:
	2655	+ case E1000_FC_RX_PAUSE:
1780	2656	ctrl &= (~E1000_CTRL_TFCE);
1781	2657	ctrl \|= E1000_CTRL_RFCE;
1782	2658	break;
1783		- case e1000_fc_tx_pause:
	2659	+ case E1000_FC_TX_PAUSE:
1784	2660	ctrl &= (~E1000_CTRL_RFCE);
1785	2661	ctrl \|= E1000_CTRL_TFCE;
1786	2662	break;
1787		- case e1000_fc_full:
	2663	+ case E1000_FC_FULL:
1788	2664	ctrl \|= (E1000_CTRL_TFCE \| E1000_CTRL_RFCE);
1789	2665	break;
1790	2666	default:

		@@ -1793,7 +2669,7 @@ e1000_force_mac_fc(struct e1000_hw *hw)
1793	2669	}
1794	2670
1795	2671	/* Disable TX Flow Control for 82542 (rev 2.0) */
1796		- if(hw->mac_type == e1000_82542_rev2_0)
	2672	+ if (hw->mac_type == e1000_82542_rev2_0)
1797	2673	ctrl &= (~E1000_CTRL_TFCE);
1798	2674
1799	2675	E1000_WRITE_REG(hw, CTRL, ctrl);

		@@ -1811,7 +2687,7 @@ e1000_force_mac_fc(struct e1000_hw *hw)
1811	2687	* based on the flow control negotiated by the PHY. In TBI mode, the TFCE
1812	2688	* and RFCE bits will be automaticaly set to the negotiated flow control mode.
1813	2689	*****************************************************************************/
1814		-int32_t
	2690	+static int32_t
1815	2691	e1000_config_fc_after_link_up(struct e1000_hw *hw)
1816	2692	{
1817	2693	int32_t ret_val;

		@@ -1827,11 +2703,12 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
1827	2703	* so we had to force link. In this case, we need to force the
1828	2704	* configuration of the MAC to match the "fc" parameter.
1829	2705	*/
1830		- if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) \|\|
1831		- ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed)) \|\|
1832		- ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
	2706	+ if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) \|\|
	2707	+ ((hw->media_type == e1000_media_type_internal_serdes) &&
	2708	+ (hw->autoneg_failed)) \|\|
	2709	+ ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
1833	2710	ret_val = e1000_force_mac_fc(hw);
1834		- if(ret_val) {
	2711	+ if (ret_val) {
1835	2712	DEBUGOUT("Error forcing flow control settings\n");
1836	2713	return ret_val;
1837	2714	}

		@@ -1842,19 +2719,19 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
1842	2719	* has completed, and if so, how the PHY and link partner has
1843	2720	* flow control configured.
1844	2721	*/
1845		- if((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
	2722	+ if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
1846	2723	/* Read the MII Status Register and check to see if AutoNeg
1847	2724	* has completed. We read this twice because this reg has
1848	2725	* some "sticky" (latched) bits.
1849	2726	*/
1850	2727	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1851		- if(ret_val)
	2728	+ if (ret_val)
1852	2729	return ret_val;
1853	2730	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1854		- if(ret_val)
	2731	+ if (ret_val)
1855	2732	return ret_val;
1856	2733
1857		- if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
	2734	+ if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
1858	2735	/* The AutoNeg process has completed, so we now need to
1859	2736	* read both the Auto Negotiation Advertisement Register
1860	2737	* (Address 4) and the Auto_Negotiation Base Page Ability

		@@ -1863,11 +2740,11 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
1863	2740	*/
1864	2741	ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
1865	2742	&mii_nway_adv_reg);
1866		- if(ret_val)
	2743	+ if (ret_val)
1867	2744	return ret_val;
1868	2745	ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
1869	2746	&mii_nway_lp_ability_reg);
1870		- if(ret_val)
	2747	+ if (ret_val)
1871	2748	return ret_val;
1872	2749
1873	2750	/* Two bits in the Auto Negotiation Advertisement Register

		@@ -1882,14 +2759,14 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
1882	2759	* LOCAL DEVICE \| LINK PARTNER
1883	2760	* PAUSE \| ASM_DIR \| PAUSE \| ASM_DIR \| NIC Resolution
1884	2761	*-------\|---------\|-------\|---------\|--------------------
1885		- * 0 \| 0 \| DC \| DC \| e1000_fc_none
1886		- * 0 \| 1 \| 0 \| DC \| e1000_fc_none
1887		- * 0 \| 1 \| 1 \| 0 \| e1000_fc_none
1888		- * 0 \| 1 \| 1 \| 1 \| e1000_fc_tx_pause
1889		- * 1 \| 0 \| 0 \| DC \| e1000_fc_none
1890		- * 1 \| DC \| 1 \| DC \| e1000_fc_full
1891		- * 1 \| 1 \| 0 \| 0 \| e1000_fc_none
1892		- * 1 \| 1 \| 0 \| 1 \| e1000_fc_rx_pause
	2762	+ * 0 \| 0 \| DC \| DC \| E1000_FC_NONE
	2763	+ * 0 \| 1 \| 0 \| DC \| E1000_FC_NONE
	2764	+ * 0 \| 1 \| 1 \| 0 \| E1000_FC_NONE
	2765	+ * 0 \| 1 \| 1 \| 1 \| E1000_FC_TX_PAUSE
	2766	+ * 1 \| 0 \| 0 \| DC \| E1000_FC_NONE
	2767	+ * 1 \| DC \| 1 \| DC \| E1000_FC_FULL
	2768	+ * 1 \| 1 \| 0 \| 0 \| E1000_FC_NONE
	2769	+ * 1 \| 1 \| 0 \| 1 \| E1000_FC_RX_PAUSE
1893	2770	*
1894	2771	*/
1895	2772	/* Are both PAUSE bits set to 1? If so, this implies

		@@ -1901,23 +2778,23 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
1901	2778	* LOCAL DEVICE \| LINK PARTNER
1902	2779	* PAUSE \| ASM_DIR \| PAUSE \| ASM_DIR \| Result
1903	2780	*-------\|---------\|-------\|---------\|--------------------
1904		- * 1 \| DC \| 1 \| DC \| e1000_fc_full
	2781	+ * 1 \| DC \| 1 \| DC \| E1000_FC_FULL
1905	2782	*
1906	2783	*/
1907		- if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1908		- (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
	2784	+ if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
	2785	+ (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1909	2786	/* Now we need to check if the user selected RX ONLY
1910	2787	* of pause frames. In this case, we had to advertise
1911	2788	* FULL flow control because we could not advertise RX
1912	2789	* ONLY. Hence, we must now check to see if we need to
1913	2790	* turn OFF the TRANSMISSION of PAUSE frames.
1914	2791	*/
1915		- if(hw->original_fc == e1000_fc_full) {
1916		- hw->fc = e1000_fc_full;
1917		- DEBUGOUT("Flow Control = FULL.\r\n");
	2792	+ if (hw->original_fc == E1000_FC_FULL) {
	2793	+ hw->fc = E1000_FC_FULL;
	2794	+ DEBUGOUT("Flow Control = FULL.\n");
1918	2795	} else {
1919		- hw->fc = e1000_fc_rx_pause;
1920		- DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
	2796	+ hw->fc = E1000_FC_RX_PAUSE;
	2797	+ DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1921	2798	}
1922	2799	}
1923	2800	/* For receiving PAUSE frames ONLY.

		@@ -1925,30 +2802,30 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
1925	2802	* LOCAL DEVICE \| LINK PARTNER
1926	2803	* PAUSE \| ASM_DIR \| PAUSE \| ASM_DIR \| Result
1927	2804	*-------\|---------\|-------\|---------\|--------------------
1928		- * 0 \| 1 \| 1 \| 1 \| e1000_fc_tx_pause
	2805	+ * 0 \| 1 \| 1 \| 1 \| E1000_FC_TX_PAUSE
1929	2806	*
1930	2807	*/
1931		- else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1932		- (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1933		- (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1934		- (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1935		- hw->fc = e1000_fc_tx_pause;
1936		- DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
	2808	+ else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
	2809	+ (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
	2810	+ (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
	2811	+ (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
	2812	+ hw->fc = E1000_FC_TX_PAUSE;
	2813	+ DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
1937	2814	}
1938	2815	/* For transmitting PAUSE frames ONLY.
1939	2816	*
1940	2817	* LOCAL DEVICE \| LINK PARTNER
1941	2818	* PAUSE \| ASM_DIR \| PAUSE \| ASM_DIR \| Result
1942	2819	*-------\|---------\|-------\|---------\|--------------------
1943		- * 1 \| 1 \| 0 \| 1 \| e1000_fc_rx_pause
	2820	+ * 1 \| 1 \| 0 \| 1 \| E1000_FC_RX_PAUSE
1944	2821	*
1945	2822	*/
1946		- else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1947		- (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1948		- !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1949		- (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1950		- hw->fc = e1000_fc_rx_pause;
1951		- DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
	2823	+ else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
	2824	+ (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
	2825	+ !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
	2826	+ (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
	2827	+ hw->fc = E1000_FC_RX_PAUSE;
	2828	+ DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1952	2829	}
1953	2830	/* Per the IEEE spec, at this point flow control should be
1954	2831	* disabled. However, we want to consider that we could

		@@ -1970,14 +2847,14 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
1970	2847	* be asked to delay transmission of packets than asking
1971	2848	* our link partner to pause transmission of frames.
1972	2849	*/
1973		- else if((hw->original_fc == e1000_fc_none \|\|
1974		- hw->original_fc == e1000_fc_tx_pause) \|\|
1975		- hw->fc_strict_ieee) {
1976		- hw->fc = e1000_fc_none;
1977		- DEBUGOUT("Flow Control = NONE.\r\n");
	2850	+ else if ((hw->original_fc == E1000_FC_NONE\|\|
	2851	+ hw->original_fc == E1000_FC_TX_PAUSE) \|\|
	2852	+ hw->fc_strict_ieee) {
	2853	+ hw->fc = E1000_FC_NONE;
	2854	+ DEBUGOUT("Flow Control = NONE.\n");
1978	2855	} else {
1979		- hw->fc = e1000_fc_rx_pause;
1980		- DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
	2856	+ hw->fc = E1000_FC_RX_PAUSE;
	2857	+ DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1981	2858	}
1982	2859
1983	2860	/* Now we need to do one last check... If we auto-

		@@ -1985,24 +2862,24 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
1985	2862	* enabled per IEEE 802.3 spec.
1986	2863	*/
1987	2864	ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
1988		- if(ret_val) {
	2865	+ if (ret_val) {
1989	2866	DEBUGOUT("Error getting link speed and duplex\n");
1990	2867	return ret_val;
1991	2868	}
1992	2869
1993		- if(duplex == HALF_DUPLEX)
1994		- hw->fc = e1000_fc_none;
	2870	+ if (duplex == HALF_DUPLEX)
	2871	+ hw->fc = E1000_FC_NONE;
1995	2872
1996	2873	/* Now we call a subroutine to actually force the MAC
1997	2874	* controller to use the correct flow control settings.
1998	2875	*/
1999	2876	ret_val = e1000_force_mac_fc(hw);
2000		- if(ret_val) {
	2877	+ if (ret_val) {
2001	2878	DEBUGOUT("Error forcing flow control settings\n");
2002	2879	return ret_val;
2003	2880	}
2004	2881	} else {
2005		- DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
	2882	+ DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
2006	2883	}
2007	2884	}
2008	2885	return E1000_SUCCESS;

		@@ -2036,13 +2913,13 @@ e1000_check_for_link(struct e1000_hw *hw)
2036	2913	* set when the optics detect a signal. On older adapters, it will be
2037	2914	* cleared when there is a signal. This applies to fiber media only.
2038	2915	*/
2039		- if((hw->media_type == e1000_media_type_fiber) \|\|
2040		- (hw->media_type == e1000_media_type_internal_serdes)) {
	2916	+ if ((hw->media_type == e1000_media_type_fiber) \|\|
	2917	+ (hw->media_type == e1000_media_type_internal_serdes)) {
2041	2918	rxcw = E1000_READ_REG(hw, RXCW);
2042	2919
2043		- if(hw->media_type == e1000_media_type_fiber) {
	2920	+ if (hw->media_type == e1000_media_type_fiber) {
2044	2921	signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2045		- if(status & E1000_STATUS_LU)
	2922	+ if (status & E1000_STATUS_LU)
2046	2923	hw->get_link_status = FALSE;
2047	2924	}
2048	2925	}

		@@ -2053,20 +2930,20 @@ e1000_check_for_link(struct e1000_hw *hw)
2053	2930	* receive a Link Status Change interrupt or we have Rx Sequence
2054	2931	* Errors.
2055	2932	*/
2056		- if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
	2933	+ if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2057	2934	/* First we want to see if the MII Status Register reports
2058	2935	* link. If so, then we want to get the current speed/duplex
2059	2936	* of the PHY.
2060	2937	* Read the register twice since the link bit is sticky.
2061	2938	*/
2062	2939	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2063		- if(ret_val)
	2940	+ if (ret_val)
2064	2941	return ret_val;
2065	2942	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2066		- if(ret_val)
	2943	+ if (ret_val)
2067	2944	return ret_val;
2068	2945
2069		- if(phy_data & MII_SR_LINK_STATUS) {
	2946	+ if (phy_data & MII_SR_LINK_STATUS) {
2070	2947	hw->get_link_status = FALSE;
2071	2948	/* Check if there was DownShift, must be checked immediately after
2072	2949	* link-up */

		@@ -2080,10 +2957,10 @@ e1000_check_for_link(struct e1000_hw *hw)
2080	2957	* happen due to the execution of this workaround.
2081	2958	*/
2082	2959
2083		- if((hw->mac_type == e1000_82544 \|\| hw->mac_type == e1000_82543) &&
2084		- (!hw->autoneg) &&
2085		- (hw->forced_speed_duplex == e1000_10_full \|\|
2086		- hw->forced_speed_duplex == e1000_10_half)) {
	2960	+ if ((hw->mac_type == e1000_82544 \|\| hw->mac_type == e1000_82543) &&
	2961	+ (!hw->autoneg) &&
	2962	+ (hw->forced_speed_duplex == e1000_10_full \|\|
	2963	+ hw->forced_speed_duplex == e1000_10_half)) {
2087	2964	E1000_WRITE_REG(hw, IMC, 0xffffffff);
2088	2965	ret_val = e1000_polarity_reversal_workaround(hw);
2089	2966	icr = E1000_READ_REG(hw, ICR);

		@@ -2100,7 +2977,7 @@ e1000_check_for_link(struct e1000_hw *hw)
2100	2977	/* If we are forcing speed/duplex, then we simply return since
2101	2978	* we have already determined whether we have link or not.
2102	2979	*/
2103		- if(!hw->autoneg) return -E1000_ERR_CONFIG;
	2980	+ if (!hw->autoneg) return -E1000_ERR_CONFIG;
2104	2981
2105	2982	/* optimize the dsp settings for the igp phy */
2106	2983	e1000_config_dsp_after_link_change(hw, TRUE);

		@@ -2113,11 +2990,11 @@ e1000_check_for_link(struct e1000_hw *hw)
2113	2990	* speed/duplex on the MAC to the current PHY speed/duplex
2114	2991	* settings.
2115	2992	*/
2116		- if(hw->mac_type >= e1000_82544)
	2993	+ if (hw->mac_type >= e1000_82544)
2117	2994	e1000_config_collision_dist(hw);
2118	2995	else {
2119	2996	ret_val = e1000_config_mac_to_phy(hw);
2120		- if(ret_val) {
	2997	+ if (ret_val) {
2121	2998	DEBUGOUT("Error configuring MAC to PHY settings\n");
2122	2999	return ret_val;
2123	3000	}

		@@ -2128,7 +3005,7 @@ e1000_check_for_link(struct e1000_hw *hw)
2128	3005	* have had to re-autoneg with a different link partner.
2129	3006	*/
2130	3007	ret_val = e1000_config_fc_after_link_up(hw);
2131		- if(ret_val) {
	3008	+ if (ret_val) {
2132	3009	DEBUGOUT("Error configuring flow control\n");
2133	3010	return ret_val;
2134	3011	}

		@@ -2140,14 +3017,18 @@ e1000_check_for_link(struct e1000_hw *hw)
2140	3017	* at gigabit speed, then TBI compatibility is not needed. If we are
2141	3018	* at gigabit speed, we turn on TBI compatibility.
2142	3019	*/
2143		- if(hw->tbi_compatibility_en) {
	3020	+ if (hw->tbi_compatibility_en) {
2144	3021	uint16_t speed, duplex;
2145		- e1000_get_speed_and_duplex(hw, &speed, &duplex);
2146		- if(speed != SPEED_1000) {
	3022	+ ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
	3023	+ if (ret_val) {
	3024	+ DEBUGOUT("Error getting link speed and duplex\n");
	3025	+ return ret_val;
	3026	+ }
	3027	+ if (speed != SPEED_1000) {
2147	3028	/* If link speed is not set to gigabit speed, we do not need
2148	3029	* to enable TBI compatibility.
2149	3030	*/
2150		- if(hw->tbi_compatibility_on) {
	3031	+ if (hw->tbi_compatibility_on) {
2151	3032	/* If we previously were in the mode, turn it off. */
2152	3033	rctl = E1000_READ_REG(hw, RCTL);
2153	3034	rctl &= ~E1000_RCTL_SBP;

		@@ -2160,7 +3041,7 @@ e1000_check_for_link(struct e1000_hw *hw)
2160	3041	* packets. Some frames have an additional byte on the end and
2161	3042	* will look like CRC errors to to the hardware.
2162	3043	*/
2163		- if(!hw->tbi_compatibility_on) {
	3044	+ if (!hw->tbi_compatibility_on) {
2164	3045	hw->tbi_compatibility_on = TRUE;
2165	3046	rctl = E1000_READ_REG(hw, RCTL);
2166	3047	rctl \|= E1000_RCTL_SBP;

		@@ -2176,16 +3057,16 @@ e1000_check_for_link(struct e1000_hw *hw)
2176	3057	* auto-negotiation time to complete, in case the cable was just plugged
2177	3058	* in. The autoneg_failed flag does this.
2178	3059	*/
2179		- else if((((hw->media_type == e1000_media_type_fiber) &&
	3060	+ else if ((((hw->media_type == e1000_media_type_fiber) &&
2180	3061	((ctrl & E1000_CTRL_SWDPIN1) == signal)) \|\|
2181		- (hw->media_type == e1000_media_type_internal_serdes)) &&
2182		- (!(status & E1000_STATUS_LU)) &&
2183		- (!(rxcw & E1000_RXCW_C))) {
2184		- if(hw->autoneg_failed == 0) {
	3062	+ (hw->media_type == e1000_media_type_internal_serdes)) &&
	3063	+ (!(status & E1000_STATUS_LU)) &&
	3064	+ (!(rxcw & E1000_RXCW_C))) {
	3065	+ if (hw->autoneg_failed == 0) {
2185	3066	hw->autoneg_failed = 1;
2186	3067	return 0;
2187	3068	}
2188		- DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
	3069	+ DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
2189	3070
2190	3071	/* Disable auto-negotiation in the TXCW register */
2191	3072	E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));

		@@ -2197,7 +3078,7 @@ e1000_check_for_link(struct e1000_hw *hw)
2197	3078
2198	3079	/* Configure Flow Control after forcing link up. */
2199	3080	ret_val = e1000_config_fc_after_link_up(hw);
2200		- if(ret_val) {
	3081	+ if (ret_val) {
2201	3082	DEBUGOUT("Error configuring flow control\n");
2202	3083	return ret_val;
2203	3084	}

		@@ -2207,10 +3088,10 @@ e1000_check_for_link(struct e1000_hw *hw)
2207	3088	* Device Control register in an attempt to auto-negotiate with our link
2208	3089	* partner.
2209	3090	*/
2210		- else if(((hw->media_type == e1000_media_type_fiber) \|\|
2211		- (hw->media_type == e1000_media_type_internal_serdes)) &&
2212		- (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
2213		- DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
	3091	+ else if (((hw->media_type == e1000_media_type_fiber) \|\|
	3092	+ (hw->media_type == e1000_media_type_internal_serdes)) &&
	3093	+ (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
	3094	+ DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
2214	3095	E1000_WRITE_REG(hw, TXCW, hw->txcw);
2215	3096	E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
2216	3097

		@@ -2219,12 +3100,12 @@ e1000_check_for_link(struct e1000_hw *hw)
2219	3100	/* If we force link for non-auto-negotiation switch, check link status
2220	3101	* based on MAC synchronization for internal serdes media type.
2221	3102	*/
2222		- else if((hw->media_type == e1000_media_type_internal_serdes) &&
2223		- !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
	3103	+ else if ((hw->media_type == e1000_media_type_internal_serdes) &&
	3104	+ !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2224	3105	/* SYNCH bit and IV bit are sticky. */
2225		- udelay(10);
2226		- if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
2227		- if(!(rxcw & E1000_RXCW_IV)) {
	3106	+ usec_delay(10);
	3107	+ if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
	3108	+ if (!(rxcw & E1000_RXCW_IV)) {
2228	3109	hw->serdes_link_down = FALSE;
2229	3110	DEBUGOUT("SERDES: Link is up.\n");
2230	3111	}

		@@ -2233,8 +3114,8 @@ e1000_check_for_link(struct e1000_hw *hw)
2233	3114	DEBUGOUT("SERDES: Link is down.\n");
2234	3115	}
2235	3116	}
2236		- if((hw->media_type == e1000_media_type_internal_serdes) &&
2237		- (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
	3117	+ if ((hw->media_type == e1000_media_type_internal_serdes) &&
	3118	+ (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2238	3119	hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
2239	3120	}
2240	3121	return E1000_SUCCESS;

		@@ -2258,12 +3139,12 @@ e1000_get_speed_and_duplex(struct e1000_hw *hw,
2258	3139
2259	3140	DEBUGFUNC("e1000_get_speed_and_duplex");
2260	3141
2261		- if(hw->mac_type >= e1000_82543) {
	3142	+ if (hw->mac_type >= e1000_82543) {
2262	3143	status = E1000_READ_REG(hw, STATUS);
2263		- if(status & E1000_STATUS_SPEED_1000) {
	3144	+ if (status & E1000_STATUS_SPEED_1000) {
2264	3145	*speed = SPEED_1000;
2265	3146	DEBUGOUT("1000 Mbs, ");
2266		- } else if(status & E1000_STATUS_SPEED_100) {
	3147	+ } else if (status & E1000_STATUS_SPEED_100) {
2267	3148	*speed = SPEED_100;
2268	3149	DEBUGOUT("100 Mbs, ");
2269	3150	} else {

		@@ -2271,15 +3152,15 @@ e1000_get_speed_and_duplex(struct e1000_hw *hw,
2271	3152	DEBUGOUT("10 Mbs, ");
2272	3153	}
2273	3154
2274		- if(status & E1000_STATUS_FD) {
	3155	+ if (status & E1000_STATUS_FD) {
2275	3156	*duplex = FULL_DUPLEX;
2276		- DEBUGOUT("Full Duplex\r\n");
	3157	+ DEBUGOUT("Full Duplex\n");
2277	3158	} else {
2278	3159	*duplex = HALF_DUPLEX;
2279		- DEBUGOUT(" Half Duplex\r\n");
	3160	+ DEBUGOUT(" Half Duplex\n");
2280	3161	}
2281	3162	} else {
2282		- DEBUGOUT("1000 Mbs, Full Duplex\r\n");
	3163	+ DEBUGOUT("1000 Mbs, Full Duplex\n");
2283	3164	*speed = SPEED_1000;
2284	3165	*duplex = FULL_DUPLEX;
2285	3166	}

		@@ -2288,23 +3169,39 @@ e1000_get_speed_and_duplex(struct e1000_hw *hw,
2288	3169	* if it is operating at half duplex. Here we set the duplex settings to
2289	3170	* match the duplex in the link partner's capabilities.
2290	3171	*/
2291		- if(hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
	3172	+ if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
2292	3173	ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
2293		- if(ret_val)
	3174	+ if (ret_val)
2294	3175	return ret_val;
2295	3176
2296		- if(!(phy_data & NWAY_ER_LP_NWAY_CAPS))
	3177	+ if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
2297	3178	*duplex = HALF_DUPLEX;
2298	3179	else {
2299	3180	ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
2300		- if(ret_val)
	3181	+ if (ret_val)
2301	3182	return ret_val;
2302		- if((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) \|\|
	3183	+ if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) \|\|
2303	3184	(*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
2304	3185	*duplex = HALF_DUPLEX;
2305	3186	}
2306	3187	}
2307	3188
	3189	+ if ((hw->mac_type == e1000_80003es2lan) &&
	3190	+ (hw->media_type == e1000_media_type_copper)) {
	3191	+ if (*speed == SPEED_1000)
	3192	+ ret_val = e1000_configure_kmrn_for_1000(hw);
	3193	+ else
	3194	+ ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
	3195	+ if (ret_val)
	3196	+ return ret_val;
	3197	+ }
	3198	+
	3199	+ if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
	3200	+ ret_val = e1000_kumeran_lock_loss_workaround(hw);
	3201	+ if (ret_val)
	3202	+ return ret_val;
	3203	+ }
	3204	+
2308	3205	return E1000_SUCCESS;
2309	3206	}
2310	3207

		@@ -2313,7 +3210,7 @@ e1000_get_speed_and_duplex(struct e1000_hw *hw,
2313	3210	*
2314	3211	* hw - Struct containing variables accessed by shared code
2315	3212	******************************************************************************/
2316		-int32_t
	3213	+static int32_t
2317	3214	e1000_wait_autoneg(struct e1000_hw *hw)
2318	3215	{
2319	3216	int32_t ret_val;

		@@ -2324,17 +3221,17 @@ e1000_wait_autoneg(struct e1000_hw *hw)
2324	3221	DEBUGOUT("Waiting for Auto-Neg to complete.\n");
2325	3222
2326	3223	/* We will wait for autoneg to complete or 4.5 seconds to expire. */
2327		- for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
	3224	+ for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2328	3225	/* Read the MII Status Register and wait for Auto-Neg
2329	3226	* Complete bit to be set.
2330	3227	*/
2331	3228	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2332		- if(ret_val)
	3229	+ if (ret_val)
2333	3230	return ret_val;
2334	3231	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2335		- if(ret_val)
	3232	+ if (ret_val)
2336	3233	return ret_val;
2337		- if(phy_data & MII_SR_AUTONEG_COMPLETE) {
	3234	+ if (phy_data & MII_SR_AUTONEG_COMPLETE) {
2338	3235	return E1000_SUCCESS;
2339	3236	}
2340	3237	msec_delay(100);

		@@ -2357,7 +3254,7 @@ e1000_raise_mdi_clk(struct e1000_hw *hw,
2357	3254	*/
2358	3255	E1000_WRITE_REG(hw, CTRL, (*ctrl \| E1000_CTRL_MDC));
2359	3256	E1000_WRITE_FLUSH(hw);
2360		- udelay(10);
	3257	+ usec_delay(10);
2361	3258	}
2362	3259
2363	3260	/******************************************************************************

		@@ -2375,7 +3272,7 @@ e1000_lower_mdi_clk(struct e1000_hw *hw,
2375	3272	*/
2376	3273	E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
2377	3274	E1000_WRITE_FLUSH(hw);
2378		- udelay(10);
	3275	+ usec_delay(10);
2379	3276	}
2380	3277
2381	3278	/******************************************************************************

		@@ -2407,19 +3304,21 @@ e1000_shift_out_mdi_bits(struct e1000_hw *hw,
2407	3304	/* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2408	3305	ctrl \|= (E1000_CTRL_MDIO_DIR \| E1000_CTRL_MDC_DIR);
2409	3306
2410		- while(mask) {
	3307	+ while (mask) {
2411	3308	/* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2412	3309	* then raising and lowering the Management Data Clock. A "0" is
2413	3310	* shifted out to the PHY by setting the MDIO bit to "0" and then
2414	3311	* raising and lowering the clock.
2415	3312	*/
2416		- if(data & mask) ctrl \|= E1000_CTRL_MDIO;
2417		- else ctrl &= ~E1000_CTRL_MDIO;
	3313	+ if (data & mask)
	3314	+ ctrl \|= E1000_CTRL_MDIO;
	3315	+ else
	3316	+ ctrl &= ~E1000_CTRL_MDIO;
2418	3317
2419	3318	E1000_WRITE_REG(hw, CTRL, ctrl);
2420	3319	E1000_WRITE_FLUSH(hw);
2421	3320
2422		- udelay(10);
	3321	+ usec_delay(10);
2423	3322
2424	3323	e1000_raise_mdi_clk(hw, &ctrl);
2425	3324	e1000_lower_mdi_clk(hw, &ctrl);

		@@ -2465,12 +3364,13 @@ e1000_shift_in_mdi_bits(struct e1000_hw *hw)
2465	3364	e1000_raise_mdi_clk(hw, &ctrl);
2466	3365	e1000_lower_mdi_clk(hw, &ctrl);
2467	3366
2468		- for(data = 0, i = 0; i < 16; i++) {
	3367	+ for (data = 0, i = 0; i < 16; i++) {
2469	3368	data = data << 1;
2470	3369	e1000_raise_mdi_clk(hw, &ctrl);
2471	3370	ctrl = E1000_READ_REG(hw, CTRL);
2472	3371	/* Check to see if we shifted in a "1". */
2473		- if(ctrl & E1000_CTRL_MDIO) data \|= 1;
	3372	+ if (ctrl & E1000_CTRL_MDIO)
	3373	+ data \|= 1;
2474	3374	e1000_lower_mdi_clk(hw, &ctrl);
2475	3375	}
2476	3376

		@@ -2480,6 +3380,80 @@ e1000_shift_in_mdi_bits(struct e1000_hw *hw)
2480	3380	return data;
2481	3381	}
2482	3382
	3383	+static int32_t
	3384	+e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
	3385	+{
	3386	+ uint32_t swfw_sync = 0;
	3387	+ uint32_t swmask = mask;
	3388	+ uint32_t fwmask = mask << 16;
	3389	+ int32_t timeout = 200;
	3390	+
	3391	+ DEBUGFUNC("e1000_swfw_sync_acquire");
	3392	+
	3393	+ if (hw->swfwhw_semaphore_present)
	3394	+ return e1000_get_software_flag(hw);
	3395	+
	3396	+ if (!hw->swfw_sync_present)
	3397	+ return e1000_get_hw_eeprom_semaphore(hw);
	3398	+
	3399	+ while (timeout) {
	3400	+ if (e1000_get_hw_eeprom_semaphore(hw))
	3401	+ return -E1000_ERR_SWFW_SYNC;
	3402	+
	3403	+ swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
	3404	+ if (!(swfw_sync & (fwmask \| swmask))) {
	3405	+ break;
	3406	+ }
	3407	+
	3408	+ /* firmware currently using resource (fwmask) */
	3409	+ /* or other software thread currently using resource (swmask) */
	3410	+ e1000_put_hw_eeprom_semaphore(hw);
	3411	+ msec_delay_irq(5);
	3412	+ timeout--;
	3413	+ }
	3414	+
	3415	+ if (!timeout) {
	3416	+ DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
	3417	+ return -E1000_ERR_SWFW_SYNC;
	3418	+ }
	3419	+
	3420	+ swfw_sync \|= swmask;
	3421	+ E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
	3422	+
	3423	+ e1000_put_hw_eeprom_semaphore(hw);
	3424	+ return E1000_SUCCESS;
	3425	+}
	3426	+
	3427	+static void
	3428	+e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
	3429	+{
	3430	+ uint32_t swfw_sync;
	3431	+ uint32_t swmask = mask;
	3432	+
	3433	+ DEBUGFUNC("e1000_swfw_sync_release");
	3434	+
	3435	+ if (hw->swfwhw_semaphore_present) {
	3436	+ e1000_release_software_flag(hw);
	3437	+ return;
	3438	+ }
	3439	+
	3440	+ if (!hw->swfw_sync_present) {
	3441	+ e1000_put_hw_eeprom_semaphore(hw);
	3442	+ return;
	3443	+ }
	3444	+
	3445	+ /* if (e1000_get_hw_eeprom_semaphore(hw))
	3446	+ * return -E1000_ERR_SWFW_SYNC; */
	3447	+ while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
	3448	+ /* empty */
	3449	+
	3450	+ swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
	3451	+ swfw_sync &= ~swmask;
	3452	+ E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
	3453	+
	3454	+ e1000_put_hw_eeprom_semaphore(hw);
	3455	+}
	3456	+
2483	3457	/*****************************************************************************
2484	3458	* Reads the value from a PHY register, if the value is on a specific non zero
2485	3459	* page, sets the page first.

		@@ -2492,28 +3466,61 @@ e1000_read_phy_reg(struct e1000_hw *hw,
2492	3466	uint16_t *phy_data)
2493	3467	{
2494	3468	uint32_t ret_val;
	3469	+ uint16_t swfw;
2495	3470
2496	3471	DEBUGFUNC("e1000_read_phy_reg");
2497	3472
	3473	+ if ((hw->mac_type == e1000_80003es2lan) &&
	3474	+ (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
	3475	+ swfw = E1000_SWFW_PHY1_SM;
	3476	+ } else {
	3477	+ swfw = E1000_SWFW_PHY0_SM;
	3478	+ }
	3479	+ if (e1000_swfw_sync_acquire(hw, swfw))
	3480	+ return -E1000_ERR_SWFW_SYNC;
2498	3481
2499		- if(hw->phy_type == e1000_phy_igp &&
	3482	+ if ((hw->phy_type == e1000_phy_igp \|\|
	3483	+ hw->phy_type == e1000_phy_igp_3 \|\|
	3484	+ hw->phy_type == e1000_phy_igp_2) &&
2500	3485	(reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2501	3486	ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2502	3487	(uint16_t)reg_addr);
2503		- if(ret_val) {
	3488	+ if (ret_val) {
	3489	+ e1000_swfw_sync_release(hw, swfw);
2504	3490	return ret_val;
2505	3491	}
	3492	+ } else if (hw->phy_type == e1000_phy_gg82563) {
	3493	+ if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) \|\|
	3494	+ (hw->mac_type == e1000_80003es2lan)) {
	3495	+ /* Select Configuration Page */
	3496	+ if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
	3497	+ ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
	3498	+ (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
	3499	+ } else {
	3500	+ /* Use Alternative Page Select register to access
	3501	+ * registers 30 and 31
	3502	+ */
	3503	+ ret_val = e1000_write_phy_reg_ex(hw,
	3504	+ GG82563_PHY_PAGE_SELECT_ALT,
	3505	+ (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
	3506	+ }
	3507	+
	3508	+ if (ret_val) {
	3509	+ e1000_swfw_sync_release(hw, swfw);
	3510	+ return ret_val;
	3511	+ }
	3512	+ }
2506	3513	}
2507	3514
2508	3515	ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2509	3516	phy_data);
2510	3517
	3518	+ e1000_swfw_sync_release(hw, swfw);
2511	3519	return ret_val;
2512	3520	}
2513	3521
2514		-int32_t
2515		-e1000_read_phy_reg_ex(struct e1000_hw *hw,
2516		- uint32_t reg_addr,
	3522	+static int32_t
	3523	+e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
2517	3524	uint16_t *phy_data)
2518	3525	{
2519	3526	uint32_t i;

		@@ -2522,12 +3529,12 @@ e1000_read_phy_reg_ex(struct e1000_hw *hw,
2522	3529
2523	3530	DEBUGFUNC("e1000_read_phy_reg_ex");
2524	3531
2525		- if(reg_addr > MAX_PHY_REG_ADDRESS) {
	3532	+ if (reg_addr > MAX_PHY_REG_ADDRESS) {
2526	3533	DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2527	3534	return -E1000_ERR_PARAM;
2528	3535	}
2529	3536
2530		- if(hw->mac_type > e1000_82543) {
	3537	+ if (hw->mac_type > e1000_82543) {
2531	3538	/* Set up Op-code, Phy Address, and register address in the MDI
2532	3539	* Control register. The MAC will take care of interfacing with the
2533	3540	* PHY to retrieve the desired data.

		@@ -2539,16 +3546,16 @@ e1000_read_phy_reg_ex(struct e1000_hw *hw,
2539	3546	E1000_WRITE_REG(hw, MDIC, mdic);
2540	3547
2541	3548	/* Poll the ready bit to see if the MDI read completed */
2542		- for(i = 0; i < 64; i++) {
2543		- udelay(50);
	3549	+ for (i = 0; i < 64; i++) {
	3550	+ usec_delay(50);
2544	3551	mdic = E1000_READ_REG(hw, MDIC);
2545		- if(mdic & E1000_MDIC_READY) break;
	3552	+ if (mdic & E1000_MDIC_READY) break;
2546	3553	}
2547		- if(!(mdic & E1000_MDIC_READY)) {
	3554	+ if (!(mdic & E1000_MDIC_READY)) {
2548	3555	DEBUGOUT("MDI Read did not complete\n");
2549	3556	return -E1000_ERR_PHY;
2550	3557	}
2551		- if(mdic & E1000_MDIC_ERROR) {
	3558	+ if (mdic & E1000_MDIC_ERROR) {
2552	3559	DEBUGOUT("MDI Error\n");
2553	3560	return -E1000_ERR_PHY;
2554	3561	}

		@@ -2593,34 +3600,66 @@ e1000_read_phy_reg_ex(struct e1000_hw *hw,
2593	3600	* data - data to write to the PHY
2594	3601	******************************************************************************/
2595	3602	int32_t
2596		-e1000_write_phy_reg(struct e1000_hw *hw,
2597		- uint32_t reg_addr,
	3603	+e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
2598	3604	uint16_t phy_data)
2599	3605	{
2600	3606	uint32_t ret_val;
	3607	+ uint16_t swfw;
2601	3608
2602	3609	DEBUGFUNC("e1000_write_phy_reg");
2603	3610
	3611	+ if ((hw->mac_type == e1000_80003es2lan) &&
	3612	+ (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
	3613	+ swfw = E1000_SWFW_PHY1_SM;
	3614	+ } else {
	3615	+ swfw = E1000_SWFW_PHY0_SM;
	3616	+ }
	3617	+ if (e1000_swfw_sync_acquire(hw, swfw))
	3618	+ return -E1000_ERR_SWFW_SYNC;
2604	3619
2605		- if(hw->phy_type == e1000_phy_igp &&
	3620	+ if ((hw->phy_type == e1000_phy_igp \|\|
	3621	+ hw->phy_type == e1000_phy_igp_3 \|\|
	3622	+ hw->phy_type == e1000_phy_igp_2) &&
2606	3623	(reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2607	3624	ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2608	3625	(uint16_t)reg_addr);
2609		- if(ret_val) {
	3626	+ if (ret_val) {
	3627	+ e1000_swfw_sync_release(hw, swfw);
2610	3628	return ret_val;
2611	3629	}
	3630	+ } else if (hw->phy_type == e1000_phy_gg82563) {
	3631	+ if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) \|\|
	3632	+ (hw->mac_type == e1000_80003es2lan)) {
	3633	+ /* Select Configuration Page */
	3634	+ if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
	3635	+ ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
	3636	+ (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
	3637	+ } else {
	3638	+ /* Use Alternative Page Select register to access
	3639	+ * registers 30 and 31
	3640	+ */
	3641	+ ret_val = e1000_write_phy_reg_ex(hw,
	3642	+ GG82563_PHY_PAGE_SELECT_ALT,
	3643	+ (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
	3644	+ }
	3645	+
	3646	+ if (ret_val) {
	3647	+ e1000_swfw_sync_release(hw, swfw);
	3648	+ return ret_val;
	3649	+ }
	3650	+ }
2612	3651	}
2613	3652
2614	3653	ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2615	3654	phy_data);
2616	3655
	3656	+ e1000_swfw_sync_release(hw, swfw);
2617	3657	return ret_val;
2618	3658	}
2619	3659
2620		-int32_t
2621		-e1000_write_phy_reg_ex(struct e1000_hw *hw,
2622		- uint32_t reg_addr,
2623		- uint16_t phy_data)
	3660	+static int32_t
	3661	+e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
	3662	+ uint16_t phy_data)
2624	3663	{
2625	3664	uint32_t i;
2626	3665	uint32_t mdic = 0;

		@@ -2628,12 +3667,12 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw,
2628	3667
2629	3668	DEBUGFUNC("e1000_write_phy_reg_ex");
2630	3669
2631		- if(reg_addr > MAX_PHY_REG_ADDRESS) {
	3670	+ if (reg_addr > MAX_PHY_REG_ADDRESS) {
2632	3671	DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2633	3672	return -E1000_ERR_PARAM;
2634	3673	}
2635	3674
2636		- if(hw->mac_type > e1000_82543) {
	3675	+ if (hw->mac_type > e1000_82543) {
2637	3676	/* Set up Op-code, Phy Address, register address, and data intended
2638	3677	* for the PHY register in the MDI Control register. The MAC will take
2639	3678	* care of interfacing with the PHY to send the desired data.

		@@ -2646,12 +3685,12 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw,
2646	3685	E1000_WRITE_REG(hw, MDIC, mdic);
2647	3686
2648	3687	/* Poll the ready bit to see if the MDI read completed */
2649		- for(i = 0; i < 640; i++) {
2650		- udelay(5);
	3688	+ for (i = 0; i < 641; i++) {
	3689	+ usec_delay(5);
2651	3690	mdic = E1000_READ_REG(hw, MDIC);
2652		- if(mdic & E1000_MDIC_READY) break;
	3691	+ if (mdic & E1000_MDIC_READY) break;
2653	3692	}
2654		- if(!(mdic & E1000_MDIC_READY)) {
	3693	+ if (!(mdic & E1000_MDIC_READY)) {
2655	3694	DEBUGOUT("MDI Write did not complete\n");
2656	3695	return -E1000_ERR_PHY;
2657	3696	}

		@@ -2680,31 +3719,122 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw,
2680	3719	return E1000_SUCCESS;
2681	3720	}
2682	3721
	3722	+static int32_t
	3723	+e1000_read_kmrn_reg(struct e1000_hw *hw,
	3724	+ uint32_t reg_addr,
	3725	+ uint16_t *data)
	3726	+{
	3727	+ uint32_t reg_val;
	3728	+ uint16_t swfw;
	3729	+ DEBUGFUNC("e1000_read_kmrn_reg");
	3730	+
	3731	+ if ((hw->mac_type == e1000_80003es2lan) &&
	3732	+ (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
	3733	+ swfw = E1000_SWFW_PHY1_SM;
	3734	+ } else {
	3735	+ swfw = E1000_SWFW_PHY0_SM;
	3736	+ }
	3737	+ if (e1000_swfw_sync_acquire(hw, swfw))
	3738	+ return -E1000_ERR_SWFW_SYNC;
	3739	+
	3740	+ /* Write register address */
	3741	+ reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
	3742	+ E1000_KUMCTRLSTA_OFFSET) \|
	3743	+ E1000_KUMCTRLSTA_REN;
	3744	+ E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
	3745	+ usec_delay(2);
	3746	+
	3747	+ /* Read the data returned */
	3748	+ reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
	3749	+ *data = (uint16_t)reg_val;
	3750	+
	3751	+ e1000_swfw_sync_release(hw, swfw);
	3752	+ return E1000_SUCCESS;
	3753	+}
	3754	+
	3755	+static int32_t
	3756	+e1000_write_kmrn_reg(struct e1000_hw *hw,
	3757	+ uint32_t reg_addr,
	3758	+ uint16_t data)
	3759	+{
	3760	+ uint32_t reg_val;
	3761	+ uint16_t swfw;
	3762	+ DEBUGFUNC("e1000_write_kmrn_reg");
	3763	+
	3764	+ if ((hw->mac_type == e1000_80003es2lan) &&
	3765	+ (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
	3766	+ swfw = E1000_SWFW_PHY1_SM;
	3767	+ } else {
	3768	+ swfw = E1000_SWFW_PHY0_SM;
	3769	+ }
	3770	+ if (e1000_swfw_sync_acquire(hw, swfw))
	3771	+ return -E1000_ERR_SWFW_SYNC;
	3772	+
	3773	+ reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
	3774	+ E1000_KUMCTRLSTA_OFFSET) \| data;
	3775	+ E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
	3776	+ usec_delay(2);
	3777	+
	3778	+ e1000_swfw_sync_release(hw, swfw);
	3779	+ return E1000_SUCCESS;
	3780	+}
	3781	+
2683	3782	/******************************************************************************
2684	3783	* Returns the PHY to the power-on reset state
2685	3784	*
2686	3785	* hw - Struct containing variables accessed by shared code
2687	3786	******************************************************************************/
2688		-void
	3787	+int32_t
2689	3788	e1000_phy_hw_reset(struct e1000_hw *hw)
2690	3789	{
2691	3790	uint32_t ctrl, ctrl_ext;
2692	3791	uint32_t led_ctrl;
	3792	+ int32_t ret_val;
	3793	+ uint16_t swfw;
2693	3794
2694	3795	DEBUGFUNC("e1000_phy_hw_reset");
2695	3796
	3797	+ /* In the case of the phy reset being blocked, it's not an error, we
	3798	+ * simply return success without performing the reset. */
	3799	+ ret_val = e1000_check_phy_reset_block(hw);
	3800	+ if (ret_val)
	3801	+ return E1000_SUCCESS;
	3802	+
2696	3803	DEBUGOUT("Resetting Phy...\n");
2697	3804
2698		- if(hw->mac_type > e1000_82543) {
	3805	+ if (hw->mac_type > e1000_82543) {
	3806	+ if ((hw->mac_type == e1000_80003es2lan) &&
	3807	+ (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
	3808	+ swfw = E1000_SWFW_PHY1_SM;
	3809	+ } else {
	3810	+ swfw = E1000_SWFW_PHY0_SM;
	3811	+ }
	3812	+ if (e1000_swfw_sync_acquire(hw, swfw)) {
	3813	+ DEBUGOUT("Unable to acquire swfw sync\n");
	3814	+ return -E1000_ERR_SWFW_SYNC;
	3815	+ }
2699	3816	/* Read the device control register and assert the E1000_CTRL_PHY_RST
2700	3817	* bit. Then, take it out of reset.
	3818	+ * For pre-e1000_82571 hardware, we delay for 10ms between the assert
	3819	+ * and deassert. For e1000_82571 hardware and later, we instead delay
	3820	+ * for 50us between and 10ms after the deassertion.
2701	3821	*/
2702	3822	ctrl = E1000_READ_REG(hw, CTRL);
2703	3823	E1000_WRITE_REG(hw, CTRL, ctrl \| E1000_CTRL_PHY_RST);
2704	3824	E1000_WRITE_FLUSH(hw);
2705		- msec_delay(10);
	3825	+
	3826	+ if (hw->mac_type < e1000_82571)
	3827	+ msec_delay(10);
	3828	+ else
	3829	+ usec_delay(100);
	3830	+
2706	3831	E1000_WRITE_REG(hw, CTRL, ctrl);
2707	3832	E1000_WRITE_FLUSH(hw);
	3833	+
	3834	+ if (hw->mac_type >= e1000_82571)
	3835	+ msec_delay_irq(10);
	3836	+
	3837	+ e1000_swfw_sync_release(hw, swfw);
2708	3838	} else {
2709	3839	/* Read the Extended Device Control Register, assert the PHY_RESET_DIR
2710	3840	* bit to put the PHY into reset. Then, take it out of reset.

		@@ -2719,15 +3849,26 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
2719	3849	E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2720	3850	E1000_WRITE_FLUSH(hw);
2721	3851	}
2722		- udelay(150);
	3852	+ usec_delay(150);
2723	3853
2724		- if((hw->mac_type == e1000_82541) \|\| (hw->mac_type == e1000_82547)) {
	3854	+ if ((hw->mac_type == e1000_82541) \|\| (hw->mac_type == e1000_82547)) {
2725	3855	/* Configure activity LED after PHY reset */
2726	3856	led_ctrl = E1000_READ_REG(hw, LEDCTL);
2727	3857	led_ctrl &= IGP_ACTIVITY_LED_MASK;
2728	3858	led_ctrl \|= (IGP_ACTIVITY_LED_ENABLE \| IGP_LED3_MODE);
2729	3859	E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2730	3860	}
	3861	+
	3862	+ /* Wait for FW to finish PHY configuration. */
	3863	+ ret_val = e1000_get_phy_cfg_done(hw);
	3864	+ if (ret_val != E1000_SUCCESS)
	3865	+ return ret_val;
	3866	+ e1000_release_software_semaphore(hw);
	3867	+
	3868	+ if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3))
	3869	+ ret_val = e1000_init_lcd_from_nvm(hw);
	3870	+
	3871	+ return ret_val;
2731	3872	}
2732	3873
2733	3874	/******************************************************************************

		@@ -2745,31 +3886,157 @@ e1000_phy_reset(struct e1000_hw *hw)
2745	3886
2746	3887	DEBUGFUNC("e1000_phy_reset");
2747	3888
2748		- if(hw->mac_type != e1000_82541_rev_2) {
	3889	+ /* In the case of the phy reset being blocked, it's not an error, we
	3890	+ * simply return success without performing the reset. */
	3891	+ ret_val = e1000_check_phy_reset_block(hw);
	3892	+ if (ret_val)
	3893	+ return E1000_SUCCESS;
	3894	+
	3895	+ switch (hw->phy_type) {
	3896	+ case e1000_phy_igp:
	3897	+ case e1000_phy_igp_2:
	3898	+ case e1000_phy_igp_3:
	3899	+ case e1000_phy_ife:
	3900	+ ret_val = e1000_phy_hw_reset(hw);
	3901	+ if (ret_val)
	3902	+ return ret_val;
	3903	+ break;
	3904	+ default:
2749	3905	ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2750		- if(ret_val)
	3906	+ if (ret_val)
2751	3907	return ret_val;
2752	3908
2753	3909	phy_data \|= MII_CR_RESET;
2754	3910	ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
2755		- if(ret_val)
	3911	+ if (ret_val)
2756	3912	return ret_val;
2757	3913
2758		- udelay(1);
2759		- } else e1000_phy_hw_reset(hw);
	3914	+ usec_delay(1);
	3915	+ break;
	3916	+ }
2760	3917
2761		- if(hw->phy_type == e1000_phy_igp)
	3918	+ if (hw->phy_type == e1000_phy_igp \|\| hw->phy_type == e1000_phy_igp_2)
2762	3919	e1000_phy_init_script(hw);
2763	3920
2764	3921	return E1000_SUCCESS;
2765	3922	}
2766	3923
2767	3924	/******************************************************************************
	3925	+* Work-around for 82566 power-down: on D3 entry-
	3926	+* 1) disable gigabit link
	3927	+* 2) write VR power-down enable
	3928	+* 3) read it back
	3929	+* if successful continue, else issue LCD reset and repeat
	3930	+*
	3931	+* hw - struct containing variables accessed by shared code
	3932	+******************************************************************************/
	3933	+void
	3934	+e1000_phy_powerdown_workaround(struct e1000_hw *hw)
	3935	+{
	3936	+ int32_t reg;
	3937	+ uint16_t phy_data;
	3938	+ int32_t retry = 0;
	3939	+
	3940	+ DEBUGFUNC("e1000_phy_powerdown_workaround");
	3941	+
	3942	+ if (hw->phy_type != e1000_phy_igp_3)
	3943	+ return;
	3944	+
	3945	+ do {
	3946	+ /* Disable link */
	3947	+ reg = E1000_READ_REG(hw, PHY_CTRL);
	3948	+ E1000_WRITE_REG(hw, PHY_CTRL, reg \| E1000_PHY_CTRL_GBE_DISABLE \|
	3949	+ E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
	3950	+
	3951	+ /* Write VR power-down enable - bits 9:8 should be 10b */
	3952	+ e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
	3953	+ phy_data \|= (1 << 9);
	3954	+ phy_data &= ~(1 << 8);
	3955	+ e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data);
	3956	+
	3957	+ /* Read it back and test */
	3958	+ e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
	3959	+ if (((phy_data & IGP3_VR_CTRL_MODE_MASK) == IGP3_VR_CTRL_MODE_SHUT) \|\| retry)
	3960	+ break;
	3961	+
	3962	+ /* Issue PHY reset and repeat at most one more time */
	3963	+ reg = E1000_READ_REG(hw, CTRL);
	3964	+ E1000_WRITE_REG(hw, CTRL, reg \| E1000_CTRL_PHY_RST);
	3965	+ retry++;
	3966	+ } while (retry);
	3967	+
	3968	+ return;
	3969	+
	3970	+}
	3971	+
	3972	+/******************************************************************************
	3973	+* Work-around for 82566 Kumeran PCS lock loss:
	3974	+* On link status change (i.e. PCI reset, speed change) and link is up and
	3975	+* speed is gigabit-
	3976	+* 0) if workaround is optionally disabled do nothing
	3977	+* 1) wait 1ms for Kumeran link to come up
	3978	+* 2) check Kumeran Diagnostic register PCS lock loss bit
	3979	+* 3) if not set the link is locked (all is good), otherwise...
	3980	+* 4) reset the PHY
	3981	+* 5) repeat up to 10 times
	3982	+* Note: this is only called for IGP3 copper when speed is 1gb.
	3983	+*
	3984	+* hw - struct containing variables accessed by shared code
	3985	+******************************************************************************/
	3986	+static int32_t
	3987	+e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
	3988	+{
	3989	+ int32_t ret_val;
	3990	+ int32_t reg;
	3991	+ int32_t cnt;
	3992	+ uint16_t phy_data;
	3993	+
	3994	+ if (hw->kmrn_lock_loss_workaround_disabled)
	3995	+ return E1000_SUCCESS;
	3996	+
	3997	+ /* Make sure link is up before proceeding. If not just return.
	3998	+ * Attempting this while link is negotiating fouled up link
	3999	+ * stability */
	4000	+ ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
	4001	+ ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
	4002	+
	4003	+ if (phy_data & MII_SR_LINK_STATUS) {
	4004	+ for (cnt = 0; cnt < 10; cnt++) {
	4005	+ /* read once to clear */
	4006	+ ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
	4007	+ if (ret_val)
	4008	+ return ret_val;
	4009	+ /* and again to get new status */
	4010	+ ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
	4011	+ if (ret_val)
	4012	+ return ret_val;
	4013	+
	4014	+ /* check for PCS lock */
	4015	+ if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
	4016	+ return E1000_SUCCESS;
	4017	+
	4018	+ /* Issue PHY reset */
	4019	+ e1000_phy_hw_reset(hw);
	4020	+ msec_delay_irq(5);
	4021	+ }
	4022	+ /* Disable GigE link negotiation */
	4023	+ reg = E1000_READ_REG(hw, PHY_CTRL);
	4024	+ E1000_WRITE_REG(hw, PHY_CTRL, reg \| E1000_PHY_CTRL_GBE_DISABLE \|
	4025	+ E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
	4026	+
	4027	+ /* unable to acquire PCS lock */
	4028	+ return E1000_ERR_PHY;
	4029	+ }
	4030	+
	4031	+ return E1000_SUCCESS;
	4032	+}
	4033	+
	4034	+/******************************************************************************
2768	4035	* Probes the expected PHY address for known PHY IDs
2769	4036	*
2770	4037	* hw - Struct containing variables accessed by shared code
2771	4038	******************************************************************************/
2772		-int32_t
	4039	+static int32_t
2773	4040	e1000_detect_gig_phy(struct e1000_hw *hw)
2774	4041	{
2775	4042	int32_t phy_init_status, ret_val;

		@@ -2778,39 +4045,73 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
2778	4045
2779	4046	DEBUGFUNC("e1000_detect_gig_phy");
2780	4047
	4048	+ if (hw->phy_id != 0)
	4049	+ return E1000_SUCCESS;
	4050	+
	4051	+ /* The 82571 firmware may still be configuring the PHY. In this
	4052	+ * case, we cannot access the PHY until the configuration is done. So
	4053	+ * we explicitly set the PHY values. */
	4054	+ if (hw->mac_type == e1000_82571 \|\|
	4055	+ hw->mac_type == e1000_82572) {
	4056	+ hw->phy_id = IGP01E1000_I_PHY_ID;
	4057	+ hw->phy_type = e1000_phy_igp_2;
	4058	+ return E1000_SUCCESS;
	4059	+ }
	4060	+
	4061	+ /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work-
	4062	+ * around that forces PHY page 0 to be set or the reads fail. The rest of
	4063	+ * the code in this routine uses e1000_read_phy_reg to read the PHY ID.
	4064	+ * So for ESB-2 we need to have this set so our reads won't fail. If the
	4065	+ * attached PHY is not a e1000_phy_gg82563, the routines below will figure
	4066	+ * this out as well. */
	4067	+ if (hw->mac_type == e1000_80003es2lan)
	4068	+ hw->phy_type = e1000_phy_gg82563;
	4069	+
2781	4070	/* Read the PHY ID Registers to identify which PHY is onboard. */
2782	4071	ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
2783		- if(ret_val)
	4072	+ if (ret_val)
2784	4073	return ret_val;
2785	4074
2786	4075	hw->phy_id = (uint32_t) (phy_id_high << 16);
2787		- udelay(20);
	4076	+ usec_delay(20);
2788	4077	ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
2789		- if(ret_val)
	4078	+ if (ret_val)
2790	4079	return ret_val;
2791	4080
2792	4081	hw->phy_id \|= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
2793	4082	hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
2794	4083
2795		- switch(hw->mac_type) {
	4084	+ switch (hw->mac_type) {
2796	4085	case e1000_82543:
2797		- if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
	4086	+ if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
2798	4087	break;
2799	4088	case e1000_82544:
2800		- if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
	4089	+ if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
2801	4090	break;
2802	4091	case e1000_82540:
2803	4092	case e1000_82545:
2804	4093	case e1000_82545_rev_3:
2805	4094	case e1000_82546:
2806	4095	case e1000_82546_rev_3:
2807		- if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
	4096	+ if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
2808	4097	break;
2809	4098	case e1000_82541:
2810	4099	case e1000_82541_rev_2:
2811	4100	case e1000_82547:
2812	4101	case e1000_82547_rev_2:
2813		- if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
	4102	+ if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
	4103	+ break;
	4104	+ case e1000_82573:
	4105	+ if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
	4106	+ break;
	4107	+ case e1000_80003es2lan:
	4108	+ if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
	4109	+ break;
	4110	+ case e1000_ich8lan:
	4111	+ if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE;
	4112	+ if (hw->phy_id == IFE_E_PHY_ID) match = TRUE;
	4113	+ if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE;
	4114	+ if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE;
2814	4115	break;
2815	4116	default:
2816	4117	DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);

		@@ -2838,14 +4139,16 @@ e1000_phy_reset_dsp(struct e1000_hw *hw)
2838	4139	DEBUGFUNC("e1000_phy_reset_dsp");
2839	4140
2840	4141	do {
2841		- ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
2842		- if(ret_val) break;
	4142	+ if (hw->phy_type != e1000_phy_gg82563) {
	4143	+ ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
	4144	+ if (ret_val) break;
	4145	+ }
2843	4146	ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
2844		- if(ret_val) break;
	4147	+ if (ret_val) break;
2845	4148	ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
2846		- if(ret_val) break;
	4149	+ if (ret_val) break;
2847	4150	ret_val = E1000_SUCCESS;
2848		- } while(0);
	4151	+ } while (0);
2849	4152
2850	4153	return ret_val;
2851	4154	}

		@@ -2856,18 +4159,19 @@ e1000_phy_reset_dsp(struct e1000_hw *hw)
2856	4159	* hw - Struct containing variables accessed by shared code
2857	4160	* phy_info - PHY information structure
2858	4161	******************************************************************************/
2859		-int32_t
	4162	+static int32_t
2860	4163	e1000_phy_igp_get_info(struct e1000_hw *hw,
2861	4164	struct e1000_phy_info *phy_info)
2862	4165	{
2863	4166	int32_t ret_val;
2864		- uint16_t phy_data, polarity, min_length, max_length, average;
	4167	+ uint16_t phy_data, min_length, max_length, average;
	4168	+ e1000_rev_polarity polarity;
2865	4169
2866	4170	DEBUGFUNC("e1000_phy_igp_get_info");
2867	4171
2868	4172	/* The downshift status is checked only once, after link is established,
2869	4173	* and it stored in the hw->speed_downgraded parameter. */
2870		- phy_info->downshift = hw->speed_downgraded;
	4174	+ phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
2871	4175
2872	4176	/* IGP01E1000 does not need to support it. */
2873	4177	phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;

		@@ -2877,45 +4181,47 @@ e1000_phy_igp_get_info(struct e1000_hw *hw,
2877	4181
2878	4182	/* Check polarity status */
2879	4183	ret_val = e1000_check_polarity(hw, &polarity);
2880		- if(ret_val)
	4184	+ if (ret_val)
2881	4185	return ret_val;
2882	4186
2883	4187	phy_info->cable_polarity = polarity;
2884	4188
2885	4189	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
2886		- if(ret_val)
	4190	+ if (ret_val)
2887	4191	return ret_val;
2888	4192
2889		- phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >>
2890		- IGP01E1000_PSSR_MDIX_SHIFT;
	4193	+ phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >>
	4194	+ IGP01E1000_PSSR_MDIX_SHIFT);
2891	4195
2892		- if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
	4196	+ if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
2893	4197	IGP01E1000_PSSR_SPEED_1000MBPS) {
2894	4198	/* Local/Remote Receiver Information are only valid at 1000 Mbps */
2895	4199	ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
2896		- if(ret_val)
	4200	+ if (ret_val)
2897	4201	return ret_val;
2898	4202
2899		- phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
2900		- SR_1000T_LOCAL_RX_STATUS_SHIFT;
2901		- phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
2902		- SR_1000T_REMOTE_RX_STATUS_SHIFT;
	4203	+ phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
	4204	+ SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
	4205	+ e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
	4206	+ phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
	4207	+ SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
	4208	+ e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
2903	4209
2904	4210	/* Get cable length */
2905	4211	ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
2906		- if(ret_val)
	4212	+ if (ret_val)
2907	4213	return ret_val;
2908	4214
2909		- /* transalte to old method */
	4215	+ /* Translate to old method */
2910	4216	average = (max_length + min_length) / 2;
2911	4217
2912		- if(average <= e1000_igp_cable_length_50)
	4218	+ if (average <= e1000_igp_cable_length_50)
2913	4219	phy_info->cable_length = e1000_cable_length_50;
2914		- else if(average <= e1000_igp_cable_length_80)
	4220	+ else if (average <= e1000_igp_cable_length_80)
2915	4221	phy_info->cable_length = e1000_cable_length_50_80;
2916		- else if(average <= e1000_igp_cable_length_110)
	4222	+ else if (average <= e1000_igp_cable_length_110)
2917	4223	phy_info->cable_length = e1000_cable_length_80_110;
2918		- else if(average <= e1000_igp_cable_length_140)
	4224	+ else if (average <= e1000_igp_cable_length_140)
2919	4225	phy_info->cable_length = e1000_cable_length_110_140;
2920	4226	else
2921	4227	phy_info->cable_length = e1000_cable_length_140;

		@@ -2925,64 +4231,129 @@ e1000_phy_igp_get_info(struct e1000_hw *hw,
2925	4231	}
2926	4232
2927	4233	/******************************************************************************
	4234	+* Get PHY information from various PHY registers for ife PHY only.
	4235	+*
	4236	+* hw - Struct containing variables accessed by shared code
	4237	+* phy_info - PHY information structure
	4238	+******************************************************************************/
	4239	+static int32_t
	4240	+e1000_phy_ife_get_info(struct e1000_hw *hw,
	4241	+ struct e1000_phy_info *phy_info)
	4242	+{
	4243	+ int32_t ret_val;
	4244	+ uint16_t phy_data;
	4245	+ e1000_rev_polarity polarity;
	4246	+
	4247	+ DEBUGFUNC("e1000_phy_ife_get_info");
	4248	+
	4249	+ phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
	4250	+ phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
	4251	+
	4252	+ ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
	4253	+ if (ret_val)
	4254	+ return ret_val;
	4255	+ phy_info->polarity_correction =
	4256	+ ((phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >>
	4257	+ IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT) ?
	4258	+ e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
	4259	+
	4260	+ if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) {
	4261	+ ret_val = e1000_check_polarity(hw, &polarity);
	4262	+ if (ret_val)
	4263	+ return ret_val;
	4264	+ } else {
	4265	+ /* Polarity is forced. */
	4266	+ polarity = ((phy_data & IFE_PSC_FORCE_POLARITY) >>
	4267	+ IFE_PSC_FORCE_POLARITY_SHIFT) ?
	4268	+ e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
	4269	+ }
	4270	+ phy_info->cable_polarity = polarity;
	4271	+
	4272	+ ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
	4273	+ if (ret_val)
	4274	+ return ret_val;
	4275	+
	4276	+ phy_info->mdix_mode = (e1000_auto_x_mode)
	4277	+ ((phy_data & (IFE_PMC_AUTO_MDIX \| IFE_PMC_FORCE_MDIX)) >>
	4278	+ IFE_PMC_MDIX_MODE_SHIFT);
	4279	+
	4280	+ return E1000_SUCCESS;
	4281	+}
	4282	+
	4283	+/******************************************************************************
2928	4284	* Get PHY information from various PHY registers fot m88 PHY only.
2929	4285	*
2930	4286	* hw - Struct containing variables accessed by shared code
2931	4287	* phy_info - PHY information structure
2932	4288	******************************************************************************/
2933		-int32_t
	4289	+static int32_t
2934	4290	e1000_phy_m88_get_info(struct e1000_hw *hw,
2935	4291	struct e1000_phy_info *phy_info)
2936	4292	{
2937	4293	int32_t ret_val;
2938		- uint16_t phy_data, polarity;
	4294	+ uint16_t phy_data;
	4295	+ e1000_rev_polarity polarity;
2939	4296
2940	4297	DEBUGFUNC("e1000_phy_m88_get_info");
2941	4298
2942	4299	/* The downshift status is checked only once, after link is established,
2943	4300	* and it stored in the hw->speed_downgraded parameter. */
2944		- phy_info->downshift = hw->speed_downgraded;
	4301	+ phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
2945	4302
2946	4303	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2947		- if(ret_val)
	4304	+ if (ret_val)
2948	4305	return ret_val;
2949	4306
2950	4307	phy_info->extended_10bt_distance =
2951		- (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
2952		- M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT;
	4308	+ ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
	4309	+ M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
	4310	+ e1000_10bt_ext_dist_enable_lower : e1000_10bt_ext_dist_enable_normal;
	4311	+
2953	4312	phy_info->polarity_correction =
2954		- (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
2955		- M88E1000_PSCR_POLARITY_REVERSAL_SHIFT;
	4313	+ ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
	4314	+ M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
	4315	+ e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
2956	4316
2957	4317	/* Check polarity status */
2958	4318	ret_val = e1000_check_polarity(hw, &polarity);
2959		- if(ret_val)
2960		- return ret_val;
	4319	+ if (ret_val)
	4320	+ return ret_val;
2961	4321	phy_info->cable_polarity = polarity;
2962	4322
2963	4323	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2964		- if(ret_val)
	4324	+ if (ret_val)
2965	4325	return ret_val;
2966	4326
2967		- phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
2968		- M88E1000_PSSR_MDIX_SHIFT;
	4327	+ phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >>
	4328	+ M88E1000_PSSR_MDIX_SHIFT);
2969	4329
2970	4330	if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2971	4331	/* Cable Length Estimation and Local/Remote Receiver Information
2972	4332	* are only valid at 1000 Mbps.
2973	4333	*/
2974		- phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2975		- M88E1000_PSSR_CABLE_LENGTH_SHIFT);
	4334	+ if (hw->phy_type != e1000_phy_gg82563) {
	4335	+ phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
	4336	+ M88E1000_PSSR_CABLE_LENGTH_SHIFT);
	4337	+ } else {
	4338	+ ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
	4339	+ &phy_data);
	4340	+ if (ret_val)
	4341	+ return ret_val;
	4342	+
	4343	+ phy_info->cable_length = (e1000_cable_length)(phy_data & GG82563_DSPD_CABLE_LENGTH);
	4344	+ }
2976	4345
2977	4346	ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
2978		- if(ret_val)
	4347	+ if (ret_val)
2979	4348	return ret_val;
2980	4349
2981		- phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
2982		- SR_1000T_LOCAL_RX_STATUS_SHIFT;
	4350	+ phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
	4351	+ SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
	4352	+ e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
	4353	+ phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
	4354	+ SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
	4355	+ e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
2983	4356
2984		- phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
2985		- SR_1000T_REMOTE_RX_STATUS_SHIFT;
2986	4357	}
2987	4358
2988	4359	return E1000_SUCCESS;

		@@ -3012,26 +4383,30 @@ e1000_phy_get_info(struct e1000_hw *hw,
3012	4383	phy_info->local_rx = e1000_1000t_rx_status_undefined;
3013	4384	phy_info->remote_rx = e1000_1000t_rx_status_undefined;
3014	4385
3015		- if(hw->media_type != e1000_media_type_copper) {
	4386	+ if (hw->media_type != e1000_media_type_copper) {
3016	4387	DEBUGOUT("PHY info is only valid for copper media\n");
3017	4388	return -E1000_ERR_CONFIG;
3018	4389	}
3019	4390
3020	4391	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3021		- if(ret_val)
	4392	+ if (ret_val)
3022	4393	return ret_val;
3023	4394
3024	4395	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3025		- if(ret_val)
	4396	+ if (ret_val)
3026	4397	return ret_val;
3027	4398
3028		- if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
	4399	+ if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
3029	4400	DEBUGOUT("PHY info is only valid if link is up\n");
3030	4401	return -E1000_ERR_CONFIG;
3031	4402	}
3032	4403
3033		- if(hw->phy_type == e1000_phy_igp)
	4404	+ if (hw->phy_type == e1000_phy_igp \|\|
	4405	+ hw->phy_type == e1000_phy_igp_3 \|\|
	4406	+ hw->phy_type == e1000_phy_igp_2)
3034	4407	return e1000_phy_igp_get_info(hw, phy_info);
	4408	+ else if (hw->phy_type == e1000_phy_ife)
	4409	+ return e1000_phy_ife_get_info(hw, phy_info);
3035	4410	else
3036	4411	return e1000_phy_m88_get_info(hw, phy_info);
3037	4412	}

		@@ -3041,7 +4416,7 @@ e1000_validate_mdi_setting(struct e1000_hw *hw)
3041	4416	{
3042	4417	DEBUGFUNC("e1000_validate_mdi_settings");
3043	4418
3044		- if(!hw->autoneg && (hw->mdix == 0 \|\| hw->mdix == 3)) {
	4419	+ if (!hw->autoneg && (hw->mdix == 0 \|\| hw->mdix == 3)) {
3045	4420	DEBUGOUT("Invalid MDI setting detected\n");
3046	4421	hw->mdix = 1;
3047	4422	return -E1000_ERR_CONFIG;

		@@ -3052,15 +4427,17 @@ e1000_validate_mdi_setting(struct e1000_hw *hw)
3052	4427
3053	4428	/******************************************************************************
3054	4429	* Sets up eeprom variables in the hw struct. Must be called after mac_type
3055		- * is configured.
	4430	+ * is configured. Additionally, if this is ICH8, the flash controller GbE
	4431	+ * registers must be mapped, or this will crash.
3056	4432	*
3057	4433	* hw - Struct containing variables accessed by shared code
3058	4434	*****************************************************************************/
3059		-void
	4435	+int32_t
3060	4436	e1000_init_eeprom_params(struct e1000_hw *hw)
3061	4437	{
3062	4438	struct e1000_eeprom_info *eeprom = &hw->eeprom;
3063	4439	uint32_t eecd = E1000_READ_REG(hw, EECD);
	4440	+ int32_t ret_val = E1000_SUCCESS;
3064	4441	uint16_t eeprom_size;
3065	4442
3066	4443	DEBUGFUNC("e1000_init_eeprom_params");

		@@ -3075,6 +4452,8 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
3075	4452	eeprom->opcode_bits = 3;
3076	4453	eeprom->address_bits = 6;
3077	4454	eeprom->delay_usec = 50;
	4455	+ eeprom->use_eerd = FALSE;
	4456	+ eeprom->use_eewr = FALSE;
3078	4457	break;
3079	4458	case e1000_82540:
3080	4459	case e1000_82545:

		@@ -3084,13 +4463,15 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
3084	4463	eeprom->type = e1000_eeprom_microwire;
3085	4464	eeprom->opcode_bits = 3;
3086	4465	eeprom->delay_usec = 50;
3087		- if(eecd & E1000_EECD_SIZE) {
	4466	+ if (eecd & E1000_EECD_SIZE) {
3088	4467	eeprom->word_size = 256;
3089	4468	eeprom->address_bits = 8;
3090	4469	} else {
3091	4470	eeprom->word_size = 64;
3092	4471	eeprom->address_bits = 6;
3093	4472	}
	4473	+ eeprom->use_eerd = FALSE;
	4474	+ eeprom->use_eewr = FALSE;
3094	4475	break;
3095	4476	case e1000_82541:
3096	4477	case e1000_82541_rev_2:

		@@ -3119,42 +4500,119 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
3119	4500	eeprom->address_bits = 6;
3120	4501	}
3121	4502	}
	4503	+ eeprom->use_eerd = FALSE;
	4504	+ eeprom->use_eewr = FALSE;
3122	4505	break;
3123		- default:
	4506	+ case e1000_82571:
	4507	+ case e1000_82572:
	4508	+ eeprom->type = e1000_eeprom_spi;
	4509	+ eeprom->opcode_bits = 8;
	4510	+ eeprom->delay_usec = 1;
	4511	+ if (eecd & E1000_EECD_ADDR_BITS) {
	4512	+ eeprom->page_size = 32;
	4513	+ eeprom->address_bits = 16;
	4514	+ } else {
	4515	+ eeprom->page_size = 8;
	4516	+ eeprom->address_bits = 8;
	4517	+ }
	4518	+ eeprom->use_eerd = FALSE;
	4519	+ eeprom->use_eewr = FALSE;
3124	4520	break;
3125		- }
	4521	+ case e1000_82573:
	4522	+ eeprom->type = e1000_eeprom_spi;
	4523	+ eeprom->opcode_bits = 8;
	4524	+ eeprom->delay_usec = 1;
	4525	+ if (eecd & E1000_EECD_ADDR_BITS) {
	4526	+ eeprom->page_size = 32;
	4527	+ eeprom->address_bits = 16;
	4528	+ } else {
	4529	+ eeprom->page_size = 8;
	4530	+ eeprom->address_bits = 8;
	4531	+ }
	4532	+ eeprom->use_eerd = TRUE;
	4533	+ eeprom->use_eewr = TRUE;
	4534	+ if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
	4535	+ eeprom->type = e1000_eeprom_flash;
	4536	+ eeprom->word_size = 2048;
	4537	+
	4538	+ /* Ensure that the Autonomous FLASH update bit is cleared due to
	4539	+ * Flash update issue on parts which use a FLASH for NVM. */
	4540	+ eecd &= ~E1000_EECD_AUPDEN;
	4541	+ E1000_WRITE_REG(hw, EECD, eecd);
	4542	+ }
	4543	+ break;
	4544	+ case e1000_80003es2lan:
	4545	+ eeprom->type = e1000_eeprom_spi;
	4546	+ eeprom->opcode_bits = 8;
	4547	+ eeprom->delay_usec = 1;
	4548	+ if (eecd & E1000_EECD_ADDR_BITS) {
	4549	+ eeprom->page_size = 32;
	4550	+ eeprom->address_bits = 16;
	4551	+ } else {
	4552	+ eeprom->page_size = 8;
	4553	+ eeprom->address_bits = 8;
	4554	+ }
	4555	+ eeprom->use_eerd = TRUE;
	4556	+ eeprom->use_eewr = FALSE;
	4557	+ break;
	4558	+ case e1000_ich8lan:
	4559	+ {
	4560	+ int32_t i = 0;
	4561	+ uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG);
	4562	+
	4563	+ eeprom->type = e1000_eeprom_ich8;
	4564	+ eeprom->use_eerd = FALSE;
	4565	+ eeprom->use_eewr = FALSE;
	4566	+ eeprom->word_size = E1000_SHADOW_RAM_WORDS;
	4567	+
	4568	+ /* Zero the shadow RAM structure. But don't load it from NVM
	4569	+ * so as to save time for driver init */
	4570	+ if (hw->eeprom_shadow_ram != NULL) {
	4571	+ for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
	4572	+ hw->eeprom_shadow_ram[i].modified = FALSE;
	4573	+ hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
	4574	+ }
	4575	+ }
3126	4576
3127		- if (eeprom->type == e1000_eeprom_spi) {
3128		- eeprom->word_size = 64;
3129		- if (e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size) == 0) {
3130		- eeprom_size &= EEPROM_SIZE_MASK;
	4577	+ hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
	4578	+ ICH_FLASH_SECTOR_SIZE;
3131	4579
3132		- switch (eeprom_size) {
3133		- case EEPROM_SIZE_16KB:
3134		- eeprom->word_size = 8192;
3135		- break;
3136		- case EEPROM_SIZE_8KB:
3137		- eeprom->word_size = 4096;
3138		- break;
3139		- case EEPROM_SIZE_4KB:
3140		- eeprom->word_size = 2048;
3141		- break;
3142		- case EEPROM_SIZE_2KB:
3143		- eeprom->word_size = 1024;
3144		- break;
3145		- case EEPROM_SIZE_1KB:
3146		- eeprom->word_size = 512;
3147		- break;
3148		- case EEPROM_SIZE_512B:
3149		- eeprom->word_size = 256;
3150		- break;
3151		- case EEPROM_SIZE_128B:
3152		- default:
3153		- eeprom->word_size = 64;
3154		- break;
3155		- }
	4580	+ hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1;
	4581	+ hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
	4582	+
	4583	+ hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
	4584	+
	4585	+ hw->flash_bank_size /= 2 * sizeof(uint16_t);
	4586	+ break;
	4587	+ }
	4588	+ default:
	4589	+ break;
	4590	+ }
	4591	+
	4592	+ if (eeprom->type == e1000_eeprom_spi) {
	4593	+ /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
	4594	+ * 32KB (incremented by powers of 2).
	4595	+ */
	4596	+ if (hw->mac_type <= e1000_82547_rev_2) {
	4597	+ /* Set to default value for initial eeprom read. */
	4598	+ eeprom->word_size = 64;
	4599	+ ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
	4600	+ if (ret_val)
	4601	+ return ret_val;
	4602	+ eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
	4603	+ /* 256B eeprom size was not supported in earlier hardware, so we
	4604	+ * bump eeprom_size up one to ensure that "1" (which maps to 256B)
	4605	+ * is never the result used in the shifting logic below. */
	4606	+ if (eeprom_size)
	4607	+ eeprom_size++;
	4608	+ } else {
	4609	+ eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
	4610	+ E1000_EECD_SIZE_EX_SHIFT);
3156	4611	}
	4612	+
	4613	+ eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
3157	4614	}
	4615	+ return ret_val;
3158	4616	}
3159	4617
3160	4618	/******************************************************************************

		@@ -3173,7 +4631,7 @@ e1000_raise_ee_clk(struct e1000_hw *hw,
3173	4631	eecd = eecd \| E1000_EECD_SK;
3174	4632	E1000_WRITE_REG(hw, EECD, *eecd);
3175	4633	E1000_WRITE_FLUSH(hw);
3176		- udelay(hw->eeprom.delay_usec);
	4634	+ usec_delay(hw->eeprom.delay_usec);
3177	4635	}
3178	4636
3179	4637	/******************************************************************************

		@@ -3192,7 +4650,7 @@ e1000_lower_ee_clk(struct e1000_hw *hw,
3192	4650	eecd = eecd & ~E1000_EECD_SK;
3193	4651	E1000_WRITE_REG(hw, EECD, *eecd);
3194	4652	E1000_WRITE_FLUSH(hw);
3195		- udelay(hw->eeprom.delay_usec);
	4653	+ usec_delay(hw->eeprom.delay_usec);
3196	4654	}
3197	4655
3198	4656	/******************************************************************************

		@@ -3230,20 +4688,20 @@ e1000_shift_out_ee_bits(struct e1000_hw *hw,
3230	4688	*/
3231	4689	eecd &= ~E1000_EECD_DI;
3232	4690
3233		- if(data & mask)
	4691	+ if (data & mask)
3234	4692	eecd \|= E1000_EECD_DI;
3235	4693
3236	4694	E1000_WRITE_REG(hw, EECD, eecd);
3237	4695	E1000_WRITE_FLUSH(hw);
3238	4696
3239		- udelay(eeprom->delay_usec);
	4697	+ usec_delay(eeprom->delay_usec);
3240	4698
3241	4699	e1000_raise_ee_clk(hw, &eecd);
3242	4700	e1000_lower_ee_clk(hw, &eecd);
3243	4701
3244	4702	mask = mask >> 1;
3245	4703
3246		- } while(mask);
	4704	+ } while (mask);
3247	4705
3248	4706	/* We leave the "DI" bit set to "0" when we leave this routine. */
3249	4707	eecd &= ~E1000_EECD_DI;

		@@ -3275,14 +4733,14 @@ e1000_shift_in_ee_bits(struct e1000_hw *hw,
3275	4733	eecd &= ~(E1000_EECD_DO \| E1000_EECD_DI);
3276	4734	data = 0;
3277	4735
3278		- for(i = 0; i < count; i++) {
	4736	+ for (i = 0; i < count; i++) {
3279	4737	data = data << 1;
3280	4738	e1000_raise_ee_clk(hw, &eecd);
3281	4739
3282	4740	eecd = E1000_READ_REG(hw, EECD);
3283	4741
3284	4742	eecd &= ~(E1000_EECD_DI);
3285		- if(eecd & E1000_EECD_DO)
	4743	+ if (eecd & E1000_EECD_DO)
3286	4744	data \|= 1;
3287	4745
3288	4746	e1000_lower_ee_clk(hw, &eecd);

		@@ -3307,24 +4765,29 @@ e1000_acquire_eeprom(struct e1000_hw *hw)
3307	4765
3308	4766	DEBUGFUNC("e1000_acquire_eeprom");
3309	4767
	4768	+ if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
	4769	+ return -E1000_ERR_SWFW_SYNC;
3310	4770	eecd = E1000_READ_REG(hw, EECD);
3311	4771
3312		- /* Request EEPROM Access */
3313		- if(hw->mac_type > e1000_82544) {
3314		- eecd \|= E1000_EECD_REQ;
3315		- E1000_WRITE_REG(hw, EECD, eecd);
3316		- eecd = E1000_READ_REG(hw, EECD);
3317		- while((!(eecd & E1000_EECD_GNT)) &&
3318		- (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
3319		- i++;
3320		- udelay(5);
3321		- eecd = E1000_READ_REG(hw, EECD);
3322		- }
3323		- if(!(eecd & E1000_EECD_GNT)) {
3324		- eecd &= ~E1000_EECD_REQ;
	4772	+ if (hw->mac_type != e1000_82573) {
	4773	+ /* Request EEPROM Access */
	4774	+ if (hw->mac_type > e1000_82544) {
	4775	+ eecd \|= E1000_EECD_REQ;
3325	4776	E1000_WRITE_REG(hw, EECD, eecd);
3326		- DEBUGOUT("Could not acquire EEPROM grant\n");
3327		- return -E1000_ERR_EEPROM;
	4777	+ eecd = E1000_READ_REG(hw, EECD);
	4778	+ while ((!(eecd & E1000_EECD_GNT)) &&
	4779	+ (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
	4780	+ i++;
	4781	+ usec_delay(5);
	4782	+ eecd = E1000_READ_REG(hw, EECD);
	4783	+ }
	4784	+ if (!(eecd & E1000_EECD_GNT)) {
	4785	+ eecd &= ~E1000_EECD_REQ;
	4786	+ E1000_WRITE_REG(hw, EECD, eecd);
	4787	+ DEBUGOUT("Could not acquire EEPROM grant\n");
	4788	+ e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
	4789	+ return -E1000_ERR_EEPROM;
	4790	+ }
3328	4791	}
3329	4792	}
3330	4793

		@@ -3342,7 +4805,7 @@ e1000_acquire_eeprom(struct e1000_hw *hw)
3342	4805	/* Clear SK and CS */
3343	4806	eecd &= ~(E1000_EECD_CS \| E1000_EECD_SK);
3344	4807	E1000_WRITE_REG(hw, EECD, eecd);
3345		- udelay(1);
	4808	+ usec_delay(1);
3346	4809	}
3347	4810
3348	4811	return E1000_SUCCESS;

		@@ -3361,39 +4824,39 @@ e1000_standby_eeprom(struct e1000_hw *hw)
3361	4824
3362	4825	eecd = E1000_READ_REG(hw, EECD);
3363	4826
3364		- if(eeprom->type == e1000_eeprom_microwire) {
	4827	+ if (eeprom->type == e1000_eeprom_microwire) {
3365	4828	eecd &= ~(E1000_EECD_CS \| E1000_EECD_SK);
3366	4829	E1000_WRITE_REG(hw, EECD, eecd);
3367	4830	E1000_WRITE_FLUSH(hw);
3368		- udelay(eeprom->delay_usec);
	4831	+ usec_delay(eeprom->delay_usec);
3369	4832
3370	4833	/* Clock high */
3371	4834	eecd \|= E1000_EECD_SK;
3372	4835	E1000_WRITE_REG(hw, EECD, eecd);
3373	4836	E1000_WRITE_FLUSH(hw);
3374		- udelay(eeprom->delay_usec);
	4837	+ usec_delay(eeprom->delay_usec);
3375	4838
3376	4839	/* Select EEPROM */
3377	4840	eecd \|= E1000_EECD_CS;
3378	4841	E1000_WRITE_REG(hw, EECD, eecd);
3379	4842	E1000_WRITE_FLUSH(hw);
3380		- udelay(eeprom->delay_usec);
	4843	+ usec_delay(eeprom->delay_usec);
3381	4844
3382	4845	/* Clock low */
3383	4846	eecd &= ~E1000_EECD_SK;
3384	4847	E1000_WRITE_REG(hw, EECD, eecd);
3385	4848	E1000_WRITE_FLUSH(hw);
3386		- udelay(eeprom->delay_usec);
3387		- } else if(eeprom->type == e1000_eeprom_spi) {
	4849	+ usec_delay(eeprom->delay_usec);
	4850	+ } else if (eeprom->type == e1000_eeprom_spi) {
3388	4851	/* Toggle CS to flush commands */
3389	4852	eecd \|= E1000_EECD_CS;
3390	4853	E1000_WRITE_REG(hw, EECD, eecd);
3391	4854	E1000_WRITE_FLUSH(hw);
3392		- udelay(eeprom->delay_usec);
	4855	+ usec_delay(eeprom->delay_usec);
3393	4856	eecd &= ~E1000_EECD_CS;
3394	4857	E1000_WRITE_REG(hw, EECD, eecd);
3395	4858	E1000_WRITE_FLUSH(hw);
3396		- udelay(eeprom->delay_usec);
	4859	+ usec_delay(eeprom->delay_usec);
3397	4860	}
3398	4861	}
3399	4862

		@@ -3417,8 +4880,8 @@ e1000_release_eeprom(struct e1000_hw *hw)
3417	4880
3418	4881	E1000_WRITE_REG(hw, EECD, eecd);
3419	4882
3420		- udelay(hw->eeprom.delay_usec);
3421		- } else if(hw->eeprom.type == e1000_eeprom_microwire) {
	4883	+ usec_delay(hw->eeprom.delay_usec);
	4884	+ } else if (hw->eeprom.type == e1000_eeprom_microwire) {
3422	4885	/* cleanup eeprom */
3423	4886
3424	4887	/* CS on Microwire is active-high */

		@@ -3430,20 +4893,22 @@ e1000_release_eeprom(struct e1000_hw *hw)
3430	4893	eecd \|= E1000_EECD_SK;
3431	4894	E1000_WRITE_REG(hw, EECD, eecd);
3432	4895	E1000_WRITE_FLUSH(hw);
3433		- udelay(hw->eeprom.delay_usec);
	4896	+ usec_delay(hw->eeprom.delay_usec);
3434	4897
3435	4898	/* Falling edge of clock */
3436	4899	eecd &= ~E1000_EECD_SK;
3437	4900	E1000_WRITE_REG(hw, EECD, eecd);
3438	4901	E1000_WRITE_FLUSH(hw);
3439		- udelay(hw->eeprom.delay_usec);
	4902	+ usec_delay(hw->eeprom.delay_usec);
3440	4903	}
3441	4904
3442	4905	/* Stop requesting EEPROM access */
3443		- if(hw->mac_type > e1000_82544) {
	4906	+ if (hw->mac_type > e1000_82544) {
3444	4907	eecd &= ~E1000_EECD_REQ;
3445	4908	E1000_WRITE_REG(hw, EECD, eecd);
3446	4909	}
	4910	+
	4911	+ e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
3447	4912	}
3448	4913
3449	4914	/******************************************************************************

		@@ -3451,7 +4916,7 @@ e1000_release_eeprom(struct e1000_hw *hw)
3451	4916	*
3452	4917	* hw - Struct containing variables accessed by shared code
3453	4918	*****************************************************************************/
3454		-int32_t
	4919	+static int32_t
3455	4920	e1000_spi_eeprom_ready(struct e1000_hw *hw)
3456	4921	{
3457	4922	uint16_t retry_count = 0;

		@@ -3472,16 +4937,16 @@ e1000_spi_eeprom_ready(struct e1000_hw *hw)
3472	4937	if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
3473	4938	break;
3474	4939
3475		- udelay(5);
	4940	+ usec_delay(5);
3476	4941	retry_count += 5;
3477	4942
3478	4943	e1000_standby_eeprom(hw);
3479		- } while(retry_count < EEPROM_MAX_RETRY_SPI);
	4944	+ } while (retry_count < EEPROM_MAX_RETRY_SPI);
3480	4945
3481	4946	/* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3482	4947	* only 0-5mSec on 5V devices)
3483	4948	*/
3484		- if(retry_count >= EEPROM_MAX_RETRY_SPI) {
	4949	+ if (retry_count >= EEPROM_MAX_RETRY_SPI) {
3485	4950	DEBUGOUT("SPI EEPROM Status error\n");
3486	4951	return -E1000_ERR_EEPROM;
3487	4952	}

		@@ -3507,24 +4972,46 @@ e1000_read_eeprom(struct e1000_hw *hw,
3507	4972	uint32_t i = 0;
3508	4973
3509	4974	DEBUGFUNC("e1000_read_eeprom");
	4975	+
	4976	+ /* If eeprom is not yet detected, do so now */
	4977	+ if (eeprom->word_size == 0)
	4978	+ e1000_init_eeprom_params(hw);
	4979	+
3510	4980	/* A check for invalid values: offset too large, too many words, and not
3511	4981	* enough words.
3512	4982	*/
3513		- if((offset >= eeprom->word_size) \|\| (words > eeprom->word_size - offset) \|\|
	4983	+ if ((offset >= eeprom->word_size) \|\| (words > eeprom->word_size - offset) \|\|
3514	4984	(words == 0)) {
3515		- DEBUGOUT("\"words\" parameter out of bounds\n");
	4985	+ DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size);
3516	4986	return -E1000_ERR_EEPROM;
3517	4987	}
3518	4988
3519		- /* Prepare the EEPROM for reading */
3520		- if(e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3521		- return -E1000_ERR_EEPROM;
	4989	+ /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
	4990	+ * directly. In this case, we need to acquire the EEPROM so that
	4991	+ * FW or other port software does not interrupt.
	4992	+ */
	4993	+ if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
	4994	+ hw->eeprom.use_eerd == FALSE) {
	4995	+ /* Prepare the EEPROM for bit-bang reading */
	4996	+ if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
	4997	+ return -E1000_ERR_EEPROM;
	4998	+ }
	4999	+
	5000	+ /* Eerd register EEPROM access requires no eeprom aquire/release */
	5001	+ if (eeprom->use_eerd == TRUE)
	5002	+ return e1000_read_eeprom_eerd(hw, offset, words, data);
3522	5003
3523		- if(eeprom->type == e1000_eeprom_spi) {
	5004	+ /* ICH EEPROM access is done via the ICH flash controller */
	5005	+ if (eeprom->type == e1000_eeprom_ich8)
	5006	+ return e1000_read_eeprom_ich8(hw, offset, words, data);
	5007	+
	5008	+ /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
	5009	+ * acquired the EEPROM at this point, so any returns should relase it */
	5010	+ if (eeprom->type == e1000_eeprom_spi) {
3524	5011	uint16_t word_in;
3525	5012	uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
3526	5013
3527		- if(e1000_spi_eeprom_ready(hw)) {
	5014	+ if (e1000_spi_eeprom_ready(hw)) {
3528	5015	e1000_release_eeprom(hw);
3529	5016	return -E1000_ERR_EEPROM;
3530	5017	}

		@@ -3532,7 +5019,7 @@ e1000_read_eeprom(struct e1000_hw *hw,
3532	5019	e1000_standby_eeprom(hw);
3533	5020
3534	5021	/* Some SPI eeproms use the 8th address bit embedded in the opcode */
3535		- if((eeprom->address_bits == 8) && (offset >= 128))
	5022	+ if ((eeprom->address_bits == 8) && (offset >= 128))
3536	5023	read_opcode \|= EEPROM_A8_OPCODE_SPI;
3537	5024
3538	5025	/* Send the READ command (opcode + addr) */

		@@ -3548,7 +5035,7 @@ e1000_read_eeprom(struct e1000_hw *hw,
3548	5035	word_in = e1000_shift_in_ee_bits(hw, 16);
3549	5036	data[i] = (word_in >> 8) \| (word_in << 8);
3550	5037	}
3551		- } else if(eeprom->type == e1000_eeprom_microwire) {
	5038	+ } else if (eeprom->type == e1000_eeprom_microwire) {
3552	5039	for (i = 0; i < words; i++) {
3553	5040	/* Send the READ command (opcode + addr) */
3554	5041	e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,

		@@ -3569,6 +5056,140 @@ e1000_read_eeprom(struct e1000_hw *hw,
3569	5056	return E1000_SUCCESS;
3570	5057	}
3571	5058
	5059	+/******************************************************************************
	5060	+ * Reads a 16 bit word from the EEPROM using the EERD register.
	5061	+ *
	5062	+ * hw - Struct containing variables accessed by shared code
	5063	+ * offset - offset of word in the EEPROM to read
	5064	+ * data - word read from the EEPROM
	5065	+ * words - number of words to read
	5066	+ *****************************************************************************/
	5067	+static int32_t
	5068	+e1000_read_eeprom_eerd(struct e1000_hw *hw,
	5069	+ uint16_t offset,
	5070	+ uint16_t words,
	5071	+ uint16_t *data)
	5072	+{
	5073	+ uint32_t i, eerd = 0;
	5074	+ int32_t error = 0;
	5075	+
	5076	+ for (i = 0; i < words; i++) {
	5077	+ eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
	5078	+ E1000_EEPROM_RW_REG_START;
	5079	+
	5080	+ E1000_WRITE_REG(hw, EERD, eerd);
	5081	+ error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
	5082	+
	5083	+ if (error) {
	5084	+ break;
	5085	+ }
	5086	+ data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
	5087	+
	5088	+ }
	5089	+
	5090	+ return error;
	5091	+}
	5092	+
	5093	+/******************************************************************************
	5094	+ * Writes a 16 bit word from the EEPROM using the EEWR register.
	5095	+ *
	5096	+ * hw - Struct containing variables accessed by shared code
	5097	+ * offset - offset of word in the EEPROM to read
	5098	+ * data - word read from the EEPROM
	5099	+ * words - number of words to read
	5100	+ *****************************************************************************/
	5101	+static int32_t
	5102	+e1000_write_eeprom_eewr(struct e1000_hw *hw,
	5103	+ uint16_t offset,
	5104	+ uint16_t words,
	5105	+ uint16_t *data)
	5106	+{
	5107	+ uint32_t register_value = 0;
	5108	+ uint32_t i = 0;
	5109	+ int32_t error = 0;
	5110	+
	5111	+ if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
	5112	+ return -E1000_ERR_SWFW_SYNC;
	5113	+
	5114	+ for (i = 0; i < words; i++) {
	5115	+ register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) \|
	5116	+ ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) \|
	5117	+ E1000_EEPROM_RW_REG_START;
	5118	+
	5119	+ error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
	5120	+ if (error) {
	5121	+ break;
	5122	+ }
	5123	+
	5124	+ E1000_WRITE_REG(hw, EEWR, register_value);
	5125	+
	5126	+ error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
	5127	+
	5128	+ if (error) {
	5129	+ break;
	5130	+ }
	5131	+ }
	5132	+
	5133	+ e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
	5134	+ return error;
	5135	+}
	5136	+
	5137	+/******************************************************************************
	5138	+ * Polls the status bit (bit 1) of the EERD to determine when the read is done.
	5139	+ *
	5140	+ * hw - Struct containing variables accessed by shared code
	5141	+ *****************************************************************************/
	5142	+static int32_t
	5143	+e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
	5144	+{
	5145	+ uint32_t attempts = 100000;
	5146	+ uint32_t i, reg = 0;
	5147	+ int32_t done = E1000_ERR_EEPROM;
	5148	+
	5149	+ for (i = 0; i < attempts; i++) {
	5150	+ if (eerd == E1000_EEPROM_POLL_READ)
	5151	+ reg = E1000_READ_REG(hw, EERD);
	5152	+ else
	5153	+ reg = E1000_READ_REG(hw, EEWR);
	5154	+
	5155	+ if (reg & E1000_EEPROM_RW_REG_DONE) {
	5156	+ done = E1000_SUCCESS;
	5157	+ break;
	5158	+ }
	5159	+ usec_delay(5);
	5160	+ }
	5161	+
	5162	+ return done;
	5163	+}
	5164	+
	5165	+/***************************************************************************
	5166	+* Description: Determines if the onboard NVM is FLASH or EEPROM.
	5167	+*
	5168	+* hw - Struct containing variables accessed by shared code
	5169	+****************************************************************************/
	5170	+static boolean_t
	5171	+e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
	5172	+{
	5173	+ uint32_t eecd = 0;
	5174	+
	5175	+ DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
	5176	+
	5177	+ if (hw->is_ich == TRUE)
	5178	+ return FALSE;
	5179	+
	5180	+ if (hw->mac_type == e1000_82573) {
	5181	+ eecd = E1000_READ_REG(hw, EECD);
	5182	+
	5183	+ /* Isolate bits 15 & 16 */
	5184	+ eecd = ((eecd >> 15) & 0x03);
	5185	+
	5186	+ /* If both bits are set, device is Flash type */
	5187	+ if (eecd == 0x03) {
	5188	+ return FALSE;
	5189	+ }
	5190	+ }
	5191	+ return TRUE;
	5192	+}
3572	5193
3573	5194	/******************************************************************************
3574	5195	* Verifies that the EEPROM has a valid checksum

		@@ -3587,15 +5208,49 @@ e1000_validate_eeprom_checksum(struct e1000_hw *hw)
3587	5208
3588	5209	DEBUGFUNC("e1000_validate_eeprom_checksum");
3589	5210
3590		- for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
3591		- if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
	5211	+ if ((hw->mac_type == e1000_82573) &&
	5212	+ (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) {
	5213	+ /* Check bit 4 of word 10h. If it is 0, firmware is done updating
	5214	+ * 10h-12h. Checksum may need to be fixed. */
	5215	+ e1000_read_eeprom(hw, 0x10, 1, &eeprom_data);
	5216	+ if ((eeprom_data & 0x10) == 0) {
	5217	+ /* Read 0x23 and check bit 15. This bit is a 1 when the checksum
	5218	+ * has already been fixed. If the checksum is still wrong and this
	5219	+ * bit is a 1, we need to return bad checksum. Otherwise, we need
	5220	+ * to set this bit to a 1 and update the checksum. */
	5221	+ e1000_read_eeprom(hw, 0x23, 1, &eeprom_data);
	5222	+ if ((eeprom_data & 0x8000) == 0) {
	5223	+ eeprom_data \|= 0x8000;
	5224	+ e1000_write_eeprom(hw, 0x23, 1, &eeprom_data);
	5225	+ e1000_update_eeprom_checksum(hw);
	5226	+ }
	5227	+ }
	5228	+ }
	5229	+
	5230	+ if (hw->is_ich == TRUE) {
	5231	+
	5232	+ /* Drivers must allocate the shadow ram structure for the
	5233	+ * EEPROM checksum to be updated. Otherwise, this bit as well
	5234	+ * as the checksum must both be set correctly for this
	5235	+ * validation to pass.
	5236	+ */
	5237	+ e1000_read_eeprom(hw, 0x19, 1, &eeprom_data);
	5238	+ if ((eeprom_data & 0x40) == 0) {
	5239	+ eeprom_data \|= 0x40;
	5240	+ e1000_write_eeprom(hw, 0x19, 1, &eeprom_data);
	5241	+ e1000_update_eeprom_checksum(hw);
	5242	+ }
	5243	+ }
	5244	+
	5245	+ for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
	5246	+ if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3592	5247	DEBUGOUT("EEPROM Read Error\n");
3593	5248	return -E1000_ERR_EEPROM;
3594	5249	}
3595	5250	checksum += eeprom_data;
3596	5251	}
3597	5252
3598		- if(checksum == (uint16_t) EEPROM_SUM)
	5253	+ if (checksum == (uint16_t) EEPROM_SUM)
3599	5254	return E1000_SUCCESS;
3600	5255	else {
3601	5256	DEBUGOUT("EEPROM Checksum Invalid\n");

		@@ -3614,22 +5269,33 @@ e1000_validate_eeprom_checksum(struct e1000_hw *hw)
3614	5269	int32_t
3615	5270	e1000_update_eeprom_checksum(struct e1000_hw *hw)
3616	5271	{
	5272	+ uint32_t ctrl_ext;
3617	5273	uint16_t checksum = 0;
3618	5274	uint16_t i, eeprom_data;
3619	5275
3620	5276	DEBUGFUNC("e1000_update_eeprom_checksum");
3621	5277
3622		- for(i = 0; i < EEPROM_CHECKSUM_REG; i++) {
3623		- if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
	5278	+ for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
	5279	+ if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3624	5280	DEBUGOUT("EEPROM Read Error\n");
3625	5281	return -E1000_ERR_EEPROM;
3626	5282	}
3627	5283	checksum += eeprom_data;
3628	5284	}
3629	5285	checksum = (uint16_t) EEPROM_SUM - checksum;
3630		- if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
	5286	+ if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
3631	5287	DEBUGOUT("EEPROM Write Error\n");
3632	5288	return -E1000_ERR_EEPROM;
	5289	+ } else if (hw->eeprom.type == e1000_eeprom_flash) {
	5290	+ e1000_commit_shadow_ram(hw);
	5291	+ } else if (hw->eeprom.type == e1000_eeprom_ich8) {
	5292	+ e1000_commit_shadow_ram(hw);
	5293	+ /* Reload the EEPROM, or else modifications will not appear
	5294	+ * until after next adapter reset. */
	5295	+ ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
	5296	+ ctrl_ext \|= E1000_CTRL_EXT_EE_RST;
	5297	+ E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
	5298	+ msec_delay(10);
3633	5299	}
3634	5300	return E1000_SUCCESS;
3635	5301	}

		@@ -3656,20 +5322,31 @@ e1000_write_eeprom(struct e1000_hw *hw,
3656	5322
3657	5323	DEBUGFUNC("e1000_write_eeprom");
3658	5324
	5325	+ /* If eeprom is not yet detected, do so now */
	5326	+ if (eeprom->word_size == 0)
	5327	+ e1000_init_eeprom_params(hw);
	5328	+
3659	5329	/* A check for invalid values: offset too large, too many words, and not
3660	5330	* enough words.
3661	5331	*/
3662		- if((offset >= eeprom->word_size) \|\| (words > eeprom->word_size - offset) \|\|
	5332	+ if ((offset >= eeprom->word_size) \|\| (words > eeprom->word_size - offset) \|\|
3663	5333	(words == 0)) {
3664	5334	DEBUGOUT("\"words\" parameter out of bounds\n");
3665	5335	return -E1000_ERR_EEPROM;
3666	5336	}
3667	5337
	5338	+ /* 82573 writes only through eewr */
	5339	+ if (eeprom->use_eewr == TRUE)
	5340	+ return e1000_write_eeprom_eewr(hw, offset, words, data);
	5341	+
	5342	+ if (eeprom->type == e1000_eeprom_ich8)
	5343	+ return e1000_write_eeprom_ich8(hw, offset, words, data);
	5344	+
3668	5345	/* Prepare the EEPROM for writing */
3669	5346	if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3670	5347	return -E1000_ERR_EEPROM;
3671	5348
3672		- if(eeprom->type == e1000_eeprom_microwire) {
	5349	+ if (eeprom->type == e1000_eeprom_microwire) {
3673	5350	status = e1000_write_eeprom_microwire(hw, offset, words, data);
3674	5351	} else {
3675	5352	status = e1000_write_eeprom_spi(hw, offset, words, data);

		@@ -3691,7 +5368,7 @@ e1000_write_eeprom(struct e1000_hw *hw,
3691	5368	* data - pointer to array of 8 bit words to be written to the EEPROM
3692	5369	*
3693	5370	*****************************************************************************/
3694		-int32_t
	5371	+static int32_t
3695	5372	e1000_write_eeprom_spi(struct e1000_hw *hw,
3696	5373	uint16_t offset,
3697	5374	uint16_t words,

		@@ -3705,7 +5382,7 @@ e1000_write_eeprom_spi(struct e1000_hw *hw,
3705	5382	while (widx < words) {
3706	5383	uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
3707	5384
3708		- if(e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
	5385	+ if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
3709	5386
3710	5387	e1000_standby_eeprom(hw);
3711	5388

		@@ -3716,7 +5393,7 @@ e1000_write_eeprom_spi(struct e1000_hw *hw,
3716	5393	e1000_standby_eeprom(hw);
3717	5394
3718	5395	/* Some SPI eeproms use the 8th address bit embedded in the opcode */
3719		- if((eeprom->address_bits == 8) && (offset >= 128))
	5396	+ if ((eeprom->address_bits == 8) && (offset >= 128))
3720	5397	write_opcode \|= EEPROM_A8_OPCODE_SPI;
3721	5398
3722	5399	/* Send the Write command (8-bit opcode + addr) */

		@@ -3738,7 +5415,7 @@ e1000_write_eeprom_spi(struct e1000_hw *hw,
3738	5415	* operation, while the smaller eeproms are capable of an 8-byte
3739	5416	* PAGE WRITE operation. Break the inner loop to pass new address
3740	5417	*/
3741		- if((((offset + widx)*2) % eeprom->page_size) == 0) {
	5418	+ if ((((offset + widx)*2) % eeprom->page_size) == 0) {
3742	5419	e1000_standby_eeprom(hw);
3743	5420	break;
3744	5421	}

		@@ -3757,7 +5434,7 @@ e1000_write_eeprom_spi(struct e1000_hw *hw,
3757	5434	* data - pointer to array of 16 bit words to be written to the EEPROM
3758	5435	*
3759	5436	*****************************************************************************/
3760		-int32_t
	5437	+static int32_t
3761	5438	e1000_write_eeprom_microwire(struct e1000_hw *hw,
3762	5439	uint16_t offset,
3763	5440	uint16_t words,

		@@ -3804,12 +5481,12 @@ e1000_write_eeprom_microwire(struct e1000_hw *hw,
3804	5481	* signal that the command has been completed by raising the DO signal.
3805	5482	* If DO does not go high in 10 milliseconds, then error out.
3806	5483	*/
3807		- for(i = 0; i < 200; i++) {
	5484	+ for (i = 0; i < 200; i++) {
3808	5485	eecd = E1000_READ_REG(hw, EECD);
3809		- if(eecd & E1000_EECD_DO) break;
3810		- udelay(50);
	5486	+ if (eecd & E1000_EECD_DO) break;
	5487	+ usec_delay(50);
3811	5488	}
3812		- if(i == 200) {
	5489	+ if (i == 200) {
3813	5490	DEBUGOUT("EEPROM Write did not complete\n");
3814	5491	return -E1000_ERR_EEPROM;
3815	5492	}

		@@ -3835,37 +5512,171 @@ e1000_write_eeprom_microwire(struct e1000_hw *hw,
3835	5512	}
3836	5513
3837	5514	/******************************************************************************
3838		- * Reads the adapter's part number from the EEPROM
	5515	+ * Flushes the cached eeprom to NVM. This is done by saving the modified values
	5516	+ * in the eeprom cache and the non modified values in the currently active bank
	5517	+ * to the new bank.
3839	5518	*
3840	5519	* hw - Struct containing variables accessed by shared code
3841		- * part_num - Adapter's part number
	5520	+ * offset - offset of word in the EEPROM to read
	5521	+ * data - word read from the EEPROM
	5522	+ * words - number of words to read
3842	5523	*****************************************************************************/
3843		-int32_t
3844		-e1000_read_part_num(struct e1000_hw *hw,
3845		- uint32_t *part_num)
	5524	+static int32_t
	5525	+e1000_commit_shadow_ram(struct e1000_hw *hw)
3846	5526	{
3847		- uint16_t offset = EEPROM_PBA_BYTE_1;
3848		- uint16_t eeprom_data;
	5527	+ uint32_t attempts = 100000;
	5528	+ uint32_t eecd = 0;
	5529	+ uint32_t flop = 0;
	5530	+ uint32_t i = 0;
	5531	+ int32_t error = E1000_SUCCESS;
	5532	+ uint32_t old_bank_offset = 0;
	5533	+ uint32_t new_bank_offset = 0;
	5534	+ uint8_t low_byte = 0;
	5535	+ uint8_t high_byte = 0;
	5536	+ boolean_t sector_write_failed = FALSE;
	5537	+
	5538	+ if (hw->mac_type == e1000_82573) {
	5539	+ /* The flop register will be used to determine if flash type is STM */
	5540	+ flop = E1000_READ_REG(hw, FLOP);
	5541	+ for (i=0; i < attempts; i++) {
	5542	+ eecd = E1000_READ_REG(hw, EECD);
	5543	+ if ((eecd & E1000_EECD_FLUPD) == 0) {
	5544	+ break;
	5545	+ }
	5546	+ usec_delay(5);
	5547	+ }
3849	5548
3850		- DEBUGFUNC("e1000_read_part_num");
	5549	+ if (i == attempts) {
	5550	+ return -E1000_ERR_EEPROM;
	5551	+ }
3851	5552
3852		- /* Get word 0 from EEPROM */
3853		- if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
3854		- DEBUGOUT("EEPROM Read Error\n");
3855		- return -E1000_ERR_EEPROM;
	5553	+ /* If STM opcode located in bits 15:8 of flop, reset firmware */
	5554	+ if ((flop & 0xFF00) == E1000_STM_OPCODE) {
	5555	+ E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET);
	5556	+ }
	5557	+
	5558	+ /* Perform the flash update */
	5559	+ E1000_WRITE_REG(hw, EECD, eecd \| E1000_EECD_FLUPD);
	5560	+
	5561	+ for (i=0; i < attempts; i++) {
	5562	+ eecd = E1000_READ_REG(hw, EECD);
	5563	+ if ((eecd & E1000_EECD_FLUPD) == 0) {
	5564	+ break;
	5565	+ }
	5566	+ usec_delay(5);
	5567	+ }
	5568	+
	5569	+ if (i == attempts) {
	5570	+ return -E1000_ERR_EEPROM;
	5571	+ }
3856	5572	}
3857		- /* Save word 0 in upper half of part_num */
3858		- *part_num = (uint32_t) (eeprom_data << 16);
3859	5573
3860		- /* Get word 1 from EEPROM */
3861		- if(e1000_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) {
3862		- DEBUGOUT("EEPROM Read Error\n");
3863		- return -E1000_ERR_EEPROM;
	5574	+ if ((hw->is_ich == TRUE) && hw->eeprom_shadow_ram != NULL) {
	5575	+ /* We're writing to the opposite bank so if we're on bank 1,
	5576	+ * write to bank 0 etc. We also need to erase the segment that
	5577	+ * is going to be written */
	5578	+ if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) {
	5579	+ new_bank_offset = hw->flash_bank_size * 2;
	5580	+ old_bank_offset = 0;
	5581	+ e1000_erase_ich8_4k_segment(hw, 1);
	5582	+ } else {
	5583	+ old_bank_offset = hw->flash_bank_size * 2;
	5584	+ new_bank_offset = 0;
	5585	+ e1000_erase_ich8_4k_segment(hw, 0);
	5586	+ }
	5587	+
	5588	+ sector_write_failed = FALSE;
	5589	+ /* Loop for every byte in the shadow RAM,
	5590	+ * which is in units of words. */
	5591	+ for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
	5592	+ /* Determine whether to write the value stored
	5593	+ * in the other NVM bank or a modified value stored
	5594	+ * in the shadow RAM */
	5595	+ if (hw->eeprom_shadow_ram[i].modified == TRUE) {
	5596	+ low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word;
	5597	+ usec_delay(100);
	5598	+ error = e1000_verify_write_ich8_byte(hw,
	5599	+ (i << 1) + new_bank_offset, low_byte);
	5600	+
	5601	+ if (error != E1000_SUCCESS)
	5602	+ sector_write_failed = TRUE;
	5603	+ else {
	5604	+ high_byte =
	5605	+ (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
	5606	+ usec_delay(100);
	5607	+ }
	5608	+ } else {
	5609	+ e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
	5610	+ &low_byte);
	5611	+ usec_delay(100);
	5612	+ error = e1000_verify_write_ich8_byte(hw,
	5613	+ (i << 1) + new_bank_offset, low_byte);
	5614	+
	5615	+ if (error != E1000_SUCCESS)
	5616	+ sector_write_failed = TRUE;
	5617	+ else {
	5618	+ e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
	5619	+ &high_byte);
	5620	+ usec_delay(100);
	5621	+ }
	5622	+ }
	5623	+
	5624	+ /* If the write of the low byte was successful, go ahread and
	5625	+ * write the high byte while checking to make sure that if it
	5626	+ * is the signature byte, then it is handled properly */
	5627	+ if (sector_write_failed == FALSE) {
	5628	+ /* If the word is 0x13, then make sure the signature bits
	5629	+ * (15:14) are 11b until the commit has completed.
	5630	+ * This will allow us to write 10b which indicates the
	5631	+ * signature is valid. We want to do this after the write
	5632	+ * has completed so that we don't mark the segment valid
	5633	+ * while the write is still in progress */
	5634	+ if (i == E1000_ICH_NVM_SIG_WORD)
	5635	+ high_byte = E1000_ICH_NVM_SIG_MASK \| high_byte;
	5636	+
	5637	+ error = e1000_verify_write_ich8_byte(hw,
	5638	+ (i << 1) + new_bank_offset + 1, high_byte);
	5639	+ if (error != E1000_SUCCESS)
	5640	+ sector_write_failed = TRUE;
	5641	+
	5642	+ } else {
	5643	+ /* If the write failed then break from the loop and
	5644	+ * return an error */
	5645	+ break;
	5646	+ }
	5647	+ }
	5648	+
	5649	+ /* Don't bother writing the segment valid bits if sector
	5650	+ * programming failed. */
	5651	+ if (sector_write_failed == FALSE) {
	5652	+ /* Finally validate the new segment by setting bit 15:14
	5653	+ * to 10b in word 0x13 , this can be done without an
	5654	+ * erase as well since these bits are 11 to start with
	5655	+ * and we need to change bit 14 to 0b */
	5656	+ e1000_read_ich8_byte(hw,
	5657	+ E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
	5658	+ &high_byte);
	5659	+ high_byte &= 0xBF;
	5660	+ error = e1000_verify_write_ich8_byte(hw,
	5661	+ E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte);
	5662	+ /* And invalidate the previously valid segment by setting
	5663	+ * its signature word (0x13) high_byte to 0b. This can be
	5664	+ * done without an erase because flash erase sets all bits
	5665	+ * to 1's. We can write 1's to 0's without an erase */
	5666	+ if (error == E1000_SUCCESS) {
	5667	+ error = e1000_verify_write_ich8_byte(hw,
	5668	+ E1000_ICH_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0);
	5669	+ }
	5670	+
	5671	+ /* Clear the now not used entry in the cache */
	5672	+ for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
	5673	+ hw->eeprom_shadow_ram[i].modified = FALSE;
	5674	+ hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
	5675	+ }
	5676	+ }
3864	5677	}
3865		- /* Save word 1 in lower half of part_num */
3866		- *part_num \|= eeprom_data;
3867	5678
3868		- return E1000_SUCCESS;
	5679	+ return error;
3869	5680	}
3870	5681
3871	5682	/******************************************************************************

		@@ -3882,20 +5693,29 @@ e1000_read_mac_addr(struct e1000_hw * hw)
3882	5693
3883	5694	DEBUGFUNC("e1000_read_mac_addr");
3884	5695
3885		- for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
	5696	+ for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
3886	5697	offset = i >> 1;
3887		- if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
	5698	+ if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
3888	5699	DEBUGOUT("EEPROM Read Error\n");
3889	5700	return -E1000_ERR_EEPROM;
3890	5701	}
3891	5702	hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
3892	5703	hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
3893	5704	}
3894		- if(((hw->mac_type == e1000_82546) \|\| (hw->mac_type == e1000_82546_rev_3)) &&
3895		- (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1))
	5705	+
	5706	+ switch (hw->mac_type) {
	5707	+ default:
	5708	+ break;
	5709	+ case e1000_82546:
	5710	+ case e1000_82546_rev_3:
	5711	+ case e1000_82571:
	5712	+ case e1000_80003es2lan:
	5713	+ if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
3896	5714	hw->perm_mac_addr[5] ^= 0x01;
	5715	+ break;
	5716	+ }
3897	5717
3898		- for(i = 0; i < NODE_ADDRESS_SIZE; i++)
	5718	+ for (i = 0; i < NODE_ADDRESS_SIZE; i++)
3899	5719	hw->mac_addr[i] = hw->perm_mac_addr[i];
3900	5720	return E1000_SUCCESS;
3901	5721	}

		@@ -3909,10 +5729,11 @@ e1000_read_mac_addr(struct e1000_hw * hw)
3909	5729	* of the receive addresss registers. Clears the multicast table. Assumes
3910	5730	* the receiver is in reset when the routine is called.
3911	5731	*****************************************************************************/
3912		-void
	5732	+static void
3913	5733	e1000_init_rx_addrs(struct e1000_hw *hw)
3914	5734	{
3915	5735	uint32_t i;
	5736	+ uint32_t rar_num;
3916	5737
3917	5738	DEBUGFUNC("e1000_init_rx_addrs");
3918	5739

		@@ -3921,86 +5742,24 @@ e1000_init_rx_addrs(struct e1000_hw *hw)
3921	5742
3922	5743	e1000_rar_set(hw, hw->mac_addr, 0);
3923	5744
3924		- /* Zero out the other 15 receive addresses. */
3925		- DEBUGOUT("Clearing RAR[1-15]\n");
3926		- for(i = 1; i < E1000_RAR_ENTRIES; i++) {
3927		- E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
3928		- E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
3929		- }
3930		-}
3931		-
3932		-/******************************************************************************
3933		- * Updates the MAC's list of multicast addresses.
3934		- *
3935		- * hw - Struct containing variables accessed by shared code
3936		- * mc_addr_list - the list of new multicast addresses
3937		- * mc_addr_count - number of addresses
3938		- * pad - number of bytes between addresses in the list
3939		- * rar_used_count - offset where to start adding mc addresses into the RAR's
3940		- *
3941		- * The given list replaces any existing list. Clears the last 15 receive
3942		- * address registers and the multicast table. Uses receive address registers
3943		- * for the first 15 multicast addresses, and hashes the rest into the
3944		- * multicast table.
3945		- *****************************************************************************/
3946		-void
3947		-e1000_mc_addr_list_update(struct e1000_hw *hw,
3948		- uint8_t *mc_addr_list,
3949		- uint32_t mc_addr_count,
3950		- uint32_t pad,
3951		- uint32_t rar_used_count)
3952		-{
3953		- uint32_t hash_value;
3954		- uint32_t i;
3955		-
3956		- DEBUGFUNC("e1000_mc_addr_list_update");
	5745	+ rar_num = E1000_RAR_ENTRIES;
3957	5746
3958		- /* Set the new number of MC addresses that we are being requested to use. */
3959		- hw->num_mc_addrs = mc_addr_count;
	5747	+ /* Reserve a spot for the Locally Administered Address to work around
	5748	+ * an 82571 issue in which a reset on one port will reload the MAC on
	5749	+ * the other port. */
	5750	+ if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
	5751	+ rar_num -= 1;
	5752	+ if (hw->mac_type == e1000_ich8lan)
	5753	+ rar_num = E1000_RAR_ENTRIES_ICH8LAN;
3960	5754
3961		- /* Clear RAR[1-15] */
3962		- DEBUGOUT(" Clearing RAR[1-15]\n");
3963		- for(i = rar_used_count; i < E1000_RAR_ENTRIES; i++) {
	5755	+ /* Zero out the other 15 receive addresses. */
	5756	+ DEBUGOUT("Clearing RAR[1-15]\n");
	5757	+ for (i = 1; i < rar_num; i++) {
3964	5758	E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
	5759	+ E1000_WRITE_FLUSH(hw);
3965	5760	E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
	5761	+ E1000_WRITE_FLUSH(hw);
3966	5762	}
3967		-
3968		- /* Clear the MTA */
3969		- DEBUGOUT(" Clearing MTA\n");
3970		- for(i = 0; i < E1000_NUM_MTA_REGISTERS; i++) {
3971		- E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
3972		- }
3973		-
3974		- /* Add the new addresses */
3975		- for(i = 0; i < mc_addr_count; i++) {
3976		- DEBUGOUT(" Adding the multicast addresses:\n");
3977		- DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
3978		- mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
3979		- mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1],
3980		- mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2],
3981		- mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3],
3982		- mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4],
3983		- mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]);
3984		-
3985		- hash_value = e1000_hash_mc_addr(hw,
3986		- mc_addr_list +
3987		- (i * (ETH_LENGTH_OF_ADDRESS + pad)));
3988		-
3989		- DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
3990		-
3991		- /* Place this multicast address in the RAR if there is room, *
3992		- * else put it in the MTA
3993		- */
3994		- if(rar_used_count < E1000_RAR_ENTRIES) {
3995		- e1000_rar_set(hw,
3996		- mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)),
3997		- rar_used_count);
3998		- rar_used_count++;
3999		- } else {
4000		- e1000_mta_set(hw, hash_value);
4001		- }
4002		- }
4003		- DEBUGOUT("MC Update Complete\n");
4004	5763	}
4005	5764
4006	5765	/******************************************************************************

		@@ -4024,24 +5783,47 @@ e1000_hash_mc_addr(struct e1000_hw *hw,
4024	5783	* LSB MSB
4025	5784	*/
4026	5785	case 0:
4027		- /* [47:36] i.e. 0x563 for above example address */
4028		- hash_value = ((mc_addr[4] >> 4) \| (((uint16_t) mc_addr[5]) << 4));
	5786	+ if (hw->is_ich == TRUE) {
	5787	+ /* [47:38] i.e. 0x158 for above example address */
	5788	+ hash_value = ((mc_addr[4] >> 6) \| (((uint16_t) mc_addr[5]) << 2));
	5789	+ } else {
	5790	+ /* [47:36] i.e. 0x563 for above example address */
	5791	+ hash_value = ((mc_addr[4] >> 4) \| (((uint16_t) mc_addr[5]) << 4));
	5792	+ }
4029	5793	break;
4030	5794	case 1:
4031		- /* [46:35] i.e. 0xAC6 for above example address */
4032		- hash_value = ((mc_addr[4] >> 3) \| (((uint16_t) mc_addr[5]) << 5));
	5795	+ if (hw->is_ich == TRUE) {
	5796	+ /* [46:37] i.e. 0x2B1 for above example address */
	5797	+ hash_value = ((mc_addr[4] >> 5) \| (((uint16_t) mc_addr[5]) << 3));
	5798	+ } else {
	5799	+ /* [46:35] i.e. 0xAC6 for above example address */
	5800	+ hash_value = ((mc_addr[4] >> 3) \| (((uint16_t) mc_addr[5]) << 5));
	5801	+ }
4033	5802	break;
4034	5803	case 2:
4035		- /* [45:34] i.e. 0x5D8 for above example address */
4036		- hash_value = ((mc_addr[4] >> 2) \| (((uint16_t) mc_addr[5]) << 6));
	5804	+ if (hw->is_ich == TRUE) {
	5805	+ /[45:36] i.e. 0x163 for above example address /
	5806	+ hash_value = ((mc_addr[4] >> 4) \| (((uint16_t) mc_addr[5]) << 4));
	5807	+ } else {
	5808	+ /* [45:34] i.e. 0x5D8 for above example address */
	5809	+ hash_value = ((mc_addr[4] >> 2) \| (((uint16_t) mc_addr[5]) << 6));
	5810	+ }
4037	5811	break;
4038	5812	case 3:
4039		- /* [43:32] i.e. 0x634 for above example address */
4040		- hash_value = ((mc_addr[4]) \| (((uint16_t) mc_addr[5]) << 8));
	5813	+ if (hw->is_ich == TRUE) {
	5814	+ /* [43:34] i.e. 0x18D for above example address */
	5815	+ hash_value = ((mc_addr[4] >> 2) \| (((uint16_t) mc_addr[5]) << 6));
	5816	+ } else {
	5817	+ /* [43:32] i.e. 0x634 for above example address */
	5818	+ hash_value = ((mc_addr[4]) \| (((uint16_t) mc_addr[5]) << 8));
	5819	+ }
4041	5820	break;
4042	5821	}
4043	5822
4044	5823	hash_value &= 0xFFF;
	5824	+ if (hw->is_ich == TRUE)
	5825	+ hash_value &= 0x3FF;
	5826	+
4045	5827	return hash_value;
4046	5828	}
4047	5829

		@@ -4068,6 +5850,9 @@ e1000_mta_set(struct e1000_hw *hw,
4068	5850	* register are determined by the lower 5 bits of the value.
4069	5851	*/
4070	5852	hash_reg = (hash_value >> 5) & 0x7F;
	5853	+ if (hw->is_ich == TRUE)
	5854	+ hash_reg &= 0x1F;
	5855	+
4071	5856	hash_bit = hash_value & 0x1F;
4072	5857
4073	5858	mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);

		@@ -4078,12 +5863,15 @@ e1000_mta_set(struct e1000_hw *hw,
4078	5863	* in the MTA, save off the previous entry before writing and
4079	5864	* restore the old value after writing.
4080	5865	*/
4081		- if((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
	5866	+ if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
4082	5867	temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
4083	5868	E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
	5869	+ E1000_WRITE_FLUSH(hw);
4084	5870	E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
	5871	+ E1000_WRITE_FLUSH(hw);
4085	5872	} else {
4086	5873	E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
	5874	+ E1000_WRITE_FLUSH(hw);
4087	5875	}
4088	5876	}
4089	5877

		@@ -4107,11 +5895,42 @@ e1000_rar_set(struct e1000_hw *hw,
4107	5895	rar_low = ((uint32_t) addr[0] \|
4108	5896	((uint32_t) addr[1] << 8) \|
4109	5897	((uint32_t) addr[2] << 16) \| ((uint32_t) addr[3] << 24));
	5898	+ rar_high = ((uint32_t) addr[4] \| ((uint32_t) addr[5] << 8));
4110	5899
4111		- rar_high = ((uint32_t) addr[4] \| ((uint32_t) addr[5] << 8) \| E1000_RAH_AV);
	5900	+ /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
	5901	+ * unit hang.
	5902	+ *
	5903	+ * Description:
	5904	+ * If there are any Rx frames queued up or otherwise present in the HW
	5905	+ * before RSS is enabled, and then we enable RSS, the HW Rx unit will
	5906	+ * hang. To work around this issue, we have to disable receives and
	5907	+ * flush out all Rx frames before we enable RSS. To do so, we modify we
	5908	+ * redirect all Rx traffic to manageability and then reset the HW.
	5909	+ * This flushes away Rx frames, and (since the redirections to
	5910	+ * manageability persists across resets) keeps new ones from coming in
	5911	+ * while we work. Then, we clear the Address Valid AV bit for all MAC
	5912	+ * addresses and undo the re-direction to manageability.
	5913	+ * Now, frames are coming in again, but the MAC won't accept them, so
	5914	+ * far so good. We now proceed to initialize RSS (if necessary) and
	5915	+ * configure the Rx unit. Last, we re-enable the AV bits and continue
	5916	+ * on our merry way.
	5917	+ */
	5918	+ switch (hw->mac_type) {
	5919	+ case e1000_82571:
	5920	+ case e1000_82572:
	5921	+ case e1000_80003es2lan:
	5922	+ if (hw->leave_av_bit_off == TRUE)
	5923	+ break;
	5924	+ default:
	5925	+ /* Indicate to hardware the Address is Valid. */
	5926	+ rar_high \|= E1000_RAH_AV;
	5927	+ break;
	5928	+ }
4112	5929
4113	5930	E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
	5931	+ E1000_WRITE_FLUSH(hw);
4114	5932	E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
	5933	+ E1000_WRITE_FLUSH(hw);
4115	5934	}
4116	5935
4117	5936	/******************************************************************************

		@@ -4128,12 +5947,18 @@ e1000_write_vfta(struct e1000_hw *hw,
4128	5947	{
4129	5948	uint32_t temp;
4130	5949
4131		- if((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
	5950	+ if (hw->is_ich == TRUE)
	5951	+ return;
	5952	+
	5953	+ if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
4132	5954	temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
4133	5955	E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
	5956	+ E1000_WRITE_FLUSH(hw);
4134	5957	E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
	5958	+ E1000_WRITE_FLUSH(hw);
4135	5959	} else {
4136	5960	E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
	5961	+ E1000_WRITE_FLUSH(hw);
4137	5962	}
4138	5963	}
4139	5964

		@@ -4142,13 +5967,38 @@ e1000_write_vfta(struct e1000_hw *hw,
4142	5967	*
4143	5968	* hw - Struct containing variables accessed by shared code
4144	5969	*****************************************************************************/
4145		-void
	5970	+static void
4146	5971	e1000_clear_vfta(struct e1000_hw *hw)
4147	5972	{
4148	5973	uint32_t offset;
4149		-
4150		- for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
4151		- E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
	5974	+ uint32_t vfta_value = 0;
	5975	+ uint32_t vfta_offset = 0;
	5976	+ uint32_t vfta_bit_in_reg = 0;
	5977	+
	5978	+ if (hw->is_ich == TRUE)
	5979	+ return;
	5980	+
	5981	+ if (hw->mac_type == e1000_82573) {
	5982	+ if (hw->mng_cookie.vlan_id != 0) {
	5983	+ /* The VFTA is a 4096b bit-field, each identifying a single VLAN