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linux-2.4.36: Commit

2.4.36-stable kernel tree


Commit MetaInfo

Revisionf9a33c5a01c8df82fd33830dfd4cd817012cf063 (tree)
Zeit2007-02-06 09:56:43
AutorJesse Brandeburg <jesse.brandeburg@inte...>
CommiterAuke Kok

Log Message

e1000: integrate latest 2.4 linux driver

This updates the e1000 driver to our out-of-tree equivalent of 7.3.20.
This adds support for several new pieces of e100 hardware, including
quad-port 82571's (copper only), integrated nics of ICH8. The patch
includes dynamic interrupt support, many rewrites of subcomponents such
as wol enabling, manageability handling, shutdown/reset race fixes,

To keep the difference with the 2.6-version of this driver minimal
(which will facilitate future updates) we include a small compatibility
layer exclusively for e1000.

Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com>

Ändern Zusammenfassung

Diff

--- a/drivers/net/e1000/Makefile
+++ b/drivers/net/e1000/Makefile
@@ -32,7 +32,7 @@
3232
3333 O_TARGET := e1000.o
3434
35-obj-y := e1000_main.o e1000_hw.o e1000_ethtool.o e1000_param.o
35+obj-y := e1000_main.o e1000_hw.o e1000_ethtool.o e1000_param.o kcompat.o
3636 obj-m := $(O_TARGET)
3737
3838 include $(TOPDIR)/Rules.make
--- a/drivers/net/e1000/e1000.h
+++ b/drivers/net/e1000/e1000.h
@@ -1,27 +1,27 @@
11 /*******************************************************************************
22
3-
4- Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
5-
6- This program is free software; you can redistribute it and/or modify it
7- under the terms of the GNU General Public License as published by the Free
8- Software Foundation; either version 2 of the License, or (at your option)
9- any later version.
10-
11- This program is distributed in the hope that it will be useful, but WITHOUT
12- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
3+ Intel PRO/1000 Linux driver
4+ Copyright(c) 1999 - 2006 Intel Corporation.
5+
6+ This program is free software; you can redistribute it and/or modify it
7+ under the terms and conditions of the GNU General Public License,
8+ version 2, as published by the Free Software Foundation.
9+
10+ This program is distributed in the hope it will be useful, but WITHOUT
11+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1413 more details.
15-
14+
1615 You should have received a copy of the GNU General Public License along with
17- this program; if not, write to the Free Software Foundation, Inc., 59
18- Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19-
20- The full GNU General Public License is included in this distribution in the
21- file called LICENSE.
22-
16+ this program; if not, write to the Free Software Foundation, Inc.,
17+ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18+
19+ The full GNU General Public License is included in this distribution in
20+ the file called "COPYING".
21+
2322 Contact Information:
2423 Linux NICS <linux.nics@intel.com>
24+ e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
2525 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
2626
2727 *******************************************************************************/
@@ -33,7 +33,6 @@
3333 #define _E1000_H_
3434
3535 #include <linux/stddef.h>
36-#include <linux/config.h>
3736 #include <linux/module.h>
3837 #include <linux/types.h>
3938 #include <asm/byteorder.h>
@@ -53,7 +52,7 @@
5352 #include <linux/interrupt.h>
5453 #include <linux/string.h>
5554 #include <linux/pagemap.h>
56-#include <asm/bitops.h>
55+#include <linux/bitops.h>
5756 #include <asm/io.h>
5857 #include <asm/irq.h>
5958 #include <linux/capability.h>
@@ -64,21 +63,21 @@
6463 #include <net/pkt_sched.h>
6564 #include <linux/list.h>
6665 #include <linux/reboot.h>
67-#ifdef NETIF_F_TSO
68-#include <net/checksum.h>
69-#endif
70-#include <linux/tqueue.h>
66+#ifdef SIOCGMIIPHY
7167 #include <linux/mii.h>
68+#endif
69+#ifdef SIOCETHTOOL
7270 #include <linux/ethtool.h>
71+#endif
72+#ifdef NETIF_F_HW_VLAN_TX
7373 #include <linux/if_vlan.h>
74-#include <linux/moduleparam.h>
74+#endif
7575
7676 #define BAR_0 0
7777 #define BAR_1 1
7878 #define BAR_5 5
79-#define PCI_DMA_64BIT 0xffffffffffffffffULL
80-#define PCI_DMA_32BIT 0x00000000ffffffffULL
8179
80+#include "kcompat.h"
8281 #define INTEL_E1000_ETHERNET_DEVICE(device_id) {\
8382 PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)}
8483
@@ -86,11 +85,7 @@ struct e1000_adapter;
8685
8786 #include "e1000_hw.h"
8887
89-#ifdef DBG
90-#define E1000_DBG(args...) printk(KERN_DEBUG "e1000: " args)
91-#else
9288 #define E1000_DBG(args...)
93-#endif
9489
9590 #define E1000_ERR(args...) printk(KERN_ERR "e1000: " args)
9691
@@ -113,7 +108,14 @@ struct e1000_adapter;
113108 #define E1000_MIN_RXD 80
114109 #define E1000_MAX_82544_RXD 4096
115110
111+/* this is the size past which hardware will drop packets when setting LPE=0 */
112+#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
113+
116114 /* Supported Rx Buffer Sizes */
115+#define E1000_RXBUFFER_128 128 /* Used for packet split */
116+#define E1000_RXBUFFER_256 256 /* Used for packet split */
117+#define E1000_RXBUFFER_512 512
118+#define E1000_RXBUFFER_1024 1024
117119 #define E1000_RXBUFFER_2048 2048
118120 #define E1000_RXBUFFER_4096 4096
119121 #define E1000_RXBUFFER_8192 8192
@@ -139,15 +141,22 @@ struct e1000_adapter;
139141 /* How many Rx Buffers do we bundle into one write to the hardware ? */
140142 #define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
141143
142-#define AUTO_ALL_MODES 0
143-#define E1000_EEPROM_82544_APM 0x0004
144-#define E1000_EEPROM_APME 0x0400
144+#define AUTO_ALL_MODES 0
145+#define E1000_EEPROM_82544_APM 0x0004
146+#define E1000_EEPROM_ICH8_APME 0x0004
147+#define E1000_EEPROM_APME 0x0400
145148
146149 #ifndef E1000_MASTER_SLAVE
147150 /* Switch to override PHY master/slave setting */
148151 #define E1000_MASTER_SLAVE e1000_ms_hw_default
149152 #endif
150153
154+#ifdef NETIF_F_HW_VLAN_TX
155+#define E1000_MNG_VLAN_NONE -1
156+#endif
157+/* Number of packet split data buffers (not including the header buffer) */
158+#define PS_PAGE_BUFFERS MAX_PS_BUFFERS-1
159+
151160 /* only works for sizes that are powers of 2 */
152161 #define E1000_ROUNDUP(i, size) ((i) = (((i) + (size) - 1) & ~((size) - 1)))
153162
@@ -155,13 +164,39 @@ struct e1000_adapter;
155164 * so a DMA handle can be stored along with the buffer */
156165 struct e1000_buffer {
157166 struct sk_buff *skb;
158- uint64_t dma;
167+ dma_addr_t dma;
159168 unsigned long time_stamp;
160169 uint16_t length;
161170 uint16_t next_to_watch;
162171 };
163172
164-struct e1000_desc_ring {
173+
174+struct e1000_ps_page { struct page *ps_page[PS_PAGE_BUFFERS]; };
175+struct e1000_ps_page_dma { uint64_t ps_page_dma[PS_PAGE_BUFFERS]; };
176+
177+struct e1000_tx_ring {
178+ /* pointer to the descriptor ring memory */
179+ void *desc;
180+ /* physical address of the descriptor ring */
181+ dma_addr_t dma;
182+ /* length of descriptor ring in bytes */
183+ unsigned int size;
184+ /* number of descriptors in the ring */
185+ unsigned int count;
186+ /* next descriptor to associate a buffer with */
187+ unsigned int next_to_use;
188+ /* next descriptor to check for DD status bit */
189+ unsigned int next_to_clean;
190+ /* array of buffer information structs */
191+ struct e1000_buffer *buffer_info;
192+
193+ spinlock_t tx_lock;
194+ uint16_t tdh;
195+ uint16_t tdt;
196+ boolean_t last_tx_tso;
197+};
198+
199+struct e1000_rx_ring {
165200 /* pointer to the descriptor ring memory */
166201 void *desc;
167202 /* physical address of the descriptor ring */
@@ -176,12 +211,25 @@ struct e1000_desc_ring {
176211 unsigned int next_to_clean;
177212 /* array of buffer information structs */
178213 struct e1000_buffer *buffer_info;
214+ /* arrays of page information for packet split */
215+ struct e1000_ps_page *ps_page;
216+ struct e1000_ps_page_dma *ps_page_dma;
217+
218+ /* cpu for rx queue */
219+ int cpu;
220+
221+ uint16_t rdh;
222+ uint16_t rdt;
179223 };
180224
181225 #define E1000_DESC_UNUSED(R) \
182226 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
183227 (R)->next_to_clean - (R)->next_to_use - 1)
184228
229+#define E1000_RX_DESC_PS(R, i) \
230+ (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
231+#define E1000_RX_DESC_EXT(R, i) \
232+ (&(((union e1000_rx_desc_extended *)((R).desc))[i]))
185233 #define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
186234 #define E1000_RX_DESC(R, i) E1000_GET_DESC(R, i, e1000_rx_desc)
187235 #define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
@@ -193,27 +241,44 @@ struct e1000_adapter {
193241 struct timer_list tx_fifo_stall_timer;
194242 struct timer_list watchdog_timer;
195243 struct timer_list phy_info_timer;
244+#ifdef NETIF_F_HW_VLAN_TX
196245 struct vlan_group *vlgrp;
246+ uint16_t mng_vlan_id;
247+#endif
197248 uint32_t bd_number;
198249 uint32_t rx_buffer_len;
199- uint32_t part_num;
200250 uint32_t wol;
201251 uint32_t smartspeed;
202252 uint32_t en_mng_pt;
203253 uint16_t link_speed;
204254 uint16_t link_duplex;
205255 spinlock_t stats_lock;
256+#ifdef CONFIG_E1000_NAPI
257+ spinlock_t tx_queue_lock;
258+#endif
206259 atomic_t irq_sem;
207- struct tq_struct tx_timeout_task;
260+ unsigned int total_tx_bytes;
261+ unsigned int total_tx_packets;
262+ unsigned int total_rx_bytes;
263+ unsigned int total_rx_packets;
264+ /* Interrupt Throttle Rate */
265+ uint32_t itr;
266+ uint32_t itr_setting;
267+ uint16_t tx_itr;
268+ uint16_t rx_itr;
269+
270+ struct work_struct reset_task;
208271 uint8_t fc_autoneg;
209272
273+#ifdef ETHTOOL_PHYS_ID
210274 struct timer_list blink_timer;
211275 unsigned long led_status;
276+#endif
212277
213278 /* TX */
214- struct e1000_desc_ring tx_ring;
215- struct e1000_buffer previous_buffer_info;
216- spinlock_t tx_lock;
279+ struct e1000_tx_ring *tx_ring; /* One per active queue */
280+ unsigned int restart_queue;
281+ unsigned long tx_queue_len;
217282 uint32_t txd_cmd;
218283 uint32_t tx_int_delay;
219284 uint32_t tx_abs_int_delay;
@@ -221,25 +286,46 @@ struct e1000_adapter {
221286 uint64_t gotcl_old;
222287 uint64_t tpt_old;
223288 uint64_t colc_old;
289+ uint32_t tx_timeout_count;
224290 uint32_t tx_fifo_head;
225291 uint32_t tx_head_addr;
226292 uint32_t tx_fifo_size;
293+ uint8_t tx_timeout_factor;
227294 atomic_t tx_fifo_stall;
228295 boolean_t pcix_82544;
229296 boolean_t detect_tx_hung;
230297
231298 /* RX */
232- struct e1000_desc_ring rx_ring;
299+#ifdef CONFIG_E1000_NAPI
300+ boolean_t (*clean_rx) (struct e1000_adapter *adapter,
301+ struct e1000_rx_ring *rx_ring,
302+ int *work_done, int work_to_do);
303+#else
304+ boolean_t (*clean_rx) (struct e1000_adapter *adapter,
305+ struct e1000_rx_ring *rx_ring);
306+#endif
307+ void (*alloc_rx_buf) (struct e1000_adapter *adapter,
308+ struct e1000_rx_ring *rx_ring,
309+ int cleaned_count);
310+ struct e1000_rx_ring *rx_ring; /* One per active queue */
311+#ifdef CONFIG_E1000_NAPI
312+ struct net_device *polling_netdev; /* One per active queue */
313+#endif
314+ int num_tx_queues;
315+ int num_rx_queues;
316+
233317 uint64_t hw_csum_err;
234318 uint64_t hw_csum_good;
319+ uint64_t rx_hdr_split;
320+ uint32_t alloc_rx_buff_failed;
235321 uint32_t rx_int_delay;
236322 uint32_t rx_abs_int_delay;
237323 boolean_t rx_csum;
324+ unsigned int rx_ps_pages;
238325 uint32_t gorcl;
239326 uint64_t gorcl_old;
327+ uint16_t rx_ps_bsize0;
240328
241- /* Interrupt Throttle Rate */
242- uint32_t itr;
243329
244330 /* OS defined structs */
245331 struct net_device *netdev;
@@ -252,12 +338,37 @@ struct e1000_adapter {
252338 struct e1000_phy_info phy_info;
253339 struct e1000_phy_stats phy_stats;
254340
341+#ifdef ETHTOOL_TEST
255342 uint32_t test_icr;
256- struct e1000_desc_ring test_tx_ring;
257- struct e1000_desc_ring test_rx_ring;
343+ struct e1000_tx_ring test_tx_ring;
344+ struct e1000_rx_ring test_rx_ring;
345+#endif
258346
347+#ifdef E1000_COUNT_ICR
348+ uint64_t icr_txdw;
349+ uint64_t icr_txqe;
350+ uint64_t icr_lsc;
351+ uint64_t icr_rxseq;
352+ uint64_t icr_rxdmt;
353+ uint64_t icr_rxo;
354+ uint64_t icr_rxt;
355+ uint64_t icr_mdac;
356+ uint64_t icr_rxcfg;
357+ uint64_t icr_gpi;
358+#endif
259359
260- uint32_t pci_state[16];
360+ uint32_t *config_space;
261361 int msg_enable;
362+ /* to not mess up cache alignment, always add to the bottom */
363+ boolean_t smart_power_down; /* phy smart power down */
364+ boolean_t quad_port_a;
365+ unsigned long flags;
366+ uint32_t eeprom_wol;
367+};
368+
369+enum e1000_state_t {
370+ __E1000_TESTING,
371+ __E1000_RESETTING,
372+ __E1000_DOWN
262373 };
263374 #endif /* _E1000_H_ */
--- a/drivers/net/e1000/e1000_ethtool.c
+++ b/drivers/net/e1000/e1000_ethtool.c
@@ -1,27 +1,27 @@
11 /*******************************************************************************
22
3-
4- Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
5-
6- This program is free software; you can redistribute it and/or modify it
7- under the terms of the GNU General Public License as published by the Free
8- Software Foundation; either version 2 of the License, or (at your option)
9- any later version.
10-
11- This program is distributed in the hope that it will be useful, but WITHOUT
12- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
3+ Intel PRO/1000 Linux driver
4+ Copyright(c) 1999 - 2006 Intel Corporation.
5+
6+ This program is free software; you can redistribute it and/or modify it
7+ under the terms and conditions of the GNU General Public License,
8+ version 2, as published by the Free Software Foundation.
9+
10+ This program is distributed in the hope it will be useful, but WITHOUT
11+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1413 more details.
15-
14+
1615 You should have received a copy of the GNU General Public License along with
17- this program; if not, write to the Free Software Foundation, Inc., 59
18- Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19-
20- The full GNU General Public License is included in this distribution in the
21- file called LICENSE.
22-
16+ this program; if not, write to the Free Software Foundation, Inc.,
17+ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18+
19+ The full GNU General Public License is included in this distribution in
20+ the file called "COPYING".
21+
2322 Contact Information:
2423 Linux NICS <linux.nics@intel.com>
24+ e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
2525 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
2626
2727 *******************************************************************************/
@@ -30,6 +30,7 @@
3030
3131 #include "e1000.h"
3232
33+#ifdef SIOCETHTOOL
3334 #include <asm/uaccess.h>
3435
3536 extern char e1000_driver_name[];
@@ -37,14 +38,16 @@ extern char e1000_driver_version[];
3738
3839 extern int e1000_up(struct e1000_adapter *adapter);
3940 extern void e1000_down(struct e1000_adapter *adapter);
41+extern void e1000_reinit_locked(struct e1000_adapter *adapter);
4042 extern void e1000_reset(struct e1000_adapter *adapter);
4143 extern int e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx);
42-extern int e1000_setup_rx_resources(struct e1000_adapter *adapter);
43-extern int e1000_setup_tx_resources(struct e1000_adapter *adapter);
44-extern void e1000_free_rx_resources(struct e1000_adapter *adapter);
45-extern void e1000_free_tx_resources(struct e1000_adapter *adapter);
44+extern int e1000_setup_all_rx_resources(struct e1000_adapter *adapter);
45+extern int e1000_setup_all_tx_resources(struct e1000_adapter *adapter);
46+extern void e1000_free_all_rx_resources(struct e1000_adapter *adapter);
47+extern void e1000_free_all_tx_resources(struct e1000_adapter *adapter);
4648 extern void e1000_update_stats(struct e1000_adapter *adapter);
4749
50+#ifdef ETHTOOL_GSTATS
4851 struct e1000_stats {
4952 char stat_string[ETH_GSTRING_LEN];
5053 int sizeof_stat;
@@ -54,31 +57,36 @@ struct e1000_stats {
5457 #define E1000_STAT(m) sizeof(((struct e1000_adapter *)0)->m), \
5558 offsetof(struct e1000_adapter, m)
5659 static const struct e1000_stats e1000_gstrings_stats[] = {
57- { "rx_packets", E1000_STAT(net_stats.rx_packets) },
58- { "tx_packets", E1000_STAT(net_stats.tx_packets) },
59- { "rx_bytes", E1000_STAT(net_stats.rx_bytes) },
60- { "tx_bytes", E1000_STAT(net_stats.tx_bytes) },
60+ { "rx_packets", E1000_STAT(stats.gprc) },
61+ { "tx_packets", E1000_STAT(stats.gptc) },
62+ { "rx_bytes", E1000_STAT(stats.gorcl) },
63+ { "tx_bytes", E1000_STAT(stats.gotcl) },
64+ { "rx_broadcast", E1000_STAT(stats.bprc) },
65+ { "tx_broadcast", E1000_STAT(stats.bptc) },
66+ { "rx_multicast", E1000_STAT(stats.mprc) },
67+ { "tx_multicast", E1000_STAT(stats.mptc) },
6168 { "rx_errors", E1000_STAT(net_stats.rx_errors) },
6269 { "tx_errors", E1000_STAT(net_stats.tx_errors) },
63- { "rx_dropped", E1000_STAT(net_stats.rx_dropped) },
6470 { "tx_dropped", E1000_STAT(net_stats.tx_dropped) },
65- { "multicast", E1000_STAT(net_stats.multicast) },
66- { "collisions", E1000_STAT(net_stats.collisions) },
71+ { "multicast", E1000_STAT(stats.mprc) },
72+ { "collisions", E1000_STAT(stats.colc) },
6773 { "rx_length_errors", E1000_STAT(net_stats.rx_length_errors) },
6874 { "rx_over_errors", E1000_STAT(net_stats.rx_over_errors) },
69- { "rx_crc_errors", E1000_STAT(net_stats.rx_crc_errors) },
75+ { "rx_crc_errors", E1000_STAT(stats.crcerrs) },
7076 { "rx_frame_errors", E1000_STAT(net_stats.rx_frame_errors) },
71- { "rx_fifo_errors", E1000_STAT(net_stats.rx_fifo_errors) },
72- { "rx_missed_errors", E1000_STAT(net_stats.rx_missed_errors) },
73- { "tx_aborted_errors", E1000_STAT(net_stats.tx_aborted_errors) },
74- { "tx_carrier_errors", E1000_STAT(net_stats.tx_carrier_errors) },
77+ { "rx_no_buffer_count", E1000_STAT(stats.rnbc) },
78+ { "rx_missed_errors", E1000_STAT(stats.mpc) },
79+ { "tx_aborted_errors", E1000_STAT(stats.ecol) },
80+ { "tx_carrier_errors", E1000_STAT(stats.tncrs) },
7581 { "tx_fifo_errors", E1000_STAT(net_stats.tx_fifo_errors) },
7682 { "tx_heartbeat_errors", E1000_STAT(net_stats.tx_heartbeat_errors) },
77- { "tx_window_errors", E1000_STAT(net_stats.tx_window_errors) },
83+ { "tx_window_errors", E1000_STAT(stats.latecol) },
7884 { "tx_abort_late_coll", E1000_STAT(stats.latecol) },
7985 { "tx_deferred_ok", E1000_STAT(stats.dc) },
8086 { "tx_single_coll_ok", E1000_STAT(stats.scc) },
8187 { "tx_multi_coll_ok", E1000_STAT(stats.mcc) },
88+ { "tx_timeout_count", E1000_STAT(tx_timeout_count) },
89+ { "tx_restart_queue", E1000_STAT(restart_queue) },
8290 { "rx_long_length_errors", E1000_STAT(stats.roc) },
8391 { "rx_short_length_errors", E1000_STAT(stats.ruc) },
8492 { "rx_align_errors", E1000_STAT(stats.algnerrc) },
@@ -90,24 +98,47 @@ static const struct e1000_stats e1000_gstrings_stats[] = {
9098 { "tx_flow_control_xoff", E1000_STAT(stats.xofftxc) },
9199 { "rx_long_byte_count", E1000_STAT(stats.gorcl) },
92100 { "rx_csum_offload_good", E1000_STAT(hw_csum_good) },
93- { "rx_csum_offload_errors", E1000_STAT(hw_csum_err) }
101+ { "rx_csum_offload_errors", E1000_STAT(hw_csum_err) },
102+ { "rx_header_split", E1000_STAT(rx_hdr_split) },
103+ { "alloc_rx_buff_failed", E1000_STAT(alloc_rx_buff_failed) },
104+ { "tx_smbus", E1000_STAT(stats.mgptc) },
105+ { "rx_smbus", E1000_STAT(stats.mgprc) },
106+ { "dropped_smbus", E1000_STAT(stats.mgpdc) },
107+#ifdef E1000_COUNT_ICR
108+ { "txdw", E1000_STAT(icr_txdw) },
109+ { "txqe", E1000_STAT(icr_txqe) },
110+ { "lsc", E1000_STAT(icr_lsc) },
111+ { "rxseq", E1000_STAT(icr_rxseq) },
112+ { "rxdmt", E1000_STAT(icr_rxdmt) },
113+ { "rxo", E1000_STAT(icr_rxo) },
114+ { "rxt", E1000_STAT(icr_rxt) },
115+ { "mdac", E1000_STAT(icr_mdac) },
116+ { "rxcfg", E1000_STAT(icr_rxcfg) },
117+ { "gpi", E1000_STAT(icr_gpi) },
118+#endif
94119 };
95-#define E1000_STATS_LEN \
120+
121+#define E1000_QUEUE_STATS_LEN 0
122+#define E1000_GLOBAL_STATS_LEN \
96123 sizeof(e1000_gstrings_stats) / sizeof(struct e1000_stats)
124+#define E1000_STATS_LEN (E1000_GLOBAL_STATS_LEN + E1000_QUEUE_STATS_LEN)
125+#endif /* ETHTOOL_GSTATS */
126+#ifdef ETHTOOL_TEST
97127 static const char e1000_gstrings_test[][ETH_GSTRING_LEN] = {
98128 "Register test (offline)", "Eeprom test (offline)",
99129 "Interrupt test (offline)", "Loopback test (offline)",
100130 "Link test (on/offline)"
101131 };
102132 #define E1000_TEST_LEN sizeof(e1000_gstrings_test) / ETH_GSTRING_LEN
133+#endif /* ETHTOOL_TEST */
103134
104135 static int
105136 e1000_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
106137 {
107- struct e1000_adapter *adapter = netdev->priv;
138+ struct e1000_adapter *adapter = netdev_priv(netdev);
108139 struct e1000_hw *hw = &adapter->hw;
109140
110- if(hw->media_type == e1000_media_type_copper) {
141+ if (hw->media_type == e1000_media_type_copper) {
111142
112143 ecmd->supported = (SUPPORTED_10baseT_Half |
113144 SUPPORTED_10baseT_Full |
@@ -116,21 +147,20 @@ e1000_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
116147 SUPPORTED_1000baseT_Full|
117148 SUPPORTED_Autoneg |
118149 SUPPORTED_TP);
119-
150+ if (hw->phy_type == e1000_phy_ife)
151+ ecmd->supported &= ~SUPPORTED_1000baseT_Full;
120152 ecmd->advertising = ADVERTISED_TP;
121153
122- if(hw->autoneg == 1) {
154+ if (hw->autoneg == 1) {
123155 ecmd->advertising |= ADVERTISED_Autoneg;
124-
125156 /* the e1000 autoneg seems to match ethtool nicely */
126-
127157 ecmd->advertising |= hw->autoneg_advertised;
128158 }
129159
130160 ecmd->port = PORT_TP;
131161 ecmd->phy_address = hw->phy_addr;
132162
133- if(hw->mac_type == e1000_82543)
163+ if (hw->mac_type == e1000_82543)
134164 ecmd->transceiver = XCVR_EXTERNAL;
135165 else
136166 ecmd->transceiver = XCVR_INTERNAL;
@@ -140,19 +170,19 @@ e1000_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
140170 SUPPORTED_FIBRE |
141171 SUPPORTED_Autoneg);
142172
143- ecmd->advertising = (SUPPORTED_1000baseT_Full |
144- SUPPORTED_FIBRE |
145- SUPPORTED_Autoneg);
173+ ecmd->advertising = (ADVERTISED_1000baseT_Full |
174+ ADVERTISED_FIBRE |
175+ ADVERTISED_Autoneg);
146176
147177 ecmd->port = PORT_FIBRE;
148178
149- if(hw->mac_type >= e1000_82545)
179+ if (hw->mac_type >= e1000_82545)
150180 ecmd->transceiver = XCVR_INTERNAL;
151181 else
152182 ecmd->transceiver = XCVR_EXTERNAL;
153183 }
154184
155- if(netif_carrier_ok(adapter->netdev)) {
185+ if (netif_carrier_ok(adapter->netdev)) {
156186
157187 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
158188 &adapter->link_duplex);
@@ -161,7 +191,7 @@ e1000_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
161191 /* unfortunatly FULL_DUPLEX != DUPLEX_FULL
162192 * and HALF_DUPLEX != DUPLEX_HALF */
163193
164- if(adapter->link_duplex == FULL_DUPLEX)
194+ if (adapter->link_duplex == FULL_DUPLEX)
165195 ecmd->duplex = DUPLEX_FULL;
166196 else
167197 ecmd->duplex = DUPLEX_HALF;
@@ -178,26 +208,46 @@ e1000_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
178208 static int
179209 e1000_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
180210 {
181- struct e1000_adapter *adapter = netdev->priv;
211+ struct e1000_adapter *adapter = netdev_priv(netdev);
182212 struct e1000_hw *hw = &adapter->hw;
183213
184- if(ecmd->autoneg == AUTONEG_ENABLE) {
214+ /* When SoL/IDER sessions are active, autoneg/speed/duplex
215+ * cannot be changed */
216+ if (e1000_check_phy_reset_block(hw)) {
217+ DPRINTK(DRV, ERR, "Cannot change link characteristics "
218+ "when SoL/IDER is active.\n");
219+ return -EINVAL;
220+ }
221+
222+ while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
223+ msleep(1);
224+
225+ if (ecmd->autoneg == AUTONEG_ENABLE) {
185226 hw->autoneg = 1;
186- hw->autoneg_advertised = 0x002F;
187- ecmd->advertising = 0x002F;
227+ if (hw->media_type == e1000_media_type_fiber)
228+ hw->autoneg_advertised = ADVERTISED_1000baseT_Full |
229+ ADVERTISED_FIBRE |
230+ ADVERTISED_Autoneg;
231+ else
232+ hw->autoneg_advertised = ecmd->advertising |
233+ ADVERTISED_TP |
234+ ADVERTISED_Autoneg;
235+ ecmd->advertising = hw->autoneg_advertised;
188236 } else
189- if(e1000_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex))
237+ if (e1000_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {
238+ clear_bit(__E1000_RESETTING, &adapter->flags);
190239 return -EINVAL;
240+ }
191241
192242 /* reset the link */
193243
194- if(netif_running(adapter->netdev)) {
244+ if (netif_running(adapter->netdev)) {
195245 e1000_down(adapter);
196- e1000_reset(adapter);
197246 e1000_up(adapter);
198247 } else
199248 e1000_reset(adapter);
200249
250+ clear_bit(__E1000_RESETTING, &adapter->flags);
201251 return 0;
202252 }
203253
@@ -205,17 +255,17 @@ static void
205255 e1000_get_pauseparam(struct net_device *netdev,
206256 struct ethtool_pauseparam *pause)
207257 {
208- struct e1000_adapter *adapter = netdev->priv;
258+ struct e1000_adapter *adapter = netdev_priv(netdev);
209259 struct e1000_hw *hw = &adapter->hw;
210260
211- pause->autoneg =
261+ pause->autoneg =
212262 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
213-
214- if(hw->fc == e1000_fc_rx_pause)
263+
264+ if (hw->fc == E1000_FC_RX_PAUSE)
215265 pause->rx_pause = 1;
216- else if(hw->fc == e1000_fc_tx_pause)
266+ else if (hw->fc == E1000_FC_TX_PAUSE)
217267 pause->tx_pause = 1;
218- else if(hw->fc == e1000_fc_full) {
268+ else if (hw->fc == E1000_FC_FULL) {
219269 pause->rx_pause = 1;
220270 pause->tx_pause = 1;
221271 }
@@ -225,57 +275,60 @@ static int
225275 e1000_set_pauseparam(struct net_device *netdev,
226276 struct ethtool_pauseparam *pause)
227277 {
228- struct e1000_adapter *adapter = netdev->priv;
278+ struct e1000_adapter *adapter = netdev_priv(netdev);
229279 struct e1000_hw *hw = &adapter->hw;
230-
280+ int retval = 0;
281+
231282 adapter->fc_autoneg = pause->autoneg;
232283
233- if(pause->rx_pause && pause->tx_pause)
234- hw->fc = e1000_fc_full;
235- else if(pause->rx_pause && !pause->tx_pause)
236- hw->fc = e1000_fc_rx_pause;
237- else if(!pause->rx_pause && pause->tx_pause)
238- hw->fc = e1000_fc_tx_pause;
239- else if(!pause->rx_pause && !pause->tx_pause)
240- hw->fc = e1000_fc_none;
284+ while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
285+ msleep(1);
286+
287+ if (pause->rx_pause && pause->tx_pause)
288+ hw->fc = E1000_FC_FULL;
289+ else if (pause->rx_pause && !pause->tx_pause)
290+ hw->fc = E1000_FC_RX_PAUSE;
291+ else if (!pause->rx_pause && pause->tx_pause)
292+ hw->fc = E1000_FC_TX_PAUSE;
293+ else if (!pause->rx_pause && !pause->tx_pause)
294+ hw->fc = E1000_FC_NONE;
241295
242296 hw->original_fc = hw->fc;
243297
244- if(adapter->fc_autoneg == AUTONEG_ENABLE) {
245- if(netif_running(adapter->netdev)) {
298+ if (adapter->fc_autoneg == AUTONEG_ENABLE) {
299+ if (netif_running(adapter->netdev)) {
246300 e1000_down(adapter);
247301 e1000_up(adapter);
248302 } else
249303 e1000_reset(adapter);
250- }
251- else
252- return ((hw->media_type == e1000_media_type_fiber) ?
253- e1000_setup_link(hw) : e1000_force_mac_fc(hw));
254-
255- return 0;
304+ } else
305+ retval = ((hw->media_type == e1000_media_type_fiber) ?
306+ e1000_setup_link(hw) : e1000_force_mac_fc(hw));
307+
308+ clear_bit(__E1000_RESETTING, &adapter->flags);
309+ return retval;
256310 }
257311
258312 static uint32_t
259313 e1000_get_rx_csum(struct net_device *netdev)
260314 {
261- struct e1000_adapter *adapter = netdev->priv;
315+ struct e1000_adapter *adapter = netdev_priv(netdev);
262316 return adapter->rx_csum;
263317 }
264318
265319 static int
266320 e1000_set_rx_csum(struct net_device *netdev, uint32_t data)
267321 {
268- struct e1000_adapter *adapter = netdev->priv;
322+ struct e1000_adapter *adapter = netdev_priv(netdev);
269323 adapter->rx_csum = data;
270324
271- if(netif_running(netdev)) {
272- e1000_down(adapter);
273- e1000_up(adapter);
274- } else
325+ if (netif_running(netdev))
326+ e1000_reinit_locked(adapter);
327+ else
275328 e1000_reset(adapter);
276329 return 0;
277330 }
278-
331+
279332 static uint32_t
280333 e1000_get_tx_csum(struct net_device *netdev)
281334 {
@@ -285,9 +338,9 @@ e1000_get_tx_csum(struct net_device *netdev)
285338 static int
286339 e1000_set_tx_csum(struct net_device *netdev, uint32_t data)
287340 {
288- struct e1000_adapter *adapter = netdev->priv;
341+ struct e1000_adapter *adapter = netdev_priv(netdev);
289342
290- if(adapter->hw.mac_type < e1000_82543) {
343+ if (adapter->hw.mac_type < e1000_82543) {
291344 if (!data)
292345 return -EINVAL;
293346 return 0;
@@ -301,38 +354,21 @@ e1000_set_tx_csum(struct net_device *netdev, uint32_t data)
301354 return 0;
302355 }
303356
304-#ifdef NETIF_F_TSO
305-static int
306-e1000_set_tso(struct net_device *netdev, uint32_t data)
307-{
308- struct e1000_adapter *adapter = netdev->priv;
309- if ((adapter->hw.mac_type < e1000_82544) ||
310- (adapter->hw.mac_type == e1000_82547))
311- return data ? -EINVAL : 0;
312-
313- if (data)
314- netdev->features |= NETIF_F_TSO;
315- else
316- netdev->features &= ~NETIF_F_TSO;
317- return 0;
318-}
319-#endif /* NETIF_F_TSO */
320-
321357 static uint32_t
322358 e1000_get_msglevel(struct net_device *netdev)
323359 {
324- struct e1000_adapter *adapter = netdev->priv;
360+ struct e1000_adapter *adapter = netdev_priv(netdev);
325361 return adapter->msg_enable;
326362 }
327363
328364 static void
329365 e1000_set_msglevel(struct net_device *netdev, uint32_t data)
330366 {
331- struct e1000_adapter *adapter = netdev->priv;
367+ struct e1000_adapter *adapter = netdev_priv(netdev);
332368 adapter->msg_enable = data;
333369 }
334370
335-static int
371+static int
336372 e1000_get_regs_len(struct net_device *netdev)
337373 {
338374 #define E1000_REGS_LEN 32
@@ -343,7 +379,7 @@ static void
343379 e1000_get_regs(struct net_device *netdev,
344380 struct ethtool_regs *regs, void *p)
345381 {
346- struct e1000_adapter *adapter = netdev->priv;
382+ struct e1000_adapter *adapter = netdev_priv(netdev);
347383 struct e1000_hw *hw = &adapter->hw;
348384 uint32_t *regs_buff = p;
349385 uint16_t phy_data;
@@ -368,7 +404,7 @@ e1000_get_regs(struct net_device *netdev,
368404 regs_buff[11] = E1000_READ_REG(hw, TIDV);
369405
370406 regs_buff[12] = adapter->hw.phy_type; /* PHY type (IGP=1, M88=0) */
371- if(hw->phy_type == e1000_phy_igp) {
407+ if (hw->phy_type == e1000_phy_igp) {
372408 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
373409 IGP01E1000_PHY_AGC_A);
374410 e1000_read_phy_reg(hw, IGP01E1000_PHY_AGC_A &
@@ -404,12 +440,12 @@ e1000_get_regs(struct net_device *netdev,
404440 regs_buff[23] = regs_buff[18]; /* mdix mode */
405441 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0);
406442 } else {
407- e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
443+ e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
408444 regs_buff[13] = (uint32_t)phy_data; /* cable length */
409445 regs_buff[14] = 0; /* Dummy (to align w/ IGP phy reg dump) */
410446 regs_buff[15] = 0; /* Dummy (to align w/ IGP phy reg dump) */
411447 regs_buff[16] = 0; /* Dummy (to align w/ IGP phy reg dump) */
412- e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
448+ e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
413449 regs_buff[17] = (uint32_t)phy_data; /* extended 10bt distance */
414450 regs_buff[18] = regs_buff[13]; /* cable polarity */
415451 regs_buff[19] = 0; /* Dummy (to align w/ IGP phy reg dump) */
@@ -422,8 +458,9 @@ e1000_get_regs(struct net_device *netdev,
422458 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
423459 regs_buff[24] = (uint32_t)phy_data; /* phy local receiver status */
424460 regs_buff[25] = regs_buff[24]; /* phy remote receiver status */
425- if(hw->mac_type >= e1000_82540 &&
426- hw->media_type == e1000_media_type_copper) {
461+ if (hw->mac_type >= e1000_82540 &&
462+ hw->mac_type < e1000_82571 &&
463+ hw->media_type == e1000_media_type_copper) {
427464 regs_buff[26] = E1000_READ_REG(hw, MANC);
428465 }
429466 }
@@ -431,7 +468,7 @@ e1000_get_regs(struct net_device *netdev,
431468 static int
432469 e1000_get_eeprom_len(struct net_device *netdev)
433470 {
434- struct e1000_adapter *adapter = netdev->priv;
471+ struct e1000_adapter *adapter = netdev_priv(netdev);
435472 return adapter->hw.eeprom.word_size * 2;
436473 }
437474
@@ -439,14 +476,14 @@ static int
439476 e1000_get_eeprom(struct net_device *netdev,
440477 struct ethtool_eeprom *eeprom, uint8_t *bytes)
441478 {
442- struct e1000_adapter *adapter = netdev->priv;
479+ struct e1000_adapter *adapter = netdev_priv(netdev);
443480 struct e1000_hw *hw = &adapter->hw;
444481 uint16_t *eeprom_buff;
445482 int first_word, last_word;
446483 int ret_val = 0;
447484 uint16_t i;
448485
449- if(eeprom->len == 0)
486+ if (eeprom->len == 0)
450487 return -EINVAL;
451488
452489 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
@@ -456,16 +493,16 @@ e1000_get_eeprom(struct net_device *netdev,
456493
457494 eeprom_buff = kmalloc(sizeof(uint16_t) *
458495 (last_word - first_word + 1), GFP_KERNEL);
459- if(!eeprom_buff)
496+ if (!eeprom_buff)
460497 return -ENOMEM;
461498
462- if(hw->eeprom.type == e1000_eeprom_spi)
499+ if (hw->eeprom.type == e1000_eeprom_spi)
463500 ret_val = e1000_read_eeprom(hw, first_word,
464501 last_word - first_word + 1,
465502 eeprom_buff);
466503 else {
467504 for (i = 0; i < last_word - first_word + 1; i++)
468- if((ret_val = e1000_read_eeprom(hw, first_word + i, 1,
505+ if ((ret_val = e1000_read_eeprom(hw, first_word + i, 1,
469506 &eeprom_buff[i])))
470507 break;
471508 }
@@ -485,17 +522,17 @@ static int
485522 e1000_set_eeprom(struct net_device *netdev,
486523 struct ethtool_eeprom *eeprom, uint8_t *bytes)
487524 {
488- struct e1000_adapter *adapter = netdev->priv;
525+ struct e1000_adapter *adapter = netdev_priv(netdev);
489526 struct e1000_hw *hw = &adapter->hw;
490527 uint16_t *eeprom_buff;
491528 void *ptr;
492529 int max_len, first_word, last_word, ret_val = 0;
493530 uint16_t i;
494531
495- if(eeprom->len == 0)
532+ if (eeprom->len == 0)
496533 return -EOPNOTSUPP;
497534
498- if(eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
535+ if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
499536 return -EFAULT;
500537
501538 max_len = hw->eeprom.word_size * 2;
@@ -503,19 +540,19 @@ e1000_set_eeprom(struct net_device *netdev,
503540 first_word = eeprom->offset >> 1;
504541 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
505542 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
506- if(!eeprom_buff)
543+ if (!eeprom_buff)
507544 return -ENOMEM;
508545
509546 ptr = (void *)eeprom_buff;
510547
511- if(eeprom->offset & 1) {
548+ if (eeprom->offset & 1) {
512549 /* need read/modify/write of first changed EEPROM word */
513550 /* only the second byte of the word is being modified */
514551 ret_val = e1000_read_eeprom(hw, first_word, 1,
515552 &eeprom_buff[0]);
516553 ptr++;
517554 }
518- if(((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
555+ if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
519556 /* need read/modify/write of last changed EEPROM word */
520557 /* only the first byte of the word is being modified */
521558 ret_val = e1000_read_eeprom(hw, last_word, 1,
@@ -534,8 +571,10 @@ e1000_set_eeprom(struct net_device *netdev,
534571 ret_val = e1000_write_eeprom(hw, first_word,
535572 last_word - first_word + 1, eeprom_buff);
536573
537- /* Update the checksum over the first part of the EEPROM if needed */
538- if((ret_val == 0) && first_word <= EEPROM_CHECKSUM_REG)
574+ /* Update the checksum over the first part of the EEPROM if needed
575+ * and flush shadow RAM for 82573 conrollers */
576+ if ((ret_val == 0) && ((first_word <= EEPROM_CHECKSUM_REG) ||
577+ (hw->mac_type == e1000_82573)))
539578 e1000_update_eeprom_checksum(hw);
540579
541580 kfree(eeprom_buff);
@@ -546,11 +585,32 @@ static void
546585 e1000_get_drvinfo(struct net_device *netdev,
547586 struct ethtool_drvinfo *drvinfo)
548587 {
549- struct e1000_adapter *adapter = netdev->priv;
588+ struct e1000_adapter *adapter = netdev_priv(netdev);
589+ char firmware_version[32];
590+ uint16_t eeprom_data;
550591
551592 strncpy(drvinfo->driver, e1000_driver_name, 32);
552593 strncpy(drvinfo->version, e1000_driver_version, 32);
553- strncpy(drvinfo->fw_version, "N/A", 32);
594+
595+ /* EEPROM image version # is reported as firmware version # for
596+ * 8257{1|2|3} controllers */
597+ e1000_read_eeprom(&adapter->hw, 5, 1, &eeprom_data);
598+ switch (adapter->hw.mac_type) {
599+ case e1000_82571:
600+ case e1000_82572:
601+ case e1000_82573:
602+ case e1000_80003es2lan:
603+ case e1000_ich8lan:
604+ sprintf(firmware_version, "%d.%d-%d",
605+ (eeprom_data & 0xF000) >> 12,
606+ (eeprom_data & 0x0FF0) >> 4,
607+ eeprom_data & 0x000F);
608+ break;
609+ default:
610+ sprintf(firmware_version, "N/A");
611+ }
612+
613+ strncpy(drvinfo->fw_version, firmware_version, 32);
554614 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
555615 drvinfo->n_stats = E1000_STATS_LEN;
556616 drvinfo->testinfo_len = E1000_TEST_LEN;
@@ -562,10 +622,10 @@ static void
562622 e1000_get_ringparam(struct net_device *netdev,
563623 struct ethtool_ringparam *ring)
564624 {
565- struct e1000_adapter *adapter = netdev->priv;
625+ struct e1000_adapter *adapter = netdev_priv(netdev);
566626 e1000_mac_type mac_type = adapter->hw.mac_type;
567- struct e1000_desc_ring *txdr = &adapter->tx_ring;
568- struct e1000_desc_ring *rxdr = &adapter->rx_ring;
627+ struct e1000_tx_ring *txdr = adapter->tx_ring;
628+ struct e1000_rx_ring *rxdr = adapter->rx_ring;
569629
570630 ring->rx_max_pending = (mac_type < e1000_82544) ? E1000_MAX_RXD :
571631 E1000_MAX_82544_RXD;
@@ -579,65 +639,94 @@ e1000_get_ringparam(struct net_device *netdev,
579639 ring->rx_jumbo_pending = 0;
580640 }
581641
582-static int
642+static int
583643 e1000_set_ringparam(struct net_device *netdev,
584644 struct ethtool_ringparam *ring)
585645 {
586- struct e1000_adapter *adapter = netdev->priv;
646+ struct e1000_adapter *adapter = netdev_priv(netdev);
587647 e1000_mac_type mac_type = adapter->hw.mac_type;
588- struct e1000_desc_ring *txdr = &adapter->tx_ring;
589- struct e1000_desc_ring *rxdr = &adapter->rx_ring;
590- struct e1000_desc_ring tx_old, tx_new, rx_old, rx_new;
591- int err;
648+ struct e1000_tx_ring *txdr, *tx_old;
649+ struct e1000_rx_ring *rxdr, *rx_old;
650+ int i, err, tx_ring_size, rx_ring_size;
651+
652+ if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
653+ return -EINVAL;
654+
655+ tx_ring_size = sizeof(struct e1000_tx_ring) * adapter->num_tx_queues;
656+ rx_ring_size = sizeof(struct e1000_rx_ring) * adapter->num_rx_queues;
657+
658+ while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
659+ msleep(1);
660+
661+ if (netif_running(adapter->netdev))
662+ e1000_down(adapter);
592663
593664 tx_old = adapter->tx_ring;
594665 rx_old = adapter->rx_ring;
595666
596- if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
597- return -EINVAL;
667+ err = -ENOMEM;
668+ txdr = kzalloc(tx_ring_size, GFP_KERNEL);
669+ if (!txdr)
670+ goto err_alloc_tx;
598671
599- if(netif_running(adapter->netdev))
600- e1000_down(adapter);
672+ rxdr = kzalloc(rx_ring_size, GFP_KERNEL);
673+ if (!rxdr)
674+ goto err_alloc_rx;
675+
676+ adapter->tx_ring = txdr;
677+ adapter->rx_ring = rxdr;
601678
602679 rxdr->count = max(ring->rx_pending,(uint32_t)E1000_MIN_RXD);
603680 rxdr->count = min(rxdr->count,(uint32_t)(mac_type < e1000_82544 ?
604681 E1000_MAX_RXD : E1000_MAX_82544_RXD));
605- E1000_ROUNDUP(rxdr->count, REQ_RX_DESCRIPTOR_MULTIPLE);
682+ E1000_ROUNDUP(rxdr->count, REQ_RX_DESCRIPTOR_MULTIPLE);
606683
607684 txdr->count = max(ring->tx_pending,(uint32_t)E1000_MIN_TXD);
608685 txdr->count = min(txdr->count,(uint32_t)(mac_type < e1000_82544 ?
609686 E1000_MAX_TXD : E1000_MAX_82544_TXD));
610- E1000_ROUNDUP(txdr->count, REQ_TX_DESCRIPTOR_MULTIPLE);
687+ E1000_ROUNDUP(txdr->count, REQ_TX_DESCRIPTOR_MULTIPLE);
611688
612- if(netif_running(adapter->netdev)) {
689+ for (i = 0; i < adapter->num_tx_queues; i++)
690+ txdr[i].count = txdr->count;
691+ for (i = 0; i < adapter->num_rx_queues; i++)
692+ rxdr[i].count = rxdr->count;
693+
694+ if (netif_running(adapter->netdev)) {
613695 /* Try to get new resources before deleting old */
614- if((err = e1000_setup_rx_resources(adapter)))
696+ if ((err = e1000_setup_all_rx_resources(adapter)))
615697 goto err_setup_rx;
616- if((err = e1000_setup_tx_resources(adapter)))
698+ if ((err = e1000_setup_all_tx_resources(adapter)))
617699 goto err_setup_tx;
618700
619701 /* save the new, restore the old in order to free it,
620702 * then restore the new back again */
621703
622- rx_new = adapter->rx_ring;
623- tx_new = adapter->tx_ring;
624704 adapter->rx_ring = rx_old;
625705 adapter->tx_ring = tx_old;
626- e1000_free_rx_resources(adapter);
627- e1000_free_tx_resources(adapter);
628- adapter->rx_ring = rx_new;
629- adapter->tx_ring = tx_new;
630- if((err = e1000_up(adapter)))
631- return err;
706+ e1000_free_all_rx_resources(adapter);
707+ e1000_free_all_tx_resources(adapter);
708+ kfree(tx_old);
709+ kfree(rx_old);
710+ adapter->rx_ring = rxdr;
711+ adapter->tx_ring = txdr;
712+ if ((err = e1000_up(adapter)))
713+ goto err_setup;
632714 }
633715
716+ clear_bit(__E1000_RESETTING, &adapter->flags);
634717 return 0;
635718 err_setup_tx:
636- e1000_free_rx_resources(adapter);
719+ e1000_free_all_rx_resources(adapter);
637720 err_setup_rx:
638721 adapter->rx_ring = rx_old;
639722 adapter->tx_ring = tx_old;
723+ kfree(rxdr);
724+err_alloc_rx:
725+ kfree(txdr);
726+err_alloc_tx:
640727 e1000_up(adapter);
728+err_setup:
729+ clear_bit(__E1000_RESETTING, &adapter->flags);
641730 return err;
642731 }
643732
@@ -646,10 +735,13 @@ err_setup_rx:
646735 uint32_t pat, value; \
647736 uint32_t test[] = \
648737 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \
649- for(pat = 0; pat < sizeof(test)/sizeof(test[0]); pat++) { \
738+ for (pat = 0; pat < sizeof(test)/sizeof(test[0]); pat++) { \
650739 E1000_WRITE_REG(&adapter->hw, R, (test[pat] & W)); \
651740 value = E1000_READ_REG(&adapter->hw, R); \
652- if(value != (test[pat] & W & M)) { \
741+ if (value != (test[pat] & W & M)) { \
742+ DPRINTK(DRV, ERR, "pattern test reg %04X failed: got " \
743+ "0x%08X expected 0x%08X\n", \
744+ E1000_##R, value, (test[pat] & W & M)); \
653745 *data = (adapter->hw.mac_type < e1000_82543) ? \
654746 E1000_82542_##R : E1000_##R; \
655747 return 1; \
@@ -663,6 +755,8 @@ err_setup_rx:
663755 E1000_WRITE_REG(&adapter->hw, R, W & M); \
664756 value = E1000_READ_REG(&adapter->hw, R); \
665757 if ((W & M) != (value & M)) { \
758+ DPRINTK(DRV, ERR, "set/check reg %04X test failed: got 0x%08X "\
759+ "expected 0x%08X\n", E1000_##R, (value & M), (W & M)); \
666760 *data = (adapter->hw.mac_type < e1000_82543) ? \
667761 E1000_82542_##R : E1000_##R; \
668762 return 1; \
@@ -672,23 +766,48 @@ err_setup_rx:
672766 static int
673767 e1000_reg_test(struct e1000_adapter *adapter, uint64_t *data)
674768 {
675- uint32_t value;
676- uint32_t i;
769+ uint32_t value, before, after;
770+ uint32_t i, toggle;
677771
678772 /* The status register is Read Only, so a write should fail.
679773 * Some bits that get toggled are ignored.
680774 */
681- value = (E1000_READ_REG(&adapter->hw, STATUS) & (0xFFFFF833));
682- E1000_WRITE_REG(&adapter->hw, STATUS, (0xFFFFFFFF));
683- if(value != (E1000_READ_REG(&adapter->hw, STATUS) & (0xFFFFF833))) {
775+ switch (adapter->hw.mac_type) {
776+ /* there are several bits on newer hardware that are r/w */
777+ case e1000_82571:
778+ case e1000_82572:
779+ case e1000_80003es2lan:
780+ toggle = 0x7FFFF3FF;
781+ break;
782+ case e1000_82573:
783+ case e1000_ich8lan:
784+ toggle = 0x7FFFF033;
785+ break;
786+ default:
787+ toggle = 0xFFFFF833;
788+ break;
789+ }
790+
791+ before = E1000_READ_REG(&adapter->hw, STATUS);
792+ value = (E1000_READ_REG(&adapter->hw, STATUS) & toggle);
793+ E1000_WRITE_REG(&adapter->hw, STATUS, toggle);
794+ after = E1000_READ_REG(&adapter->hw, STATUS) & toggle;
795+ if (value != after) {
796+ DPRINTK(DRV, ERR, "failed STATUS register test got: "
797+ "0x%08X expected: 0x%08X\n", after, value);
684798 *data = 1;
685799 return 1;
686800 }
801+ /* restore previous status */
802+ E1000_WRITE_REG(&adapter->hw, STATUS, before);
803+
804+ if (adapter->hw.mac_type != e1000_ich8lan) {
805+ REG_PATTERN_TEST(FCAL, 0xFFFFFFFF, 0xFFFFFFFF);
806+ REG_PATTERN_TEST(FCAH, 0x0000FFFF, 0xFFFFFFFF);
807+ REG_PATTERN_TEST(FCT, 0x0000FFFF, 0xFFFFFFFF);
808+ REG_PATTERN_TEST(VET, 0x0000FFFF, 0xFFFFFFFF);
809+ }
687810
688- REG_PATTERN_TEST(FCAL, 0xFFFFFFFF, 0xFFFFFFFF);
689- REG_PATTERN_TEST(FCAH, 0x0000FFFF, 0xFFFFFFFF);
690- REG_PATTERN_TEST(FCT, 0x0000FFFF, 0xFFFFFFFF);
691- REG_PATTERN_TEST(VET, 0x0000FFFF, 0xFFFFFFFF);
692811 REG_PATTERN_TEST(RDTR, 0x0000FFFF, 0xFFFFFFFF);
693812 REG_PATTERN_TEST(RDBAH, 0xFFFFFFFF, 0xFFFFFFFF);
694813 REG_PATTERN_TEST(RDLEN, 0x000FFF80, 0x000FFFFF);
@@ -701,22 +820,25 @@ e1000_reg_test(struct e1000_adapter *adapter, uint64_t *data)
701820 REG_PATTERN_TEST(TDLEN, 0x000FFF80, 0x000FFFFF);
702821
703822 REG_SET_AND_CHECK(RCTL, 0xFFFFFFFF, 0x00000000);
704- REG_SET_AND_CHECK(RCTL, 0x06DFB3FE, 0x003FFFFB);
823+
824+ before = (adapter->hw.mac_type == e1000_ich8lan ?
825+ 0x06C3B33E : 0x06DFB3FE);
826+ REG_SET_AND_CHECK(RCTL, before, 0x003FFFFB);
705827 REG_SET_AND_CHECK(TCTL, 0xFFFFFFFF, 0x00000000);
706828
707- if(adapter->hw.mac_type >= e1000_82543) {
829+ if (adapter->hw.mac_type >= e1000_82543) {
708830
709- REG_SET_AND_CHECK(RCTL, 0x06DFB3FE, 0xFFFFFFFF);
831+ REG_SET_AND_CHECK(RCTL, before, 0xFFFFFFFF);
710832 REG_PATTERN_TEST(RDBAL, 0xFFFFFFF0, 0xFFFFFFFF);
711- REG_PATTERN_TEST(TXCW, 0xC000FFFF, 0x0000FFFF);
833+ if (adapter->hw.mac_type != e1000_ich8lan)
834+ REG_PATTERN_TEST(TXCW, 0xC000FFFF, 0x0000FFFF);
712835 REG_PATTERN_TEST(TDBAL, 0xFFFFFFF0, 0xFFFFFFFF);
713836 REG_PATTERN_TEST(TIDV, 0x0000FFFF, 0x0000FFFF);
714-
715- for(i = 0; i < E1000_RAR_ENTRIES; i++) {
716- REG_PATTERN_TEST(RA + ((i << 1) << 2), 0xFFFFFFFF,
717- 0xFFFFFFFF);
837+ value = (adapter->hw.mac_type == e1000_ich8lan ?
838+ E1000_RAR_ENTRIES_ICH8LAN : E1000_RAR_ENTRIES);
839+ for (i = 0; i < value; i++) {
718840 REG_PATTERN_TEST(RA + (((i << 1) + 1) << 2), 0x8003FFFF,
719- 0xFFFFFFFF);
841+ 0xFFFFFFFF);
720842 }
721843
722844 } else {
@@ -728,7 +850,9 @@ e1000_reg_test(struct e1000_adapter *adapter, uint64_t *data)
728850
729851 }
730852
731- for(i = 0; i < E1000_MC_TBL_SIZE; i++)
853+ value = (adapter->hw.mac_type == e1000_ich8lan ?
854+ E1000_MC_TBL_SIZE_ICHXLAN : E1000_MC_TBL_SIZE);
855+ for (i = 0; i < value; i++)
732856 REG_PATTERN_TEST(MTA + (i << 2), 0xFFFFFFFF, 0xFFFFFFFF);
733857
734858 *data = 0;
@@ -744,8 +868,8 @@ e1000_eeprom_test(struct e1000_adapter *adapter, uint64_t *data)
744868
745869 *data = 0;
746870 /* Read and add up the contents of the EEPROM */
747- for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
748- if((e1000_read_eeprom(&adapter->hw, i, 1, &temp)) < 0) {
871+ for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
872+ if ((e1000_read_eeprom(&adapter->hw, i, 1, &temp)) < 0) {
749873 *data = 1;
750874 break;
751875 }
@@ -753,19 +877,17 @@ e1000_eeprom_test(struct e1000_adapter *adapter, uint64_t *data)
753877 }
754878
755879 /* If Checksum is not Correct return error else test passed */
756- if((checksum != (uint16_t) EEPROM_SUM) && !(*data))
880+ if ((checksum != (uint16_t) EEPROM_SUM) && !(*data))
757881 *data = 2;
758882
759883 return *data;
760884 }
761885
762886 static irqreturn_t
763-e1000_test_intr(int irq,
764- void *data,
765- struct pt_regs *regs)
887+e1000_test_intr(int irq, void *data)
766888 {
767889 struct net_device *netdev = (struct net_device *) data;
768- struct e1000_adapter *adapter = netdev->priv;
890+ struct e1000_adapter *adapter = netdev_priv(netdev);
769891
770892 adapter->test_icr |= E1000_READ_REG(&adapter->hw, ICR);
771893
@@ -776,46 +898,53 @@ static int
776898 e1000_intr_test(struct e1000_adapter *adapter, uint64_t *data)
777899 {
778900 struct net_device *netdev = adapter->netdev;
779- uint32_t mask, i=0, shared_int = TRUE;
780- uint32_t irq = adapter->pdev->irq;
901+ uint32_t mask, i=0, shared_int = TRUE;
902+ uint32_t irq = adapter->pdev->irq;
781903
782904 *data = 0;
783905
906+ /* NOTE: we don't test MSI interrupts here, yet */
784907 /* Hook up test interrupt handler just for this test */
785- if(!request_irq(irq, &e1000_test_intr, 0, netdev->name, netdev)) {
786- shared_int = FALSE;
787- } else if(request_irq(irq, &e1000_test_intr, SA_SHIRQ,
788- netdev->name, netdev)){
908+ if (!request_irq(irq, &e1000_test_intr, IRQF_PROBE_SHARED, netdev->name,
909+ netdev))
910+ shared_int = FALSE;
911+ else if (request_irq(irq, &e1000_test_intr, IRQF_SHARED,
912+ netdev->name, netdev)) {
789913 *data = 1;
790914 return -1;
791915 }
916+ DPRINTK(HW, INFO, "testing %s interrupt\n",
917+ (shared_int ? "shared" : "unshared"));
792918
793919 /* Disable all the interrupts */
794920 E1000_WRITE_REG(&adapter->hw, IMC, 0xFFFFFFFF);
795- msec_delay(10);
921+ msleep(10);
796922
797923 /* Test each interrupt */
798- for(; i < 10; i++) {
924+ for (; i < 10; i++) {
925+
926+ if (adapter->hw.mac_type == e1000_ich8lan && i == 8)
927+ continue;
799928
800929 /* Interrupt to test */
801930 mask = 1 << i;
802931
803- if(!shared_int) {
804- /* Disable the interrupt to be reported in
805- * the cause register and then force the same
806- * interrupt and see if one gets posted. If
807- * an interrupt was posted to the bus, the
808- * test failed.
809- */
810- adapter->test_icr = 0;
811- E1000_WRITE_REG(&adapter->hw, IMC, mask);
812- E1000_WRITE_REG(&adapter->hw, ICS, mask);
813- msec_delay(10);
814-
815- if(adapter->test_icr & mask) {
816- *data = 3;
817- break;
818- }
932+ if (!shared_int) {
933+ /* Disable the interrupt to be reported in
934+ * the cause register and then force the same
935+ * interrupt and see if one gets posted. If
936+ * an interrupt was posted to the bus, the
937+ * test failed.
938+ */
939+ adapter->test_icr = 0;
940+ E1000_WRITE_REG(&adapter->hw, IMC, mask);
941+ E1000_WRITE_REG(&adapter->hw, ICS, mask);
942+ msleep(10);
943+
944+ if (adapter->test_icr & mask) {
945+ *data = 3;
946+ break;
947+ }
819948 }
820949
821950 /* Enable the interrupt to be reported in
@@ -827,14 +956,14 @@ e1000_intr_test(struct e1000_adapter *adapter, uint64_t *data)
827956 adapter->test_icr = 0;
828957 E1000_WRITE_REG(&adapter->hw, IMS, mask);
829958 E1000_WRITE_REG(&adapter->hw, ICS, mask);
830- msec_delay(10);
959+ msleep(10);
831960
832- if(!(adapter->test_icr & mask)) {
961+ if (!(adapter->test_icr & mask)) {
833962 *data = 4;
834963 break;
835964 }
836965
837- if(!shared_int) {
966+ if (!shared_int) {
838967 /* Disable the other interrupts to be reported in
839968 * the cause register and then force the other
840969 * interrupts and see if any get posted. If
@@ -842,13 +971,11 @@ e1000_intr_test(struct e1000_adapter *adapter, uint64_t *data)
842971 * test failed.
843972 */
844973 adapter->test_icr = 0;
845- E1000_WRITE_REG(&adapter->hw, IMC,
846- (~mask & 0x00007FFF));
847- E1000_WRITE_REG(&adapter->hw, ICS,
848- (~mask & 0x00007FFF));
849- msec_delay(10);
974+ E1000_WRITE_REG(&adapter->hw, IMC, ~mask & 0x00007FFF);
975+ E1000_WRITE_REG(&adapter->hw, ICS, ~mask & 0x00007FFF);
976+ msleep(10);
850977
851- if(adapter->test_icr) {
978+ if (adapter->test_icr) {
852979 *data = 5;
853980 break;
854981 }
@@ -857,7 +984,7 @@ e1000_intr_test(struct e1000_adapter *adapter, uint64_t *data)
857984
858985 /* Disable all the interrupts */
859986 E1000_WRITE_REG(&adapter->hw, IMC, 0xFFFFFFFF);
860- msec_delay(10);
987+ msleep(10);
861988
862989 /* Unhook test interrupt handler */
863990 free_irq(irq, netdev);
@@ -868,42 +995,46 @@ e1000_intr_test(struct e1000_adapter *adapter, uint64_t *data)
868995 static void
869996 e1000_free_desc_rings(struct e1000_adapter *adapter)
870997 {
871- struct e1000_desc_ring *txdr = &adapter->test_tx_ring;
872- struct e1000_desc_ring *rxdr = &adapter->test_rx_ring;
998+ struct e1000_tx_ring *txdr = &adapter->test_tx_ring;
999+ struct e1000_rx_ring *rxdr = &adapter->test_rx_ring;
8731000 struct pci_dev *pdev = adapter->pdev;
8741001 int i;
8751002
876- if(txdr->desc && txdr->buffer_info) {
877- for(i = 0; i < txdr->count; i++) {
878- if(txdr->buffer_info[i].dma)
1003+ if (txdr->desc && txdr->buffer_info) {
1004+ for (i = 0; i < txdr->count; i++) {
1005+ if (txdr->buffer_info[i].dma)
8791006 pci_unmap_single(pdev, txdr->buffer_info[i].dma,
8801007 txdr->buffer_info[i].length,
8811008 PCI_DMA_TODEVICE);
882- if(txdr->buffer_info[i].skb)
1009+ if (txdr->buffer_info[i].skb)
8831010 dev_kfree_skb(txdr->buffer_info[i].skb);
8841011 }
8851012 }
8861013
887- if(rxdr->desc && rxdr->buffer_info) {
888- for(i = 0; i < rxdr->count; i++) {
889- if(rxdr->buffer_info[i].dma)
1014+ if (rxdr->desc && rxdr->buffer_info) {
1015+ for (i = 0; i < rxdr->count; i++) {
1016+ if (rxdr->buffer_info[i].dma)
8901017 pci_unmap_single(pdev, rxdr->buffer_info[i].dma,
8911018 rxdr->buffer_info[i].length,
8921019 PCI_DMA_FROMDEVICE);
893- if(rxdr->buffer_info[i].skb)
1020+ if (rxdr->buffer_info[i].skb)
8941021 dev_kfree_skb(rxdr->buffer_info[i].skb);
8951022 }
8961023 }
8971024
898- if(txdr->desc)
1025+ if (txdr->desc) {
8991026 pci_free_consistent(pdev, txdr->size, txdr->desc, txdr->dma);
900- if(rxdr->desc)
1027+ txdr->desc = NULL;
1028+ }
1029+ if (rxdr->desc) {
9011030 pci_free_consistent(pdev, rxdr->size, rxdr->desc, rxdr->dma);
1031+ rxdr->desc = NULL;
1032+ }
9021033
903- if(txdr->buffer_info)
904- kfree(txdr->buffer_info);
905- if(rxdr->buffer_info)
906- kfree(rxdr->buffer_info);
1034+ kfree(txdr->buffer_info);
1035+ txdr->buffer_info = NULL;
1036+ kfree(rxdr->buffer_info);
1037+ rxdr->buffer_info = NULL;
9071038
9081039 return;
9091040 }
@@ -911,18 +1042,19 @@ e1000_free_desc_rings(struct e1000_adapter *adapter)
9111042 static int
9121043 e1000_setup_desc_rings(struct e1000_adapter *adapter)
9131044 {
914- struct e1000_desc_ring *txdr = &adapter->test_tx_ring;
915- struct e1000_desc_ring *rxdr = &adapter->test_rx_ring;
1045+ struct e1000_tx_ring *txdr = &adapter->test_tx_ring;
1046+ struct e1000_rx_ring *rxdr = &adapter->test_rx_ring;
9161047 struct pci_dev *pdev = adapter->pdev;
9171048 uint32_t rctl;
9181049 int size, i, ret_val;
9191050
9201051 /* Setup Tx descriptor ring and Tx buffers */
9211052
922- txdr->count = 80;
1053+ if (!txdr->count)
1054+ txdr->count = E1000_DEFAULT_TXD;
9231055
9241056 size = txdr->count * sizeof(struct e1000_buffer);
925- if(!(txdr->buffer_info = kmalloc(size, GFP_KERNEL))) {
1057+ if (!(txdr->buffer_info = kmalloc(size, GFP_KERNEL))) {
9261058 ret_val = 1;
9271059 goto err_nomem;
9281060 }
@@ -930,7 +1062,7 @@ e1000_setup_desc_rings(struct e1000_adapter *adapter)
9301062
9311063 txdr->size = txdr->count * sizeof(struct e1000_tx_desc);
9321064 E1000_ROUNDUP(txdr->size, 4096);
933- if(!(txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma))) {
1065+ if (!(txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma))) {
9341066 ret_val = 2;
9351067 goto err_nomem;
9361068 }
@@ -949,12 +1081,12 @@ e1000_setup_desc_rings(struct e1000_adapter *adapter)
9491081 E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT |
9501082 E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT);
9511083
952- for(i = 0; i < txdr->count; i++) {
1084+ for (i = 0; i < txdr->count; i++) {
9531085 struct e1000_tx_desc *tx_desc = E1000_TX_DESC(*txdr, i);
9541086 struct sk_buff *skb;
9551087 unsigned int size = 1024;
9561088
957- if(!(skb = alloc_skb(size, GFP_KERNEL))) {
1089+ if (!(skb = alloc_skb(size, GFP_KERNEL))) {
9581090 ret_val = 3;
9591091 goto err_nomem;
9601092 }
@@ -974,17 +1106,18 @@ e1000_setup_desc_rings(struct e1000_adapter *adapter)
9741106
9751107 /* Setup Rx descriptor ring and Rx buffers */
9761108
977- rxdr->count = 80;
1109+ if (!rxdr->count)
1110+ rxdr->count = E1000_DEFAULT_RXD;
9781111
9791112 size = rxdr->count * sizeof(struct e1000_buffer);
980- if(!(rxdr->buffer_info = kmalloc(size, GFP_KERNEL))) {
1113+ if (!(rxdr->buffer_info = kmalloc(size, GFP_KERNEL))) {
9811114 ret_val = 4;
9821115 goto err_nomem;
9831116 }
9841117 memset(rxdr->buffer_info, 0, size);
9851118
9861119 rxdr->size = rxdr->count * sizeof(struct e1000_rx_desc);
987- if(!(rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma))) {
1120+ if (!(rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma))) {
9881121 ret_val = 5;
9891122 goto err_nomem;
9901123 }
@@ -1004,15 +1137,16 @@ e1000_setup_desc_rings(struct e1000_adapter *adapter)
10041137 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
10051138 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
10061139
1007- for(i = 0; i < rxdr->count; i++) {
1140+ for (i = 0; i < rxdr->count; i++) {
10081141 struct e1000_rx_desc *rx_desc = E1000_RX_DESC(*rxdr, i);
10091142 struct sk_buff *skb;
10101143
1011- if(!(skb = alloc_skb(E1000_RXBUFFER_2048 + 2, GFP_KERNEL))) {
1144+ if (!(skb = alloc_skb(E1000_RXBUFFER_2048 + NET_IP_ALIGN,
1145+ GFP_KERNEL))) {
10121146 ret_val = 6;
10131147 goto err_nomem;
10141148 }
1015- skb_reserve(skb, 2);
1149+ skb_reserve(skb, NET_IP_ALIGN);
10161150 rxdr->buffer_info[i].skb = skb;
10171151 rxdr->buffer_info[i].length = E1000_RXBUFFER_2048;
10181152 rxdr->buffer_info[i].dma =
@@ -1116,15 +1250,15 @@ e1000_nonintegrated_phy_loopback(struct e1000_adapter *adapter)
11161250
11171251 /* Check Phy Configuration */
11181252 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_reg);
1119- if(phy_reg != 0x4100)
1253+ if (phy_reg != 0x4100)
11201254 return 9;
11211255
11221256 e1000_read_phy_reg(&adapter->hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_reg);
1123- if(phy_reg != 0x0070)
1257+ if (phy_reg != 0x0070)
11241258 return 10;
11251259
11261260 e1000_read_phy_reg(&adapter->hw, 29, &phy_reg);
1127- if(phy_reg != 0x001A)
1261+ if (phy_reg != 0x001A)
11281262 return 11;
11291263
11301264 return 0;
@@ -1138,7 +1272,7 @@ e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
11381272
11391273 adapter->hw.autoneg = FALSE;
11401274
1141- if(adapter->hw.phy_type == e1000_phy_m88) {
1275+ if (adapter->hw.phy_type == e1000_phy_m88) {
11421276 /* Auto-MDI/MDIX Off */
11431277 e1000_write_phy_reg(&adapter->hw,
11441278 M88E1000_PHY_SPEC_CTRL, 0x0808);
@@ -1146,26 +1280,44 @@ e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
11461280 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x9140);
11471281 /* autoneg off */
11481282 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x8140);
1149- }
1150- /* force 1000, set loopback */
1151- e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x4140);
1283+ } else if (adapter->hw.phy_type == e1000_phy_gg82563)
1284+ e1000_write_phy_reg(&adapter->hw,
1285+ GG82563_PHY_KMRN_MODE_CTRL,
1286+ 0x1CC);
11521287
1153- /* Now set up the MAC to the same speed/duplex as the PHY. */
11541288 ctrl_reg = E1000_READ_REG(&adapter->hw, CTRL);
1155- ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1156- ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1157- E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1158- E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1159- E1000_CTRL_FD); /* Force Duplex to FULL */
1160-
1161- if(adapter->hw.media_type == e1000_media_type_copper &&
1162- adapter->hw.phy_type == e1000_phy_m88) {
1163- ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1289+
1290+ if (adapter->hw.phy_type == e1000_phy_ife) {
1291+ /* force 100, set loopback */
1292+ e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x6100);
1293+
1294+ /* Now set up the MAC to the same speed/duplex as the PHY. */
1295+ ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1296+ ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1297+ E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1298+ E1000_CTRL_SPD_100 |/* Force Speed to 100 */
1299+ E1000_CTRL_FD); /* Force Duplex to FULL */
11641300 } else {
1301+ /* force 1000, set loopback */
1302+ e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x4140);
1303+
1304+ /* Now set up the MAC to the same speed/duplex as the PHY. */
1305+ ctrl_reg = E1000_READ_REG(&adapter->hw, CTRL);
1306+ ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1307+ ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1308+ E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1309+ E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1310+ E1000_CTRL_FD); /* Force Duplex to FULL */
1311+ }
1312+
1313+ if (adapter->hw.media_type == e1000_media_type_copper &&
1314+ adapter->hw.phy_type == e1000_phy_m88)
1315+ ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1316+ else {
11651317 /* Set the ILOS bit on the fiber Nic is half
11661318 * duplex link is detected. */
11671319 stat_reg = E1000_READ_REG(&adapter->hw, STATUS);
1168- if((stat_reg & E1000_STATUS_FD) == 0)
1320+ if ((stat_reg & E1000_STATUS_FD) == 0)
11691321 ctrl_reg |= (E1000_CTRL_ILOS | E1000_CTRL_SLU);
11701322 }
11711323
@@ -1174,7 +1326,7 @@ e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
11741326 /* Disable the receiver on the PHY so when a cable is plugged in, the
11751327 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
11761328 */
1177- if(adapter->hw.phy_type == e1000_phy_m88)
1329+ if (adapter->hw.phy_type == e1000_phy_m88)
11781330 e1000_phy_disable_receiver(adapter);
11791331
11801332 udelay(500);
@@ -1190,14 +1342,14 @@ e1000_set_phy_loopback(struct e1000_adapter *adapter)
11901342
11911343 switch (adapter->hw.mac_type) {
11921344 case e1000_82543:
1193- if(adapter->hw.media_type == e1000_media_type_copper) {
1345+ if (adapter->hw.media_type == e1000_media_type_copper) {
11941346 /* Attempt to setup Loopback mode on Non-integrated PHY.
11951347 * Some PHY registers get corrupted at random, so
11961348 * attempt this 10 times.
11971349 */
1198- while(e1000_nonintegrated_phy_loopback(adapter) &&
1350+ while (e1000_nonintegrated_phy_loopback(adapter) &&
11991351 count++ < 10);
1200- if(count < 11)
1352+ if (count < 11)
12011353 return 0;
12021354 }
12031355 break;
@@ -1212,6 +1364,11 @@ e1000_set_phy_loopback(struct e1000_adapter *adapter)
12121364 case e1000_82541_rev_2:
12131365 case e1000_82547:
12141366 case e1000_82547_rev_2:
1367+ case e1000_82571:
1368+ case e1000_82572:
1369+ case e1000_82573:
1370+ case e1000_80003es2lan:
1371+ case e1000_ich8lan:
12151372 return e1000_integrated_phy_loopback(adapter);
12161373 break;
12171374
@@ -1232,22 +1389,33 @@ e1000_set_phy_loopback(struct e1000_adapter *adapter)
12321389 static int
12331390 e1000_setup_loopback_test(struct e1000_adapter *adapter)
12341391 {
1392+ struct e1000_hw *hw = &adapter->hw;
12351393 uint32_t rctl;
12361394
1237- if(adapter->hw.media_type == e1000_media_type_fiber ||
1238- adapter->hw.media_type == e1000_media_type_internal_serdes) {
1239- if(adapter->hw.mac_type == e1000_82545 ||
1240- adapter->hw.mac_type == e1000_82546 ||
1241- adapter->hw.mac_type == e1000_82545_rev_3 ||
1242- adapter->hw.mac_type == e1000_82546_rev_3)
1395+ if (hw->media_type == e1000_media_type_fiber ||
1396+ hw->media_type == e1000_media_type_internal_serdes) {
1397+ switch (hw->mac_type) {
1398+ case e1000_82545:
1399+ case e1000_82546:
1400+ case e1000_82545_rev_3:
1401+ case e1000_82546_rev_3:
12431402 return e1000_set_phy_loopback(adapter);
1244- else {
1245- rctl = E1000_READ_REG(&adapter->hw, RCTL);
1403+ break;
1404+ case e1000_82571:
1405+ case e1000_82572:
1406+#define E1000_SERDES_LB_ON 0x410
1407+ e1000_set_phy_loopback(adapter);
1408+ E1000_WRITE_REG(hw, SCTL, E1000_SERDES_LB_ON);
1409+ msleep(10);
1410+ return 0;
1411+ break;
1412+ default:
1413+ rctl = E1000_READ_REG(hw, RCTL);
12461414 rctl |= E1000_RCTL_LBM_TCVR;
1247- E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1415+ E1000_WRITE_REG(hw, RCTL, rctl);
12481416 return 0;
12491417 }
1250- } else if(adapter->hw.media_type == e1000_media_type_copper)
1418+ } else if (hw->media_type == e1000_media_type_copper)
12511419 return e1000_set_phy_loopback(adapter);
12521420
12531421 return 7;
@@ -1256,27 +1424,42 @@ e1000_setup_loopback_test(struct e1000_adapter *adapter)
12561424 static void
12571425 e1000_loopback_cleanup(struct e1000_adapter *adapter)
12581426 {
1427+ struct e1000_hw *hw = &adapter->hw;
12591428 uint32_t rctl;
12601429 uint16_t phy_reg;
12611430
1262- rctl = E1000_READ_REG(&adapter->hw, RCTL);
1431+ rctl = E1000_READ_REG(hw, RCTL);
12631432 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1264- E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1265-
1266- if(adapter->hw.media_type == e1000_media_type_copper ||
1267- ((adapter->hw.media_type == e1000_media_type_fiber ||
1268- adapter->hw.media_type == e1000_media_type_internal_serdes) &&
1269- (adapter->hw.mac_type == e1000_82545 ||
1270- adapter->hw.mac_type == e1000_82546 ||
1271- adapter->hw.mac_type == e1000_82545_rev_3 ||
1272- adapter->hw.mac_type == e1000_82546_rev_3))) {
1273- adapter->hw.autoneg = TRUE;
1274- e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_reg);
1275- if(phy_reg & MII_CR_LOOPBACK) {
1433+ E1000_WRITE_REG(hw, RCTL, rctl);
1434+
1435+ switch (hw->mac_type) {
1436+ case e1000_82571:
1437+ case e1000_82572:
1438+ if (hw->media_type == e1000_media_type_fiber ||
1439+ hw->media_type == e1000_media_type_internal_serdes) {
1440+#define E1000_SERDES_LB_OFF 0x400
1441+ E1000_WRITE_REG(hw, SCTL, E1000_SERDES_LB_OFF);
1442+ msleep(10);
1443+ break;
1444+ }
1445+ /* Fall Through */
1446+ case e1000_82545:
1447+ case e1000_82546:
1448+ case e1000_82545_rev_3:
1449+ case e1000_82546_rev_3:
1450+ default:
1451+ hw->autoneg = TRUE;
1452+ if (hw->phy_type == e1000_phy_gg82563)
1453+ e1000_write_phy_reg(hw,
1454+ GG82563_PHY_KMRN_MODE_CTRL,
1455+ 0x180);
1456+ e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg);
1457+ if (phy_reg & MII_CR_LOOPBACK) {
12761458 phy_reg &= ~MII_CR_LOOPBACK;
1277- e1000_write_phy_reg(&adapter->hw, PHY_CTRL, phy_reg);
1278- e1000_phy_reset(&adapter->hw);
1459+ e1000_write_phy_reg(hw, PHY_CTRL, phy_reg);
1460+ e1000_phy_reset(hw);
12791461 }
1462+ break;
12801463 }
12811464 }
12821465
@@ -1284,7 +1467,7 @@ static void
12841467 e1000_create_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
12851468 {
12861469 memset(skb->data, 0xFF, frame_size);
1287- frame_size = (frame_size % 2) ? (frame_size - 1) : frame_size;
1470+ frame_size &= ~1;
12881471 memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
12891472 memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
12901473 memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
@@ -1293,9 +1476,9 @@ e1000_create_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
12931476 static int
12941477 e1000_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
12951478 {
1296- frame_size = (frame_size % 2) ? (frame_size - 1) : frame_size;
1297- if(*(skb->data + 3) == 0xFF) {
1298- if((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1479+ frame_size &= ~1;
1480+ if (*(skb->data + 3) == 0xFF) {
1481+ if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
12991482 (*(skb->data + frame_size / 2 + 12) == 0xAF)) {
13001483 return 0;
13011484 }
@@ -1306,46 +1489,90 @@ e1000_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
13061489 static int
13071490 e1000_run_loopback_test(struct e1000_adapter *adapter)
13081491 {
1309- struct e1000_desc_ring *txdr = &adapter->test_tx_ring;
1310- struct e1000_desc_ring *rxdr = &adapter->test_rx_ring;
1492+ struct e1000_tx_ring *txdr = &adapter->test_tx_ring;
1493+ struct e1000_rx_ring *rxdr = &adapter->test_rx_ring;
13111494 struct pci_dev *pdev = adapter->pdev;
1312- int i, ret_val;
1495+ int i, j, k, l, lc, good_cnt, ret_val=0;
1496+ unsigned long time;
13131497
13141498 E1000_WRITE_REG(&adapter->hw, RDT, rxdr->count - 1);
13151499
1316- for(i = 0; i < 64; i++) {
1317- e1000_create_lbtest_frame(txdr->buffer_info[i].skb, 1024);
1318- pci_dma_sync_single(pdev, txdr->buffer_info[i].dma,
1319- txdr->buffer_info[i].length,
1320- PCI_DMA_TODEVICE);
1321- }
1322- E1000_WRITE_REG(&adapter->hw, TDT, i);
1323-
1324- msec_delay(200);
1325-
1326- i = 0;
1327- do {
1328- pci_dma_sync_single(pdev, rxdr->buffer_info[i].dma,
1329- rxdr->buffer_info[i].length,
1330- PCI_DMA_FROMDEVICE);
1331-
1332- ret_val = e1000_check_lbtest_frame(rxdr->buffer_info[i].skb,
1333- 1024);
1334- i++;
1335- } while (ret_val != 0 && i < 64);
1500+ /* Calculate the loop count based on the largest descriptor ring
1501+ * The idea is to wrap the largest ring a number of times using 64
1502+ * send/receive pairs during each loop
1503+ */
13361504
1505+ if (rxdr->count <= txdr->count)
1506+ lc = ((txdr->count / 64) * 2) + 1;
1507+ else
1508+ lc = ((rxdr->count / 64) * 2) + 1;
1509+
1510+ k = l = 0;
1511+ for (j = 0; j <= lc; j++) { /* loop count loop */
1512+ for (i = 0; i < 64; i++) { /* send the packets */
1513+ e1000_create_lbtest_frame(txdr->buffer_info[i].skb,
1514+ 1024);
1515+ pci_dma_sync_single_for_device(pdev,
1516+ txdr->buffer_info[k].dma,
1517+ txdr->buffer_info[k].length,
1518+ PCI_DMA_TODEVICE);
1519+ if (unlikely(++k == txdr->count)) k = 0;
1520+ }
1521+ E1000_WRITE_REG(&adapter->hw, TDT, k);
1522+ msleep(200);
1523+ time = jiffies; /* set the start time for the receive */
1524+ good_cnt = 0;
1525+ do { /* receive the sent packets */
1526+ pci_dma_sync_single_for_cpu(pdev,
1527+ rxdr->buffer_info[l].dma,
1528+ rxdr->buffer_info[l].length,
1529+ PCI_DMA_FROMDEVICE);
1530+
1531+ ret_val = e1000_check_lbtest_frame(
1532+ rxdr->buffer_info[l].skb,
1533+ 1024);
1534+ if (!ret_val)
1535+ good_cnt++;
1536+ if (unlikely(++l == rxdr->count)) l = 0;
1537+ /* time + 20 msecs (200 msecs on 2.4) is more than
1538+ * enough time to complete the receives, if it's
1539+ * exceeded, break and error off
1540+ */
1541+ } while (good_cnt < 64 && jiffies < (time + 20));
1542+ if (good_cnt != 64) {
1543+ ret_val = 13; /* ret_val is the same as mis-compare */
1544+ break;
1545+ }
1546+ if (jiffies >= (time + 2)) {
1547+ ret_val = 14; /* error code for time out error */
1548+ break;
1549+ }
1550+ } /* end loop count loop */
13371551 return ret_val;
13381552 }
13391553
13401554 static int
13411555 e1000_loopback_test(struct e1000_adapter *adapter, uint64_t *data)
13421556 {
1343- if((*data = e1000_setup_desc_rings(adapter))) goto err_loopback;
1344- if((*data = e1000_setup_loopback_test(adapter))) goto err_loopback;
1557+ /* PHY loopback cannot be performed if SoL/IDER
1558+ * sessions are active */
1559+ if (e1000_check_phy_reset_block(&adapter->hw)) {
1560+ DPRINTK(DRV, ERR, "Cannot do PHY loopback test "
1561+ "when SoL/IDER is active.\n");
1562+ *data = 0;
1563+ goto out;
1564+ }
1565+
1566+ if ((*data = e1000_setup_desc_rings(adapter)))
1567+ goto out;
1568+ if ((*data = e1000_setup_loopback_test(adapter)))
1569+ goto err_loopback;
13451570 *data = e1000_run_loopback_test(adapter);
13461571 e1000_loopback_cleanup(adapter);
1347- e1000_free_desc_rings(adapter);
1572+
13481573 err_loopback:
1574+ e1000_free_desc_rings(adapter);
1575+out:
13491576 return *data;
13501577 }
13511578
@@ -1353,45 +1580,49 @@ static int
13531580 e1000_link_test(struct e1000_adapter *adapter, uint64_t *data)
13541581 {
13551582 *data = 0;
1356-
13571583 if (adapter->hw.media_type == e1000_media_type_internal_serdes) {
13581584 int i = 0;
13591585 adapter->hw.serdes_link_down = TRUE;
13601586
1361- /* on some blade server designs link establishment */
1362- /* could take as long as 2-3 minutes. */
1587+ /* On some blade server designs, link establishment
1588+ * could take as long as 2-3 minutes */
13631589 do {
13641590 e1000_check_for_link(&adapter->hw);
13651591 if (adapter->hw.serdes_link_down == FALSE)
13661592 return *data;
1367- msec_delay(20);
1593+ msleep(20);
13681594 } while (i++ < 3750);
13691595
1370- *data = 1;
1596+ *data = 1;
13711597 } else {
13721598 e1000_check_for_link(&adapter->hw);
1599+ if (adapter->hw.autoneg) /* if auto_neg is set wait for it */
1600+ msleep(4000);
13731601
1374- if(!(E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU)) {
1602+ if (!(E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU)) {
13751603 *data = 1;
13761604 }
13771605 }
13781606 return *data;
13791607 }
13801608
1381-static int
1609+static int
13821610 e1000_diag_test_count(struct net_device *netdev)
13831611 {
13841612 return E1000_TEST_LEN;
13851613 }
13861614
1615+extern void e1000_power_up_phy(struct e1000_adapter *);
1616+
13871617 static void
13881618 e1000_diag_test(struct net_device *netdev,
13891619 struct ethtool_test *eth_test, uint64_t *data)
13901620 {
1391- struct e1000_adapter *adapter = netdev->priv;
1621+ struct e1000_adapter *adapter = netdev_priv(netdev);
13921622 boolean_t if_running = netif_running(netdev);
13931623
1394- if(eth_test->flags == ETH_TEST_FL_OFFLINE) {
1624+ set_bit(__E1000_TESTING, &adapter->flags);
1625+ if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
13951626 /* Offline tests */
13961627
13971628 /* save speed, duplex, autoneg settings */
@@ -1399,29 +1630,34 @@ e1000_diag_test(struct net_device *netdev,
13991630 uint8_t forced_speed_duplex = adapter->hw.forced_speed_duplex;
14001631 uint8_t autoneg = adapter->hw.autoneg;
14011632
1633+ DPRINTK(HW, INFO, "offline testing starting\n");
1634+
14021635 /* Link test performed before hardware reset so autoneg doesn't
14031636 * interfere with test result */
1404- if(e1000_link_test(adapter, &data[4]))
1637+ if (e1000_link_test(adapter, &data[4]))
14051638 eth_test->flags |= ETH_TEST_FL_FAILED;
14061639
1407- if(if_running)
1408- e1000_down(adapter);
1640+ if (if_running)
1641+ /* indicate we're in test mode */
1642+ dev_close(netdev);
14091643 else
14101644 e1000_reset(adapter);
14111645
1412- if(e1000_reg_test(adapter, &data[0]))
1646+ if (e1000_reg_test(adapter, &data[0]))
14131647 eth_test->flags |= ETH_TEST_FL_FAILED;
14141648
14151649 e1000_reset(adapter);
1416- if(e1000_eeprom_test(adapter, &data[1]))
1650+ if (e1000_eeprom_test(adapter, &data[1]))
14171651 eth_test->flags |= ETH_TEST_FL_FAILED;
14181652
14191653 e1000_reset(adapter);
1420- if(e1000_intr_test(adapter, &data[2]))
1654+ if (e1000_intr_test(adapter, &data[2]))
14211655 eth_test->flags |= ETH_TEST_FL_FAILED;
14221656
14231657 e1000_reset(adapter);
1424- if(e1000_loopback_test(adapter, &data[3]))
1658+ /* make sure the phy is powered up */
1659+ e1000_power_up_phy(adapter);
1660+ if (e1000_loopback_test(adapter, &data[3]))
14251661 eth_test->flags |= ETH_TEST_FL_FAILED;
14261662
14271663 /* restore speed, duplex, autoneg settings */
@@ -1430,28 +1666,32 @@ e1000_diag_test(struct net_device *netdev,
14301666 adapter->hw.autoneg = autoneg;
14311667
14321668 e1000_reset(adapter);
1433- if(if_running)
1434- e1000_up(adapter);
1669+ clear_bit(__E1000_TESTING, &adapter->flags);
1670+ if (if_running)
1671+ dev_open(netdev);
14351672 } else {
1673+ DPRINTK(HW, INFO, "online testing starting\n");
14361674 /* Online tests */
1437- if(e1000_link_test(adapter, &data[4]))
1675+ if (e1000_link_test(adapter, &data[4]))
14381676 eth_test->flags |= ETH_TEST_FL_FAILED;
14391677
1440- /* Offline tests aren't run; pass by default */
1678+ /* Online tests aren't run; pass by default */
14411679 data[0] = 0;
14421680 data[1] = 0;
14431681 data[2] = 0;
14441682 data[3] = 0;
1683+
1684+ clear_bit(__E1000_TESTING, &adapter->flags);
14451685 }
1686+ msleep_interruptible(4 * 1000);
14461687 }
14471688
1448-static void
1449-e1000_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1689+static int e1000_wol_exclusion(struct e1000_adapter *adapter, struct ethtool_wolinfo *wol)
14501690 {
1451- struct e1000_adapter *adapter = netdev->priv;
14521691 struct e1000_hw *hw = &adapter->hw;
1692+ int retval = 1; /* fail by default */
14531693
1454- switch(adapter->hw.device_id) {
1694+ switch (hw->device_id) {
14551695 case E1000_DEV_ID_82542:
14561696 case E1000_DEV_ID_82543GC_FIBER:
14571697 case E1000_DEV_ID_82543GC_COPPER:
@@ -1459,75 +1699,126 @@ e1000_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
14591699 case E1000_DEV_ID_82546EB_QUAD_COPPER:
14601700 case E1000_DEV_ID_82545EM_FIBER:
14611701 case E1000_DEV_ID_82545EM_COPPER:
1702+ case E1000_DEV_ID_82546GB_QUAD_COPPER:
1703+ case E1000_DEV_ID_82546GB_PCIE:
1704+ /* these don't support WoL at all */
14621705 wol->supported = 0;
1463- wol->wolopts = 0;
1464- return;
1465-
1706+ break;
14661707 case E1000_DEV_ID_82546EB_FIBER:
14671708 case E1000_DEV_ID_82546GB_FIBER:
1468- /* Wake events only supported on port A for dual fiber */
1469- if(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) {
1709+ case E1000_DEV_ID_82571EB_FIBER:
1710+ case E1000_DEV_ID_82571EB_SERDES:
1711+ case E1000_DEV_ID_82571EB_COPPER:
1712+ /* Wake events not supported on port B */
1713+ if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) {
1714+ wol->supported = 0;
1715+ break;
1716+ }
1717+ /* return success for non excluded adapter ports */
1718+ retval = 0;
1719+ break;
1720+ case E1000_DEV_ID_82571EB_QUAD_COPPER:
1721+ case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
1722+ case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1723+ /* quad port adapters only support WoL on port A */
1724+ if (!adapter->quad_port_a) {
14701725 wol->supported = 0;
1471- wol->wolopts = 0;
1472- return;
1726+ break;
14731727 }
1474- /* Fall Through */
1475-
1728+ /* return success for non excluded adapter ports */
1729+ retval = 0;
1730+ break;
14761731 default:
1477- wol->supported = WAKE_UCAST | WAKE_MCAST |
1478- WAKE_BCAST | WAKE_MAGIC;
1479-
1480- wol->wolopts = 0;
1481- if(adapter->wol & E1000_WUFC_EX)
1482- wol->wolopts |= WAKE_UCAST;
1483- if(adapter->wol & E1000_WUFC_MC)
1484- wol->wolopts |= WAKE_MCAST;
1485- if(adapter->wol & E1000_WUFC_BC)
1486- wol->wolopts |= WAKE_BCAST;
1487- if(adapter->wol & E1000_WUFC_MAG)
1488- wol->wolopts |= WAKE_MAGIC;
1732+ /* dual port cards only support WoL on port A from now on
1733+ * unless it was enabled in the eeprom for port B
1734+ * so exclude FUNC_1 ports from having WoL enabled */
1735+ if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1 &&
1736+ !adapter->eeprom_wol) {
1737+ wol->supported = 0;
1738+ break;
1739+ }
1740+
1741+ retval = 0;
1742+ }
1743+
1744+ return retval;
1745+}
1746+
1747+static void
1748+e1000_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1749+{
1750+ struct e1000_adapter *adapter = netdev_priv(netdev);
1751+
1752+ wol->supported = WAKE_UCAST | WAKE_MCAST |
1753+ WAKE_BCAST | WAKE_MAGIC;
1754+ wol->wolopts = 0;
1755+
1756+ /* this function will set ->supported = 0 and return 1 if wol is not
1757+ * supported by this hardware */
1758+ if (e1000_wol_exclusion(adapter, wol))
14891759 return;
1760+
1761+ /* apply any specific unsupported masks here */
1762+ switch (adapter->hw.device_id) {
1763+ case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1764+ /* KSP3 does not suppport UCAST wake-ups */
1765+ wol->supported &= ~WAKE_UCAST;
1766+
1767+ if (adapter->wol & E1000_WUFC_EX)
1768+ DPRINTK(DRV, ERR, "Interface does not support "
1769+ "directed (unicast) frame wake-up packets\n");
1770+ break;
1771+ default:
1772+ break;
14901773 }
1774+
1775+ if (adapter->wol & E1000_WUFC_EX)
1776+ wol->wolopts |= WAKE_UCAST;
1777+ if (adapter->wol & E1000_WUFC_MC)
1778+ wol->wolopts |= WAKE_MCAST;
1779+ if (adapter->wol & E1000_WUFC_BC)
1780+ wol->wolopts |= WAKE_BCAST;
1781+ if (adapter->wol & E1000_WUFC_MAG)
1782+ wol->wolopts |= WAKE_MAGIC;
1783+
1784+ return;
14911785 }
14921786
14931787 static int
14941788 e1000_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
14951789 {
1496- struct e1000_adapter *adapter = netdev->priv;
1790+ struct e1000_adapter *adapter = netdev_priv(netdev);
14971791 struct e1000_hw *hw = &adapter->hw;
14981792
1499- switch(adapter->hw.device_id) {
1500- case E1000_DEV_ID_82542:
1501- case E1000_DEV_ID_82543GC_FIBER:
1502- case E1000_DEV_ID_82543GC_COPPER:
1503- case E1000_DEV_ID_82544EI_FIBER:
1504- case E1000_DEV_ID_82546EB_QUAD_COPPER:
1505- case E1000_DEV_ID_82545EM_FIBER:
1506- case E1000_DEV_ID_82545EM_COPPER:
1507- return wol->wolopts ? -EOPNOTSUPP : 0;
1793+ if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1794+ return -EOPNOTSUPP;
15081795
1509- case E1000_DEV_ID_82546EB_FIBER:
1510- case E1000_DEV_ID_82546GB_FIBER:
1511- /* Wake events only supported on port A for dual fiber */
1512- if(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
1513- return wol->wolopts ? -EOPNOTSUPP : 0;
1514- /* Fall Through */
1796+ if (e1000_wol_exclusion(adapter, wol))
1797+ return wol->wolopts ? -EOPNOTSUPP : 0;
15151798
1516- default:
1517- if(wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1799+ switch (hw->device_id) {
1800+ case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1801+ if (wol->wolopts & WAKE_UCAST) {
1802+ DPRINTK(DRV, ERR, "Interface does not support "
1803+ "directed (unicast) frame wake-up packets\n");
15181804 return -EOPNOTSUPP;
1805+ }
1806+ break;
1807+ default:
1808+ break;
1809+ }
15191810
1520- adapter->wol = 0;
1811+ /* these settings will always override what we currently have */
1812+ adapter->wol = 0;
15211813
1522- if(wol->wolopts & WAKE_UCAST)
1523- adapter->wol |= E1000_WUFC_EX;
1524- if(wol->wolopts & WAKE_MCAST)
1525- adapter->wol |= E1000_WUFC_MC;
1526- if(wol->wolopts & WAKE_BCAST)
1527- adapter->wol |= E1000_WUFC_BC;
1528- if(wol->wolopts & WAKE_MAGIC)
1529- adapter->wol |= E1000_WUFC_MAG;
1530- }
1814+ if (wol->wolopts & WAKE_UCAST)
1815+ adapter->wol |= E1000_WUFC_EX;
1816+ if (wol->wolopts & WAKE_MCAST)
1817+ adapter->wol |= E1000_WUFC_MC;
1818+ if (wol->wolopts & WAKE_BCAST)
1819+ adapter->wol |= E1000_WUFC_BC;
1820+ if (wol->wolopts & WAKE_MAGIC)
1821+ adapter->wol |= E1000_WUFC_MAG;
15311822
15321823 return 0;
15331824 }
@@ -1543,7 +1834,7 @@ e1000_led_blink_callback(unsigned long data)
15431834 {
15441835 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
15451836
1546- if(test_and_change_bit(E1000_LED_ON, &adapter->led_status))
1837+ if (test_and_change_bit(E1000_LED_ON, &adapter->led_status))
15471838 e1000_led_off(&adapter->hw);
15481839 else
15491840 e1000_led_on(&adapter->hw);
@@ -1554,24 +1845,36 @@ e1000_led_blink_callback(unsigned long data)
15541845 static int
15551846 e1000_phys_id(struct net_device *netdev, uint32_t data)
15561847 {
1557- struct e1000_adapter *adapter = netdev->priv;
1848+ struct e1000_adapter *adapter = netdev_priv(netdev);
15581849
1559- if(!data || data > (uint32_t)(MAX_SCHEDULE_TIMEOUT / HZ))
1850+ if (!data || data > (uint32_t)(MAX_SCHEDULE_TIMEOUT / HZ))
15601851 data = (uint32_t)(MAX_SCHEDULE_TIMEOUT / HZ);
15611852
1562- if(!adapter->blink_timer.function) {
1563- init_timer(&adapter->blink_timer);
1564- adapter->blink_timer.function = e1000_led_blink_callback;
1565- adapter->blink_timer.data = (unsigned long) adapter;
1853+ if (adapter->hw.mac_type < e1000_82571) {
1854+ if (!adapter->blink_timer.function) {
1855+ init_timer(&adapter->blink_timer);
1856+ adapter->blink_timer.function = e1000_led_blink_callback;
1857+ adapter->blink_timer.data = (unsigned long) adapter;
1858+ }
1859+ e1000_setup_led(&adapter->hw);
1860+ mod_timer(&adapter->blink_timer, jiffies);
1861+ msleep_interruptible(data * 1000);
1862+ del_timer_sync(&adapter->blink_timer);
1863+ } else if (adapter->hw.phy_type == e1000_phy_ife) {
1864+ if (!adapter->blink_timer.function) {
1865+ init_timer(&adapter->blink_timer);
1866+ adapter->blink_timer.function = e1000_led_blink_callback;
1867+ adapter->blink_timer.data = (unsigned long) adapter;
1868+ }
1869+ mod_timer(&adapter->blink_timer, jiffies);
1870+ msleep_interruptible(data * 1000);
1871+ del_timer_sync(&adapter->blink_timer);
1872+ e1000_write_phy_reg(&(adapter->hw), IFE_PHY_SPECIAL_CONTROL_LED, 0);
1873+ } else {
1874+ e1000_blink_led_start(&adapter->hw);
1875+ msleep_interruptible(data * 1000);
15661876 }
15671877
1568- e1000_setup_led(&adapter->hw);
1569- mod_timer(&adapter->blink_timer, jiffies);
1570-
1571- set_current_state(TASK_INTERRUPTIBLE);
1572-
1573- schedule_timeout(data * HZ);
1574- del_timer_sync(&adapter->blink_timer);
15751878 e1000_led_off(&adapter->hw);
15761879 clear_bit(E1000_LED_ON, &adapter->led_status);
15771880 e1000_cleanup_led(&adapter->hw);
@@ -1582,56 +1885,57 @@ e1000_phys_id(struct net_device *netdev, uint32_t data)
15821885 static int
15831886 e1000_nway_reset(struct net_device *netdev)
15841887 {
1585- struct e1000_adapter *adapter = netdev->priv;
1586- if(netif_running(netdev)) {
1587- e1000_down(adapter);
1588- e1000_up(adapter);
1589- }
1888+ struct e1000_adapter *adapter = netdev_priv(netdev);
1889+ if (netif_running(netdev))
1890+ e1000_reinit_locked(adapter);
15901891 return 0;
15911892 }
15921893
1593-static int
1894+static int
15941895 e1000_get_stats_count(struct net_device *netdev)
15951896 {
15961897 return E1000_STATS_LEN;
15971898 }
15981899
1599-static void
1600-e1000_get_ethtool_stats(struct net_device *netdev,
1900+static void
1901+e1000_get_ethtool_stats(struct net_device *netdev,
16011902 struct ethtool_stats *stats, uint64_t *data)
16021903 {
1603- struct e1000_adapter *adapter = netdev->priv;
1904+ struct e1000_adapter *adapter = netdev_priv(netdev);
16041905 int i;
16051906
16061907 e1000_update_stats(adapter);
1607- for(i = 0; i < E1000_STATS_LEN; i++) {
1608- char *p = (char *)adapter+e1000_gstrings_stats[i].stat_offset;
1609- data[i] = (e1000_gstrings_stats[i].sizeof_stat ==
1908+ for (i = 0; i < E1000_GLOBAL_STATS_LEN; i++) {
1909+ char *p = (char *)adapter+e1000_gstrings_stats[i].stat_offset;
1910+ data[i] = (e1000_gstrings_stats[i].sizeof_stat ==
16101911 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
16111912 }
1913+/* BUG_ON(i != E1000_STATS_LEN); */
16121914 }
16131915
1614-static void
1916+static void
16151917 e1000_get_strings(struct net_device *netdev, uint32_t stringset, uint8_t *data)
16161918 {
1919+ uint8_t *p = data;
16171920 int i;
16181921
1619- switch(stringset) {
1922+ switch (stringset) {
16201923 case ETH_SS_TEST:
1621- memcpy(data, *e1000_gstrings_test,
1924+ memcpy(data, *e1000_gstrings_test,
16221925 E1000_TEST_LEN*ETH_GSTRING_LEN);
16231926 break;
16241927 case ETH_SS_STATS:
1625- for (i=0; i < E1000_STATS_LEN; i++) {
1626- memcpy(data + i * ETH_GSTRING_LEN,
1627- e1000_gstrings_stats[i].stat_string,
1628- ETH_GSTRING_LEN);
1928+ for (i = 0; i < E1000_GLOBAL_STATS_LEN; i++) {
1929+ memcpy(p, e1000_gstrings_stats[i].stat_string,
1930+ ETH_GSTRING_LEN);
1931+ p += ETH_GSTRING_LEN;
16291932 }
1933+/* BUG_ON(p - data != E1000_STATS_LEN * ETH_GSTRING_LEN); */
16301934 break;
16311935 }
16321936 }
16331937
1634-struct ethtool_ops e1000_ethtool_ops = {
1938+static struct ethtool_ops e1000_ethtool_ops = {
16351939 .get_settings = e1000_get_settings,
16361940 .set_settings = e1000_set_settings,
16371941 .get_drvinfo = e1000_get_drvinfo,
@@ -1639,8 +1943,8 @@ struct ethtool_ops e1000_ethtool_ops = {
16391943 .get_regs = e1000_get_regs,
16401944 .get_wol = e1000_get_wol,
16411945 .set_wol = e1000_set_wol,
1642- .get_msglevel = e1000_get_msglevel,
1643- .set_msglevel = e1000_set_msglevel,
1946+ .get_msglevel = e1000_get_msglevel,
1947+ .set_msglevel = e1000_set_msglevel,
16441948 .nway_reset = e1000_nway_reset,
16451949 .get_link = ethtool_op_get_link,
16461950 .get_eeprom_len = e1000_get_eeprom_len,
@@ -1648,27 +1952,27 @@ struct ethtool_ops e1000_ethtool_ops = {
16481952 .set_eeprom = e1000_set_eeprom,
16491953 .get_ringparam = e1000_get_ringparam,
16501954 .set_ringparam = e1000_set_ringparam,
1651- .get_pauseparam = e1000_get_pauseparam,
1652- .set_pauseparam = e1000_set_pauseparam,
1653- .get_rx_csum = e1000_get_rx_csum,
1654- .set_rx_csum = e1000_set_rx_csum,
1655- .get_tx_csum = e1000_get_tx_csum,
1656- .set_tx_csum = e1000_set_tx_csum,
1657- .get_sg = ethtool_op_get_sg,
1658- .set_sg = ethtool_op_set_sg,
1659-#ifdef NETIF_F_TSO
1660- .get_tso = ethtool_op_get_tso,
1661- .set_tso = e1000_set_tso,
1662-#endif
1955+ .get_pauseparam = e1000_get_pauseparam,
1956+ .set_pauseparam = e1000_set_pauseparam,
1957+ .get_rx_csum = e1000_get_rx_csum,
1958+ .set_rx_csum = e1000_set_rx_csum,
1959+ .get_tx_csum = e1000_get_tx_csum,
1960+ .set_tx_csum = e1000_set_tx_csum,
1961+ .get_sg = ethtool_op_get_sg,
1962+ .set_sg = ethtool_op_set_sg,
16631963 .self_test_count = e1000_diag_test_count,
16641964 .self_test = e1000_diag_test,
16651965 .get_strings = e1000_get_strings,
16661966 .phys_id = e1000_phys_id,
16671967 .get_stats_count = e1000_get_stats_count,
16681968 .get_ethtool_stats = e1000_get_ethtool_stats,
1969+#ifdef ETHTOOL_GPERMADDR
1970+ .get_perm_addr = ethtool_op_get_perm_addr,
1971+#endif
16691972 };
16701973
1671-void set_ethtool_ops(struct net_device *netdev)
1974+void e1000_set_ethtool_ops(struct net_device *netdev)
16721975 {
16731976 SET_ETHTOOL_OPS(netdev, &e1000_ethtool_ops);
16741977 }
1978+#endif /* SIOCETHTOOL */
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -1,27 +1,27 @@
11 /*******************************************************************************
22
3-
4- Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
5-
6- This program is free software; you can redistribute it and/or modify it
7- under the terms of the GNU General Public License as published by the Free
8- Software Foundation; either version 2 of the License, or (at your option)
9- any later version.
10-
11- This program is distributed in the hope that it will be useful, but WITHOUT
12- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
3+ Intel PRO/1000 Linux driver
4+ Copyright(c) 1999 - 2006 Intel Corporation.
5+
6+ This program is free software; you can redistribute it and/or modify it
7+ under the terms and conditions of the GNU General Public License,
8+ version 2, as published by the Free Software Foundation.
9+
10+ This program is distributed in the hope it will be useful, but WITHOUT
11+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1413 more details.
15-
14+
1615 You should have received a copy of the GNU General Public License along with
17- this program; if not, write to the Free Software Foundation, Inc., 59
18- Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19-
20- The full GNU General Public License is included in this distribution in the
21- file called LICENSE.
22-
16+ this program; if not, write to the Free Software Foundation, Inc.,
17+ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18+
19+ The full GNU General Public License is included in this distribution in
20+ the file called "COPYING".
21+
2322 Contact Information:
2423 Linux NICS <linux.nics@intel.com>
24+ e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
2525 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
2626
2727 *******************************************************************************/
@@ -30,8 +30,66 @@
3030 * Shared functions for accessing and configuring the MAC
3131 */
3232
33+
34+
3335 #include "e1000_hw.h"
3436
37+static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
38+static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
39+static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data);
40+static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
41+static int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
42+static void e1000_release_software_semaphore(struct e1000_hw *hw);
43+
44+static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw);
45+static int32_t e1000_check_downshift(struct e1000_hw *hw);
46+static int32_t e1000_check_polarity(struct e1000_hw *hw, e1000_rev_polarity *polarity);
47+static void e1000_clear_vfta(struct e1000_hw *hw);
48+static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw);
49+static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up);
50+static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
51+static int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
52+static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank);
53+static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw);
54+static int32_t e1000_get_cable_length(struct e1000_hw *hw, uint16_t *min_length, uint16_t *max_length);
55+static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
56+static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw);
57+static int32_t e1000_get_software_flag(struct e1000_hw *hw);
58+static int32_t e1000_ich8_cycle_init(struct e1000_hw *hw);
59+static int32_t e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout);
60+static int32_t e1000_id_led_init(struct e1000_hw *hw);
61+static int32_t e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size);
62+static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw);
63+static void e1000_init_rx_addrs(struct e1000_hw *hw);
64+static void e1000_initialize_hardware_bits(struct e1000_hw *hw);
65+static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
66+static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
67+static int32_t e1000_mng_enable_host_if(struct e1000_hw *hw);
68+static int32_t e1000_mng_host_if_write(struct e1000_hw *hw, uint8_t *buffer, uint16_t length, uint16_t offset, uint8_t *sum);
69+static int32_t e1000_mng_write_cmd_header(struct e1000_hw* hw, struct e1000_host_mng_command_header* hdr);
70+static int32_t e1000_mng_write_commit(struct e1000_hw *hw);
71+static int32_t e1000_phy_ife_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
72+static int32_t e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
73+static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
74+static int32_t e1000_write_eeprom_eewr(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
75+static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
76+static int32_t e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
77+static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
78+static int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t *data);
79+static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte);
80+static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte);
81+static int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data);
82+static int32_t e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t *data);
83+static int32_t e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t data);
84+static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
85+static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
86+static void e1000_release_software_flag(struct e1000_hw *hw);
87+static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
88+static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active);
89+static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop);
90+static void e1000_set_pci_express_master_disable(struct e1000_hw *hw);
91+static int32_t e1000_wait_autoneg(struct e1000_hw *hw);
92+static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value);
3593 static int32_t e1000_set_phy_type(struct e1000_hw *hw);
3694 static void e1000_phy_init_script(struct e1000_hw *hw);
3795 static int32_t e1000_setup_copper_link(struct e1000_hw *hw);
@@ -63,10 +121,15 @@ static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);
63121 static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
64122 static void e1000_release_eeprom(struct e1000_hw *hw);
65123 static void e1000_standby_eeprom(struct e1000_hw *hw);
66-static int32_t e1000_id_led_init(struct e1000_hw * hw);
67124 static int32_t e1000_set_vco_speed(struct e1000_hw *hw);
68125 static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw);
69126 static int32_t e1000_set_phy_mode(struct e1000_hw *hw);
127+static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer);
128+static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length);
129+static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw,
130+ uint16_t duplex);
131+static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
132+static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
70133
71134 /* IGP cable length table */
72135 static const
@@ -80,31 +143,58 @@ uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
80143 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
81144 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
82145
146+static const
147+uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
148+ { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
149+ 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
150+ 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
151+ 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
152+ 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
153+ 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
154+ 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
155+ 104, 109, 114, 118, 121, 124};
83156
84157 /******************************************************************************
85158 * Set the phy type member in the hw struct.
86159 *
87160 * hw - Struct containing variables accessed by shared code
88161 *****************************************************************************/
89-int32_t
162+static int32_t
90163 e1000_set_phy_type(struct e1000_hw *hw)
91164 {
92165 DEBUGFUNC("e1000_set_phy_type");
93166
94- switch(hw->phy_id) {
167+ if (hw->mac_type == e1000_undefined)
168+ return -E1000_ERR_PHY_TYPE;
169+
170+ switch (hw->phy_id) {
95171 case M88E1000_E_PHY_ID:
96172 case M88E1000_I_PHY_ID:
97173 case M88E1011_I_PHY_ID:
174+ case M88E1111_I_PHY_ID:
98175 hw->phy_type = e1000_phy_m88;
99176 break;
100177 case IGP01E1000_I_PHY_ID:
101- if(hw->mac_type == e1000_82541 ||
102- hw->mac_type == e1000_82541_rev_2 ||
103- hw->mac_type == e1000_82547 ||
104- hw->mac_type == e1000_82547_rev_2) {
178+ if (hw->mac_type == e1000_82541 ||
179+ hw->mac_type == e1000_82541_rev_2 ||
180+ hw->mac_type == e1000_82547 ||
181+ hw->mac_type == e1000_82547_rev_2) {
105182 hw->phy_type = e1000_phy_igp;
106183 break;
107184 }
185+ case IGP03E1000_E_PHY_ID:
186+ hw->phy_type = e1000_phy_igp_3;
187+ break;
188+ case IFE_E_PHY_ID:
189+ case IFE_PLUS_E_PHY_ID:
190+ case IFE_C_E_PHY_ID:
191+ hw->phy_type = e1000_phy_ife;
192+ break;
193+ case GG82563_E_PHY_ID:
194+ if (hw->mac_type == e1000_80003es2lan) {
195+ hw->phy_type = e1000_phy_gg82563;
196+ break;
197+ }
108198 /* Fall Through */
109199 default:
110200 /* Should never have loaded on this device */
@@ -128,8 +218,7 @@ e1000_phy_init_script(struct e1000_hw *hw)
128218
129219 DEBUGFUNC("e1000_phy_init_script");
130220
131-
132- if(hw->phy_init_script) {
221+ if (hw->phy_init_script) {
133222 msec_delay(20);
134223
135224 /* Save off the current value of register 0x2F5B to be restored at
@@ -145,7 +234,7 @@ e1000_phy_init_script(struct e1000_hw *hw)
145234
146235 msec_delay(5);
147236
148- switch(hw->mac_type) {
237+ switch (hw->mac_type) {
149238 case e1000_82541:
150239 case e1000_82547:
151240 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
@@ -182,22 +271,22 @@ e1000_phy_init_script(struct e1000_hw *hw)
182271 /* Now enable the transmitter */
183272 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
184273
185- if(hw->mac_type == e1000_82547) {
274+ if (hw->mac_type == e1000_82547) {
186275 uint16_t fused, fine, coarse;
187276
188277 /* Move to analog registers page */
189278 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
190279
191- if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
280+ if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
192281 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
193282
194283 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
195284 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
196285
197- if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
286+ if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
198287 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
199288 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
200- } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
289+ } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
201290 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
202291
203292 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
@@ -271,10 +360,13 @@ e1000_set_mac_type(struct e1000_hw *hw)
271360 case E1000_DEV_ID_82546GB_FIBER:
272361 case E1000_DEV_ID_82546GB_SERDES:
273362 case E1000_DEV_ID_82546GB_PCIE:
363+ case E1000_DEV_ID_82546GB_QUAD_COPPER:
364+ case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
274365 hw->mac_type = e1000_82546_rev_3;
275366 break;
276367 case E1000_DEV_ID_82541EI:
277368 case E1000_DEV_ID_82541EI_MOBILE:
369+ case E1000_DEV_ID_82541ER_LOM:
278370 hw->mac_type = e1000_82541;
279371 break;
280372 case E1000_DEV_ID_82541ER:
@@ -284,17 +376,66 @@ e1000_set_mac_type(struct e1000_hw *hw)
284376 hw->mac_type = e1000_82541_rev_2;
285377 break;
286378 case E1000_DEV_ID_82547EI:
379+ case E1000_DEV_ID_82547EI_MOBILE:
287380 hw->mac_type = e1000_82547;
288381 break;
289382 case E1000_DEV_ID_82547GI:
290383 hw->mac_type = e1000_82547_rev_2;
291384 break;
385+ case E1000_DEV_ID_82571EB_COPPER:
386+ case E1000_DEV_ID_82571EB_FIBER:
387+ case E1000_DEV_ID_82571EB_SERDES:
388+ case E1000_DEV_ID_82571EB_QUAD_COPPER:
389+ case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
390+ hw->mac_type = e1000_82571;
391+ break;
392+ case E1000_DEV_ID_82572EI_COPPER:
393+ case E1000_DEV_ID_82572EI_FIBER:
394+ case E1000_DEV_ID_82572EI_SERDES:
395+ case E1000_DEV_ID_82572EI:
396+ hw->mac_type = e1000_82572;
397+ break;
398+ case E1000_DEV_ID_82573E:
399+ case E1000_DEV_ID_82573E_IAMT:
400+ case E1000_DEV_ID_82573L:
401+ hw->mac_type = e1000_82573;
402+ break;
403+ case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
404+ case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
405+ case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
406+ case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
407+ hw->mac_type = e1000_80003es2lan;
408+ break;
409+ case E1000_DEV_ID_ICH8_IGP_M_AMT:
410+ case E1000_DEV_ID_ICH8_IGP_AMT:
411+ case E1000_DEV_ID_ICH8_IGP_C:
412+ case E1000_DEV_ID_ICH8_IFE:
413+ case E1000_DEV_ID_ICH8_IFE_GT:
414+ case E1000_DEV_ID_ICH8_IFE_G:
415+ case E1000_DEV_ID_ICH8_IGP_M:
416+ hw->mac_type = e1000_ich8lan;
417+ hw->is_ich = TRUE;
418+ break;
419+
420+
292421 default:
293422 /* Should never have loaded on this device */
294423 return -E1000_ERR_MAC_TYPE;
295424 }
296425
297- switch(hw->mac_type) {
426+ switch (hw->mac_type) {
427+ case e1000_ich8lan:
428+ hw->swfwhw_semaphore_present = TRUE;
429+ hw->asf_firmware_present = TRUE;
430+ break;
431+ case e1000_80003es2lan:
432+ hw->swfw_sync_present = TRUE;
433+ /* fall through */
434+ case e1000_82571:
435+ case e1000_82572:
436+ case e1000_82573:
437+ hw->eeprom_semaphore_present = TRUE;
438+ /* fall through */
298439 case e1000_82541:
299440 case e1000_82547:
300441 case e1000_82541_rev_2:
@@ -320,7 +461,7 @@ e1000_set_media_type(struct e1000_hw *hw)
320461
321462 DEBUGFUNC("e1000_set_media_type");
322463
323- if(hw->mac_type != e1000_82543) {
464+ if (hw->mac_type != e1000_82543) {
324465 /* tbi_compatibility is only valid on 82543 */
325466 hw->tbi_compatibility_en = FALSE;
326467 }
@@ -328,21 +469,34 @@ e1000_set_media_type(struct e1000_hw *hw)
328469 switch (hw->device_id) {
329470 case E1000_DEV_ID_82545GM_SERDES:
330471 case E1000_DEV_ID_82546GB_SERDES:
472+ case E1000_DEV_ID_82571EB_SERDES:
473+ case E1000_DEV_ID_82572EI_SERDES:
474+ case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
331475 hw->media_type = e1000_media_type_internal_serdes;
332476 break;
333477 default:
334- if(hw->mac_type >= e1000_82543) {
478+ switch (hw->mac_type) {
479+ case e1000_82542_rev2_0:
480+ case e1000_82542_rev2_1:
481+ hw->media_type = e1000_media_type_fiber;
482+ break;
483+ case e1000_ich8lan:
484+ case e1000_82573:
485+ /* The STATUS_TBIMODE bit is reserved or reused for the this
486+ * device.
487+ */
488+ hw->media_type = e1000_media_type_copper;
489+ break;
490+ default:
335491 status = E1000_READ_REG(hw, STATUS);
336- if(status & E1000_STATUS_TBIMODE) {
492+ if (status & E1000_STATUS_TBIMODE) {
337493 hw->media_type = e1000_media_type_fiber;
338494 /* tbi_compatibility not valid on fiber */
339495 hw->tbi_compatibility_en = FALSE;
340496 } else {
341497 hw->media_type = e1000_media_type_copper;
342498 }
343- } else {
344- /* This is an 82542 (fiber only) */
345- hw->media_type = e1000_media_type_fiber;
499+ break;
346500 }
347501 }
348502 }
@@ -360,15 +514,27 @@ e1000_reset_hw(struct e1000_hw *hw)
360514 uint32_t icr;
361515 uint32_t manc;
362516 uint32_t led_ctrl;
517+ uint32_t timeout;
518+ uint32_t extcnf_ctrl;
519+ int32_t ret_val;
363520
364521 DEBUGFUNC("e1000_reset_hw");
365522
366523 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
367- if(hw->mac_type == e1000_82542_rev2_0) {
524+ if (hw->mac_type == e1000_82542_rev2_0) {
368525 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
369526 e1000_pci_clear_mwi(hw);
370527 }
371528
529+ if (hw->bus_type == e1000_bus_type_pci_express) {
530+ /* Prevent the PCI-E bus from sticking if there is no TLP connection
531+ * on the last TLP read/write transaction when MAC is reset.
532+ */
533+ if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
534+ DEBUGOUT("PCI-E Master disable polling has failed.\n");
535+ }
536+ }
537+
372538 /* Clear interrupt mask to stop board from generating interrupts */
373539 DEBUGOUT("Masking off all interrupts\n");
374540 E1000_WRITE_REG(hw, IMC, 0xffffffff);
@@ -392,11 +558,42 @@ e1000_reset_hw(struct e1000_hw *hw)
392558 ctrl = E1000_READ_REG(hw, CTRL);
393559
394560 /* Must reset the PHY before resetting the MAC */
395- if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
396- E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
561+ if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
562+ E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
397563 msec_delay(5);
398564 }
399565
566+ /* Must acquire the MDIO ownership before MAC reset.
567+ * Ownership defaults to firmware after a reset. */
568+ if (hw->mac_type == e1000_82573) {
569+ timeout = 10;
570+
571+ extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
572+ extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
573+
574+ do {
575+ E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
576+ extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
577+
578+ if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
579+ break;
580+ else
581+ extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
582+
583+ msec_delay(2);
584+ timeout--;
585+ } while (timeout);
586+ }
587+
588+ /* Workaround for ICH8 bit corruption issue in FIFO memory */
589+ if (hw->mac_type == e1000_ich8lan)
590+ {
591+ /* Set Tx and Rx buffer allocation to 8k apiece. */
592+ E1000_WRITE_REG(hw, PBA, E1000_PBA_8K);
593+ /* Set Packet Buffer Size to 16k. */
594+ E1000_WRITE_REG(hw, PBS, E1000_PBS_16K);
595+ }
596+
400597 /* Issue a global reset to the MAC. This will reset the chip's
401598 * transmit, receive, DMA, and link units. It will not effect
402599 * the current PCI configuration. The global reset bit is self-
@@ -404,7 +601,7 @@ e1000_reset_hw(struct e1000_hw *hw)
404601 */
405602 DEBUGOUT("Issuing a global reset to MAC\n");
406603
407- switch(hw->mac_type) {
604+ switch (hw->mac_type) {
408605 case e1000_82544:
409606 case e1000_82540:
410607 case e1000_82545:
@@ -420,6 +617,20 @@ e1000_reset_hw(struct e1000_hw *hw)
420617 /* Reset is performed on a shadow of the control register */
421618 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
422619 break;
620+ case e1000_ich8lan:
621+ if (!hw->phy_reset_disable &&
622+ e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {
623+ /* e1000_ich8lan PHY HW reset requires MAC CORE reset
624+ * at the same time to make sure the interface between
625+ * MAC and the external PHY is reset.
626+ */
627+ ctrl |= E1000_CTRL_PHY_RST;
628+ }
629+
630+ e1000_get_software_flag(hw);
631+ E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
632+ msec_delay(5);
633+ break;
423634 default:
424635 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
425636 break;
@@ -429,13 +640,13 @@ e1000_reset_hw(struct e1000_hw *hw)
429640 * device. Later controllers reload the EEPROM automatically, so just wait
430641 * for reload to complete.
431642 */
432- switch(hw->mac_type) {
643+ switch (hw->mac_type) {
433644 case e1000_82542_rev2_0:
434645 case e1000_82542_rev2_1:
435646 case e1000_82543:
436647 case e1000_82544:
437648 /* Wait for reset to complete */
438- udelay(10);
649+ usec_delay(10);
439650 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
440651 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
441652 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
@@ -450,20 +661,31 @@ e1000_reset_hw(struct e1000_hw *hw)
450661 /* Wait for EEPROM reload */
451662 msec_delay(20);
452663 break;
664+ case e1000_82573:
665+ if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
666+ usec_delay(10);
667+ ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
668+ ctrl_ext |= E1000_CTRL_EXT_EE_RST;
669+ E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
670+ E1000_WRITE_FLUSH(hw);
671+ }
672+ /* fall through */
453673 default:
454- /* Wait for EEPROM reload (it happens automatically) */
455- msec_delay(5);
674+ /* Auto read done will delay 5ms or poll based on mac type */
675+ ret_val = e1000_get_auto_rd_done(hw);
676+ if (ret_val)
677+ return ret_val;
456678 break;
457679 }
458680
459681 /* Disable HW ARPs on ASF enabled adapters */
460- if(hw->mac_type >= e1000_82540) {
682+ if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
461683 manc = E1000_READ_REG(hw, MANC);
462684 manc &= ~(E1000_MANC_ARP_EN);
463685 E1000_WRITE_REG(hw, MANC, manc);
464686 }
465687
466- if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
688+ if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
467689 e1000_phy_init_script(hw);
468690
469691 /* Configure activity LED after PHY reset */
@@ -481,15 +703,137 @@ e1000_reset_hw(struct e1000_hw *hw)
481703 icr = E1000_READ_REG(hw, ICR);
482704
483705 /* If MWI was previously enabled, reenable it. */
484- if(hw->mac_type == e1000_82542_rev2_0) {
485- if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
706+ if (hw->mac_type == e1000_82542_rev2_0) {
707+ if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
486708 e1000_pci_set_mwi(hw);
487709 }
488710
711+ if (hw->is_ich) {
712+ uint32_t kab = E1000_READ_REG(hw, KABGTXD);
713+ kab |= E1000_KABGTXD_BGSQLBIAS;
714+ E1000_WRITE_REG(hw, KABGTXD, kab);
715+ }
716+
489717 return E1000_SUCCESS;
490718 }
491719
492720 /******************************************************************************
721+ *
722+ * Initialize a number of hardware-dependent bits
723+ *
724+ * hw: Struct containing variables accessed by shared code
725+ *
726+ *****************************************************************************/
727+static void
728+e1000_initialize_hardware_bits(struct e1000_hw *hw)
729+{
730+ if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) {
731+ /* Settings common to all PCI-express silicon */
732+ uint32_t reg_ctrl, reg_ctrl_ext;
733+ uint32_t reg_tarc0, reg_tarc1;
734+ uint32_t reg_tctl;
735+ uint32_t reg_txdctl, reg_txdctl1;
736+
737+ reg_tarc0 = E1000_READ_REG(hw, TARC0);
738+ /* link autonegotiation/sync workarounds */
739+ reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
740+
741+ reg_txdctl = E1000_READ_REG(hw, TXDCTL);
742+ /* Enable not-done TX descriptor counting */
743+ reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
744+ E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
745+
746+ reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
747+ reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
748+ E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
749+
750+ switch (hw->mac_type) {
751+ case e1000_82571:
752+ case e1000_82572:
753+ reg_tarc1 = E1000_READ_REG(hw, TARC1);
754+ reg_tctl = E1000_READ_REG(hw, TCTL);
755+
756+ /* Clear PHY TX compatible mode bits */
757+ reg_tarc1 &= ~((1 << 30)|(1 << 29));
758+
759+ /* link autonegotiation/sync workarounds */
760+ reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
761+ /* TX ring control fixes */
762+ reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
763+
764+ /* Multiple read bit is reversed polarity */
765+ if (reg_tctl & E1000_TCTL_MULR)
766+ reg_tarc1 &= ~(1 << 28);
767+ else
768+ reg_tarc1 |= (1 << 28);
769+
770+ E1000_WRITE_REG(hw, TARC1, reg_tarc1);
771+ break;
772+ case e1000_82573:
773+ reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
774+ reg_ctrl = E1000_READ_REG(hw, CTRL);
775+
776+ reg_ctrl_ext &= ~(1 << 23);
777+ reg_ctrl_ext |= (1 << 22);
778+ /* TX byte count fix */
779+ reg_ctrl &= ~(1 << 29);
780+
781+ E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
782+ E1000_WRITE_REG(hw, CTRL, reg_ctrl);
783+ break;
784+ case e1000_80003es2lan:
785+ /* improve small packet performance for fiber/serdes */
786+ if ((hw->media_type == e1000_media_type_fiber) ||
787+ (hw->media_type == e1000_media_type_internal_serdes)) {
788+ reg_tarc0 &= ~(1 << 20);
789+ }
790+
791+ /* Multiple read bit is reversed polarity */
792+ reg_tctl = E1000_READ_REG(hw, TCTL);
793+ reg_tarc1 = E1000_READ_REG(hw, TARC1);
794+ if (reg_tctl & E1000_TCTL_MULR)
795+ reg_tarc1 &= ~(1 << 28);
796+ else
797+ reg_tarc1 |= (1 << 28);
798+
799+ E1000_WRITE_REG(hw, TARC1, reg_tarc1);
800+ break;
801+ case e1000_ich8lan:
802+ /* Reduce concurrent DMA requests to 3 from 4 */
803+ if ((hw->revision_id < 3) ||
804+ ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
805+ (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
806+ reg_tarc0 |= ((1 << 29)|(1 << 28));
807+ reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
808+ reg_ctrl_ext |= (1 << 22);
809+ E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
810+
811+ /* workaround TX hang with TSO=on */
812+ reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
813+
814+ reg_tarc1 = E1000_READ_REG(hw, TARC1);
815+ reg_tctl = E1000_READ_REG(hw, TCTL);
816+
817+ /* Multiple read bit is reversed polarity */
818+ if (reg_tctl & E1000_TCTL_MULR)
819+ reg_tarc1 &= ~(1 << 28);
820+ else
821+ reg_tarc1 |= (1 << 28);
822+
823+ /* workaround TX hang and TSO=on */
824+ reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
825+
826+ E1000_WRITE_REG(hw, TARC1, reg_tarc1);
827+ break;
828+ default:
829+ break;
830+ }
831+
832+ E1000_WRITE_REG(hw, TARC0, reg_tarc0);
833+ }
834+}
835+
836+/******************************************************************************
493837 * Performs basic configuration of the adapter.
494838 *
495839 * hw - Struct containing variables accessed by shared code
@@ -510,11 +854,25 @@ e1000_init_hw(struct e1000_hw *hw)
510854 uint16_t pcix_stat_hi_word;
511855 uint16_t cmd_mmrbc;
512856 uint16_t stat_mmrbc;
857+ uint32_t mta_size;
858+ uint32_t reg_data;
859+ uint32_t ctrl_ext;
860+
513861 DEBUGFUNC("e1000_init_hw");
514862
863+ /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
864+ if ((hw->mac_type == e1000_ich8lan) &&
865+ ((hw->revision_id < 3) ||
866+ ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
867+ (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
868+ reg_data = E1000_READ_REG(hw, STATUS);
869+ reg_data &= ~0x80000000;
870+ E1000_WRITE_REG(hw, STATUS, reg_data);
871+ }
872+
515873 /* Initialize Identification LED */
516874 ret_val = e1000_id_led_init(hw);
517- if(ret_val) {
875+ if (ret_val) {
518876 DEBUGOUT("Error Initializing Identification LED\n");
519877 return ret_val;
520878 }
@@ -522,14 +880,19 @@ e1000_init_hw(struct e1000_hw *hw)
522880 /* Set the media type and TBI compatibility */
523881 e1000_set_media_type(hw);
524882
883+ /* Must be called after e1000_set_media_type because media_type is used */
884+ e1000_initialize_hardware_bits(hw);
525885 /* Disabling VLAN filtering. */
526886 DEBUGOUT("Initializing the IEEE VLAN\n");
527- E1000_WRITE_REG(hw, VET, 0);
528-
529- e1000_clear_vfta(hw);
887+ /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
888+ if (hw->is_ich == FALSE) {
889+ if (hw->mac_type < e1000_82545_rev_3)
890+ E1000_WRITE_REG(hw, VET, 0);
891+ e1000_clear_vfta(hw);
892+ }
530893
531894 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
532- if(hw->mac_type == e1000_82542_rev2_0) {
895+ if (hw->mac_type == e1000_82542_rev2_0) {
533896 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
534897 e1000_pci_clear_mwi(hw);
535898 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
@@ -543,35 +906,43 @@ e1000_init_hw(struct e1000_hw *hw)
543906 e1000_init_rx_addrs(hw);
544907
545908 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
546- if(hw->mac_type == e1000_82542_rev2_0) {
909+ if (hw->mac_type == e1000_82542_rev2_0) {
547910 E1000_WRITE_REG(hw, RCTL, 0);
548911 E1000_WRITE_FLUSH(hw);
549912 msec_delay(1);
550- if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
913+ if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
551914 e1000_pci_set_mwi(hw);
552915 }
553916
554917 /* Zero out the Multicast HASH table */
555918 DEBUGOUT("Zeroing the MTA\n");
556- for(i = 0; i < E1000_MC_TBL_SIZE; i++)
919+ mta_size = E1000_MC_TBL_SIZE;
920+ if (hw->is_ich == TRUE)
921+ mta_size = E1000_MC_TBL_SIZE_ICHXLAN;
922+ for (i = 0; i < mta_size; i++) {
557923 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
924+ /* use write flush to prevent Memory Write Block (MWB) from
925+ * occuring when accessing our register space */
926+ E1000_WRITE_FLUSH(hw);
927+ }
558928
559929 /* Set the PCI priority bit correctly in the CTRL register. This
560930 * determines if the adapter gives priority to receives, or if it
561- * gives equal priority to transmits and receives.
931+ * gives equal priority to transmits and receives. Valid only on
932+ * 82542 and 82543 silicon.
562933 */
563- if(hw->dma_fairness) {
934+ if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
564935 ctrl = E1000_READ_REG(hw, CTRL);
565936 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
566937 }
567938
568- switch(hw->mac_type) {
939+ switch (hw->mac_type) {
569940 case e1000_82545_rev_3:
570941 case e1000_82546_rev_3:
571942 break;
572943 default:
573944 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
574- if(hw->bus_type == e1000_bus_type_pcix) {
945+ if (hw->bus_type == e1000_bus_type_pcix) {
575946 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
576947 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
577948 &pcix_stat_hi_word);
@@ -579,9 +950,9 @@ e1000_init_hw(struct e1000_hw *hw)
579950 PCIX_COMMAND_MMRBC_SHIFT;
580951 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
581952 PCIX_STATUS_HI_MMRBC_SHIFT;
582- if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
953+ if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
583954 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
584- if(cmd_mmrbc > stat_mmrbc) {
955+ if (cmd_mmrbc > stat_mmrbc) {
585956 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
586957 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
587958 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
@@ -591,16 +962,65 @@ e1000_init_hw(struct e1000_hw *hw)
591962 break;
592963 }
593964
965+ /* More time needed for PHY to initialize */
966+ if (hw->is_ich == TRUE)
967+ msec_delay(15);
968+
594969 /* Call a subroutine to configure the link and setup flow control. */
595970 ret_val = e1000_setup_link(hw);
596971
597972 /* Set the transmit descriptor write-back policy */
598- if(hw->mac_type > e1000_82544) {
973+ if (hw->mac_type > e1000_82544) {
599974 ctrl = E1000_READ_REG(hw, TXDCTL);
600975 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
601976 E1000_WRITE_REG(hw, TXDCTL, ctrl);
602977 }
603978
979+ if (hw->mac_type == e1000_82573) {
980+ e1000_enable_tx_pkt_filtering(hw);
981+ }
982+
983+ switch (hw->mac_type) {
984+ default:
985+ break;
986+ case e1000_80003es2lan:
987+ /* Enable retransmit on late collisions */
988+ reg_data = E1000_READ_REG(hw, TCTL);
989+ reg_data |= E1000_TCTL_RTLC;
990+ E1000_WRITE_REG(hw, TCTL, reg_data);
991+
992+ /* Configure Gigabit Carry Extend Padding */
993+ reg_data = E1000_READ_REG(hw, TCTL_EXT);
994+ reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
995+ reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
996+ E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
997+
998+ /* Configure Transmit Inter-Packet Gap */
999+ reg_data = E1000_READ_REG(hw, TIPG);
1000+ reg_data &= ~E1000_TIPG_IPGT_MASK;
1001+ reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1002+ E1000_WRITE_REG(hw, TIPG, reg_data);
1003+
1004+ reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1005+ reg_data &= ~0x00100000;
1006+ E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1007+ /* Fall through */
1008+ case e1000_82571:
1009+ case e1000_82572:
1010+ case e1000_ich8lan:
1011+ ctrl = E1000_READ_REG(hw, TXDCTL1);
1012+ ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
1013+ E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1014+ break;
1015+ }
1016+
1017+
1018+ if (hw->mac_type == e1000_82573) {
1019+ uint32_t gcr = E1000_READ_REG(hw, GCR);
1020+ gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1021+ E1000_WRITE_REG(hw, GCR, gcr);
1022+ }
1023+
6041024 /* Clear all of the statistics registers (clear on read). It is
6051025 * important that we do this after we have tried to establish link
6061026 * because the symbol error count will increment wildly if there
@@ -608,6 +1028,20 @@ e1000_init_hw(struct e1000_hw *hw)
6081028 */
6091029 e1000_clear_hw_cntrs(hw);
6101030
1031+ /* ICH8 No-snoop bits are opposite polarity.
1032+ * Set to snoop by default after reset. */
1033+ if (hw->mac_type == e1000_ich8lan)
1034+ e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
1035+
1036+ if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1037+ hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1038+ ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1039+ /* Relaxed ordering must be disabled to avoid a parity
1040+ * error crash in a PCI slot. */
1041+ ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1042+ E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1043+ }
1044+
6111045 return ret_val;
6121046 }
6131047
@@ -624,10 +1058,10 @@ e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
6241058
6251059 DEBUGFUNC("e1000_adjust_serdes_amplitude");
6261060
627- if(hw->media_type != e1000_media_type_internal_serdes)
1061+ if (hw->media_type != e1000_media_type_internal_serdes)
6281062 return E1000_SUCCESS;
6291063
630- switch(hw->mac_type) {
1064+ switch (hw->mac_type) {
6311065 case e1000_82545_rev_3:
6321066 case e1000_82546_rev_3:
6331067 break;
@@ -640,11 +1074,11 @@ e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
6401074 return ret_val;
6411075 }
6421076
643- if(eeprom_data != EEPROM_RESERVED_WORD) {
1077+ if (eeprom_data != EEPROM_RESERVED_WORD) {
6441078 /* Adjust SERDES output amplitude only. */
645- eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
1079+ eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
6461080 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
647- if(ret_val)
1081+ if (ret_val)
6481082 return ret_val;
6491083 }
6501084
@@ -671,6 +1105,11 @@ e1000_setup_link(struct e1000_hw *hw)
6711105
6721106 DEBUGFUNC("e1000_setup_link");
6731107
1108+ /* In the case of the phy reset being blocked, we already have a link.
1109+ * We do not have to set it up again. */
1110+ if (e1000_check_phy_reset_block(hw))
1111+ return E1000_SUCCESS;
1112+
6741113 /* Read and store word 0x0F of the EEPROM. This word contains bits
6751114 * that determine the hardware's default PAUSE (flow control) mode,
6761115 * a bit that determines whether the HW defaults to enabling or
@@ -679,30 +1118,39 @@ e1000_setup_link(struct e1000_hw *hw)
6791118 * control setting, then the variable hw->fc will
6801119 * be initialized based on a value in the EEPROM.
6811120 */
682- if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) {
683- DEBUGOUT("EEPROM Read Error\n");
684- return -E1000_ERR_EEPROM;
685- }
686-
687- if(hw->fc == e1000_fc_default) {
688- if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
689- hw->fc = e1000_fc_none;
690- else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
691- EEPROM_WORD0F_ASM_DIR)
692- hw->fc = e1000_fc_tx_pause;
693- else
694- hw->fc = e1000_fc_full;
1121+ if (hw->fc == E1000_FC_DEFAULT) {
1122+ switch (hw->mac_type) {
1123+ case e1000_ich8lan:
1124+ case e1000_82573:
1125+ hw->fc = E1000_FC_FULL;
1126+ break;
1127+ default:
1128+ ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1129+ 1, &eeprom_data);
1130+ if (ret_val) {
1131+ DEBUGOUT("EEPROM Read Error\n");
1132+ return -E1000_ERR_EEPROM;
1133+ }
1134+ if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1135+ hw->fc = E1000_FC_NONE;
1136+ else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1137+ EEPROM_WORD0F_ASM_DIR)
1138+ hw->fc = E1000_FC_TX_PAUSE;
1139+ else
1140+ hw->fc = E1000_FC_FULL;
1141+ break;
1142+ }
6951143 }
6961144
6971145 /* We want to save off the original Flow Control configuration just
6981146 * in case we get disconnected and then reconnected into a different
6991147 * hub or switch with different Flow Control capabilities.
7001148 */
701- if(hw->mac_type == e1000_82542_rev2_0)
702- hw->fc &= (~e1000_fc_tx_pause);
1149+ if (hw->mac_type == e1000_82542_rev2_0)
1150+ hw->fc &= (~E1000_FC_TX_PAUSE);
7031151
704- if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
705- hw->fc &= (~e1000_fc_rx_pause);
1152+ if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1153+ hw->fc &= (~E1000_FC_RX_PAUSE);
7061154
7071155 hw->original_fc = hw->fc;
7081156
@@ -715,7 +1163,13 @@ e1000_setup_link(struct e1000_hw *hw)
7151163 * signal detection. So this should be done before e1000_setup_pcs_link()
7161164 * or e1000_phy_setup() is called.
7171165 */
718- if(hw->mac_type == e1000_82543) {
1166+ if (hw->mac_type == e1000_82543) {
1167+ ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1168+ 1, &eeprom_data);
1169+ if (ret_val) {
1170+ DEBUGOUT("EEPROM Read Error\n");
1171+ return -E1000_ERR_EEPROM;
1172+ }
7191173 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
7201174 SWDPIO__EXT_SHIFT);
7211175 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
@@ -733,9 +1187,13 @@ e1000_setup_link(struct e1000_hw *hw)
7331187 */
7341188 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
7351189
736- E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
737- E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
738- E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1190+ /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1191+ if (hw->is_ich == FALSE) {
1192+ E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1193+ E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1194+ E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1195+ }
1196+
7391197 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
7401198
7411199 /* Set the flow control receive threshold registers. Normally,
@@ -744,14 +1202,14 @@ e1000_setup_link(struct e1000_hw *hw)
7441202 * ability to transmit pause frames in not enabled, then these
7451203 * registers will be set to 0.
7461204 */
747- if(!(hw->fc & e1000_fc_tx_pause)) {
1205+ if (!(hw->fc & E1000_FC_TX_PAUSE)) {
7481206 E1000_WRITE_REG(hw, FCRTL, 0);
7491207 E1000_WRITE_REG(hw, FCRTH, 0);
7501208 } else {
7511209 /* We need to set up the Receive Threshold high and low water marks
7521210 * as well as (optionally) enabling the transmission of XON frames.
7531211 */
754- if(hw->fc_send_xon) {
1212+ if (hw->fc_send_xon) {
7551213 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
7561214 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
7571215 } else {
@@ -783,18 +1241,26 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
7831241
7841242 DEBUGFUNC("e1000_setup_fiber_serdes_link");
7851243
786- /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
1244+ /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
1245+ * until explicitly turned off or a power cycle is performed. A read to
1246+ * the register does not indicate its status. Therefore, we ensure
1247+ * loopback mode is disabled during initialization.
1248+ */
1249+ if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572)
1250+ E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK);
1251+
1252+ /* On adapters with a MAC newer than 82544, SWDP 1 will be
7871253 * set when the optics detect a signal. On older adapters, it will be
7881254 * cleared when there is a signal. This applies to fiber media only.
789- * If we're on serdes media, adjust the output amplitude to value set in
790- * the EEPROM.
1255+ * If we're on serdes media, adjust the output amplitude to value
1256+ * set in the EEPROM.
7911257 */
7921258 ctrl = E1000_READ_REG(hw, CTRL);
793- if(hw->media_type == e1000_media_type_fiber)
1259+ if (hw->media_type == e1000_media_type_fiber)
7941260 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
7951261
7961262 ret_val = e1000_adjust_serdes_amplitude(hw);
797- if(ret_val)
1263+ if (ret_val)
7981264 return ret_val;
7991265
8001266 /* Take the link out of reset */
@@ -802,7 +1268,7 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
8021268
8031269 /* Adjust VCO speed to improve BER performance */
8041270 ret_val = e1000_set_vco_speed(hw);
805- if(ret_val)
1271+ if (ret_val)
8061272 return ret_val;
8071273
8081274 e1000_config_collision_dist(hw);
@@ -823,11 +1289,11 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
8231289 * 3: Both Rx and TX flow control (symmetric) are enabled.
8241290 */
8251291 switch (hw->fc) {
826- case e1000_fc_none:
1292+ case E1000_FC_NONE:
8271293 /* Flow control is completely disabled by a software over-ride. */
8281294 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
8291295 break;
830- case e1000_fc_rx_pause:
1296+ case E1000_FC_RX_PAUSE:
8311297 /* RX Flow control is enabled and TX Flow control is disabled by a
8321298 * software over-ride. Since there really isn't a way to advertise
8331299 * that we are capable of RX Pause ONLY, we will advertise that we
@@ -836,13 +1302,13 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
8361302 */
8371303 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
8381304 break;
839- case e1000_fc_tx_pause:
1305+ case E1000_FC_TX_PAUSE:
8401306 /* TX Flow control is enabled, and RX Flow control is disabled, by a
8411307 * software over-ride.
8421308 */
8431309 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
8441310 break;
845- case e1000_fc_full:
1311+ case E1000_FC_FULL:
8461312 /* Flow control (both RX and TX) is enabled by a software over-ride. */
8471313 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
8481314 break;
@@ -873,15 +1339,15 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
8731339 * less than 500 milliseconds even if the other end is doing it in SW).
8741340 * For internal serdes, we just assume a signal is present, then poll.
8751341 */
876- if(hw->media_type == e1000_media_type_internal_serdes ||
1342+ if (hw->media_type == e1000_media_type_internal_serdes ||
8771343 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
8781344 DEBUGOUT("Looking for Link\n");
879- for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1345+ for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
8801346 msec_delay(10);
8811347 status = E1000_READ_REG(hw, STATUS);
882- if(status & E1000_STATUS_LU) break;
1348+ if (status & E1000_STATUS_LU) break;
8831349 }
884- if(i == (LINK_UP_TIMEOUT / 10)) {
1350+ if (i == (LINK_UP_TIMEOUT / 10)) {
8851351 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
8861352 hw->autoneg_failed = 1;
8871353 /* AutoNeg failed to achieve a link, so we'll call
@@ -890,7 +1356,7 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
8901356 * non-autonegotiating link partners.
8911357 */
8921358 ret_val = e1000_check_for_link(hw);
893- if(ret_val) {
1359+ if (ret_val) {
8941360 DEBUGOUT("Error while checking for link\n");
8951361 return ret_val;
8961362 }
@@ -906,39 +1372,39 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
9061372 }
9071373
9081374 /******************************************************************************
909-* Detects which PHY is present and the speed and duplex
1375+* Make sure we have a valid PHY and change PHY mode before link setup.
9101376 *
9111377 * hw - Struct containing variables accessed by shared code
9121378 ******************************************************************************/
9131379 static int32_t
914-e1000_setup_copper_link(struct e1000_hw *hw)
1380+e1000_copper_link_preconfig(struct e1000_hw *hw)
9151381 {
9161382 uint32_t ctrl;
917- uint32_t led_ctrl;
9181383 int32_t ret_val;
919- uint16_t i;
9201384 uint16_t phy_data;
9211385
922- DEBUGFUNC("e1000_setup_copper_link");
1386+ DEBUGFUNC("e1000_copper_link_preconfig");
9231387
9241388 ctrl = E1000_READ_REG(hw, CTRL);
9251389 /* With 82543, we need to force speed and duplex on the MAC equal to what
9261390 * the PHY speed and duplex configuration is. In addition, we need to
9271391 * perform a hardware reset on the PHY to take it out of reset.
9281392 */
929- if(hw->mac_type > e1000_82543) {
1393+ if (hw->mac_type > e1000_82543) {
9301394 ctrl |= E1000_CTRL_SLU;
9311395 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
9321396 E1000_WRITE_REG(hw, CTRL, ctrl);
9331397 } else {
9341398 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
9351399 E1000_WRITE_REG(hw, CTRL, ctrl);
936- e1000_phy_hw_reset(hw);
1400+ ret_val = e1000_phy_hw_reset(hw);
1401+ if (ret_val)
1402+ return ret_val;
9371403 }
9381404
9391405 /* Make sure we have a valid PHY */
9401406 ret_val = e1000_detect_gig_phy(hw);
941- if(ret_val) {
1407+ if (ret_val) {
9421408 DEBUGOUT("Error, did not detect valid phy.\n");
9431409 return ret_val;
9441410 }
@@ -946,520 +1412,904 @@ e1000_setup_copper_link(struct e1000_hw *hw)
9461412
9471413 /* Set PHY to class A mode (if necessary) */
9481414 ret_val = e1000_set_phy_mode(hw);
949- if(ret_val)
1415+ if (ret_val)
9501416 return ret_val;
9511417
952- if((hw->mac_type == e1000_82545_rev_3) ||
1418+ if ((hw->mac_type == e1000_82545_rev_3) ||
9531419 (hw->mac_type == e1000_82546_rev_3)) {
9541420 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
9551421 phy_data |= 0x00000008;
9561422 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
9571423 }
9581424
959- if(hw->mac_type <= e1000_82543 ||
960- hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
961- hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
1425+ if (hw->mac_type <= e1000_82543 ||
1426+ hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1427+ hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
9621428 hw->phy_reset_disable = FALSE;
9631429
964- if(!hw->phy_reset_disable) {
965- if (hw->phy_type == e1000_phy_igp) {
1430+ return E1000_SUCCESS;
1431+}
9661432
967- ret_val = e1000_phy_reset(hw);
968- if(ret_val) {
969- DEBUGOUT("Error Resetting the PHY\n");
970- return ret_val;
971- }
9721433
973- /* Wait 10ms for MAC to configure PHY from eeprom settings */
974- msec_delay(15);
1434+/********************************************************************
1435+* Copper link setup for e1000_phy_igp series.
1436+*
1437+* hw - Struct containing variables accessed by shared code
1438+*********************************************************************/
1439+static int32_t
1440+e1000_copper_link_igp_setup(struct e1000_hw *hw)
1441+{
1442+ uint32_t led_ctrl;
1443+ int32_t ret_val;
1444+ uint16_t phy_data;
9751445
976- /* Configure activity LED after PHY reset */
977- led_ctrl = E1000_READ_REG(hw, LEDCTL);
978- led_ctrl &= IGP_ACTIVITY_LED_MASK;
979- led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
980- E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
1446+ DEBUGFUNC("e1000_copper_link_igp_setup");
9811447
982- /* disable lplu d3 during driver init */
983- ret_val = e1000_set_d3_lplu_state(hw, FALSE);
984- if(ret_val) {
985- DEBUGOUT("Error Disabling LPLU D3\n");
986- return ret_val;
987- }
1448+ if (hw->phy_reset_disable)
1449+ return E1000_SUCCESS;
9881450
989- /* Configure mdi-mdix settings */
990- ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
991- &phy_data);
992- if(ret_val)
993- return ret_val;
1451+ ret_val = e1000_phy_reset(hw);
1452+ if (ret_val) {
1453+ DEBUGOUT("Error Resetting the PHY\n");
1454+ return ret_val;
1455+ }
9941456
995- if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
996- hw->dsp_config_state = e1000_dsp_config_disabled;
997- /* Force MDI for earlier revs of the IGP PHY */
998- phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX |
999- IGP01E1000_PSCR_FORCE_MDI_MDIX);
1000- hw->mdix = 1;
1457+ /* Wait 15ms for MAC to configure PHY from eeprom settings */
1458+ msec_delay(15);
1459+ if (hw->is_ich == FALSE) {
1460+ /* Configure activity LED after PHY reset */
1461+ led_ctrl = E1000_READ_REG(hw, LEDCTL);
1462+ led_ctrl &= IGP_ACTIVITY_LED_MASK;
1463+ led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1464+ E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
1465+ }
10011466
1002- } else {
1003- hw->dsp_config_state = e1000_dsp_config_enabled;
1004- phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1467+ /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
1468+ if (hw->phy_type == e1000_phy_igp) {
1469+ /* disable lplu d3 during driver init */
1470+ ret_val = e1000_set_d3_lplu_state(hw, FALSE);
1471+ if (ret_val) {
1472+ DEBUGOUT("Error Disabling LPLU D3\n");
1473+ return ret_val;
1474+ }
1475+ }
10051476
1006- switch (hw->mdix) {
1007- case 1:
1008- phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1009- break;
1010- case 2:
1011- phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1012- break;
1013- case 0:
1014- default:
1015- phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1016- break;
1017- }
1018- }
1019- ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1020- phy_data);
1021- if(ret_val)
1022- return ret_val;
1477+ /* disable lplu d0 during driver init */
1478+ ret_val = e1000_set_d0_lplu_state(hw, FALSE);
1479+ if (ret_val) {
1480+ DEBUGOUT("Error Disabling LPLU D0\n");
1481+ return ret_val;
1482+ }
1483+ /* Configure mdi-mdix settings */
1484+ ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1485+ if (ret_val)
1486+ return ret_val;
10231487
1024- /* set auto-master slave resolution settings */
1025- if(hw->autoneg) {
1026- e1000_ms_type phy_ms_setting = hw->master_slave;
1488+ if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1489+ hw->dsp_config_state = e1000_dsp_config_disabled;
1490+ /* Force MDI for earlier revs of the IGP PHY */
1491+ phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
1492+ hw->mdix = 1;
10271493
1028- if(hw->ffe_config_state == e1000_ffe_config_active)
1029- hw->ffe_config_state = e1000_ffe_config_enabled;
1494+ } else {
1495+ hw->dsp_config_state = e1000_dsp_config_enabled;
1496+ phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
10301497
1031- if(hw->dsp_config_state == e1000_dsp_config_activated)
1032- hw->dsp_config_state = e1000_dsp_config_enabled;
1498+ switch (hw->mdix) {
1499+ case 1:
1500+ phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1501+ break;
1502+ case 2:
1503+ phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1504+ break;
1505+ case 0:
1506+ default:
1507+ phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1508+ break;
1509+ }
1510+ }
1511+ ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1512+ if (ret_val)
1513+ return ret_val;
10331514
1034- /* when autonegotiation advertisment is only 1000Mbps then we
1035- * should disable SmartSpeed and enable Auto MasterSlave
1036- * resolution as hardware default. */
1037- if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1038- /* Disable SmartSpeed */
1039- ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1040- &phy_data);
1041- if(ret_val)
1042- return ret_val;
1043- phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1044- ret_val = e1000_write_phy_reg(hw,
1045- IGP01E1000_PHY_PORT_CONFIG,
1046- phy_data);
1047- if(ret_val)
1048- return ret_val;
1049- /* Set auto Master/Slave resolution process */
1050- ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1051- if(ret_val)
1052- return ret_val;
1053- phy_data &= ~CR_1000T_MS_ENABLE;
1054- ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1055- if(ret_val)
1056- return ret_val;
1057- }
1515+ /* set auto-master slave resolution settings */
1516+ if (hw->autoneg) {
1517+ e1000_ms_type phy_ms_setting = hw->master_slave;
10581518
1059- ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1060- if(ret_val)
1061- return ret_val;
1519+ if (hw->ffe_config_state == e1000_ffe_config_active)
1520+ hw->ffe_config_state = e1000_ffe_config_enabled;
10621521
1063- /* load defaults for future use */
1064- hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1065- ((phy_data & CR_1000T_MS_VALUE) ?
1066- e1000_ms_force_master :
1067- e1000_ms_force_slave) :
1068- e1000_ms_auto;
1522+ if (hw->dsp_config_state == e1000_dsp_config_activated)
1523+ hw->dsp_config_state = e1000_dsp_config_enabled;
10691524
1070- switch (phy_ms_setting) {
1071- case e1000_ms_force_master:
1072- phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1073- break;
1074- case e1000_ms_force_slave:
1075- phy_data |= CR_1000T_MS_ENABLE;
1076- phy_data &= ~(CR_1000T_MS_VALUE);
1077- break;
1078- case e1000_ms_auto:
1079- phy_data &= ~CR_1000T_MS_ENABLE;
1080- default:
1081- break;
1082- }
1083- ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1084- if(ret_val)
1085- return ret_val;
1086- }
1087- } else {
1088- /* Enable CRS on TX. This must be set for half-duplex operation. */
1089- ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1525+ /* when autonegotiation advertisment is only 1000Mbps then we
1526+ * should disable SmartSpeed and enable Auto MasterSlave
1527+ * resolution as hardware default. */
1528+ if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1529+ /* Disable SmartSpeed */
1530+ ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
10901531 &phy_data);
1091- if(ret_val)
1532+ if (ret_val)
10921533 return ret_val;
1093-
1094- phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1095-
1096- /* Options:
1097- * MDI/MDI-X = 0 (default)
1098- * 0 - Auto for all speeds
1099- * 1 - MDI mode
1100- * 2 - MDI-X mode
1101- * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1102- */
1103- phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1104-
1105- switch (hw->mdix) {
1106- case 1:
1107- phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1108- break;
1109- case 2:
1110- phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1111- break;
1112- case 3:
1113- phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1114- break;
1115- case 0:
1116- default:
1117- phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1118- break;
1119- }
1120-
1121- /* Options:
1122- * disable_polarity_correction = 0 (default)
1123- * Automatic Correction for Reversed Cable Polarity
1124- * 0 - Disabled
1125- * 1 - Enabled
1126- */
1127- phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1128- if(hw->disable_polarity_correction == 1)
1129- phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1130- ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1534+ phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1535+ ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
11311536 phy_data);
1132- if(ret_val)
1537+ if (ret_val)
11331538 return ret_val;
1134-
1135- /* Force TX_CLK in the Extended PHY Specific Control Register
1136- * to 25MHz clock.
1137- */
1138- ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1139- &phy_data);
1140- if(ret_val)
1539+ /* Set auto Master/Slave resolution process */
1540+ ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1541+ if (ret_val)
11411542 return ret_val;
1142-
1143- phy_data |= M88E1000_EPSCR_TX_CLK_25;
1144-
1145- if (hw->phy_revision < M88E1011_I_REV_4) {
1146- /* Configure Master and Slave downshift values */
1147- phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1148- M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1149- phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1150- M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1151- ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1152- phy_data);
1153- if(ret_val)
1154- return ret_val;
1155- }
1156-
1157- /* SW Reset the PHY so all changes take effect */
1158- ret_val = e1000_phy_reset(hw);
1159- if(ret_val) {
1160- DEBUGOUT("Error Resetting the PHY\n");
1543+ phy_data &= ~CR_1000T_MS_ENABLE;
1544+ ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1545+ if (ret_val)
11611546 return ret_val;
1162- }
11631547 }
11641548
1165- /* Options:
1166- * autoneg = 1 (default)
1167- * PHY will advertise value(s) parsed from
1168- * autoneg_advertised and fc
1169- * autoneg = 0
1170- * PHY will be set to 10H, 10F, 100H, or 100F
1171- * depending on value parsed from forced_speed_duplex.
1172- */
1549+ ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1550+ if (ret_val)
1551+ return ret_val;
11731552
1174- /* Is autoneg enabled? This is enabled by default or by software
1175- * override. If so, call e1000_phy_setup_autoneg routine to parse the
1176- * autoneg_advertised and fc options. If autoneg is NOT enabled, then
1177- * the user should have provided a speed/duplex override. If so, then
1178- * call e1000_phy_force_speed_duplex to parse and set this up.
1179- */
1180- if(hw->autoneg) {
1181- /* Perform some bounds checking on the hw->autoneg_advertised
1182- * parameter. If this variable is zero, then set it to the default.
1183- */
1184- hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1553+ /* load defaults for future use */
1554+ hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1555+ ((phy_data & CR_1000T_MS_VALUE) ?
1556+ e1000_ms_force_master :
1557+ e1000_ms_force_slave) :
1558+ e1000_ms_auto;
11851559
1186- /* If autoneg_advertised is zero, we assume it was not defaulted
1187- * by the calling code so we set to advertise full capability.
1188- */
1189- if(hw->autoneg_advertised == 0)
1190- hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1560+ switch (phy_ms_setting) {
1561+ case e1000_ms_force_master:
1562+ phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1563+ break;
1564+ case e1000_ms_force_slave:
1565+ phy_data |= CR_1000T_MS_ENABLE;
1566+ phy_data &= ~(CR_1000T_MS_VALUE);
1567+ break;
1568+ case e1000_ms_auto:
1569+ phy_data &= ~CR_1000T_MS_ENABLE;
1570+ default:
1571+ break;
1572+ }
1573+ ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1574+ if (ret_val)
1575+ return ret_val;
1576+ }
11911577
1192- DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1193- ret_val = e1000_phy_setup_autoneg(hw);
1194- if(ret_val) {
1195- DEBUGOUT("Error Setting up Auto-Negotiation\n");
1196- return ret_val;
1197- }
1198- DEBUGOUT("Restarting Auto-Neg\n");
1578+ return E1000_SUCCESS;
1579+}
11991580
1200- /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1201- * the Auto Neg Restart bit in the PHY control register.
1202- */
1203- ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1204- if(ret_val)
1205- return ret_val;
1581+/********************************************************************
1582+* Copper link setup for e1000_phy_gg82563 series.
1583+*
1584+* hw - Struct containing variables accessed by shared code
1585+*********************************************************************/
1586+static int32_t
1587+e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1588+{
1589+ int32_t ret_val;
1590+ uint16_t phy_data;
1591+ uint32_t reg_data;
12061592
1207- phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1208- ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1209- if(ret_val)
1210- return ret_val;
1593+ DEBUGFUNC("e1000_copper_link_ggp_setup");
12111594
1212- /* Does the user want to wait for Auto-Neg to complete here, or
1213- * check at a later time (for example, callback routine).
1214- */
1215- if(hw->wait_autoneg_complete) {
1216- ret_val = e1000_wait_autoneg(hw);
1217- if(ret_val) {
1218- DEBUGOUT("Error while waiting for autoneg to complete\n");
1219- return ret_val;
1220- }
1221- }
1222- hw->get_link_status = TRUE;
1223- } else {
1224- DEBUGOUT("Forcing speed and duplex\n");
1225- ret_val = e1000_phy_force_speed_duplex(hw);
1226- if(ret_val) {
1227- DEBUGOUT("Error Forcing Speed and Duplex\n");
1228- return ret_val;
1229- }
1595+ if (!hw->phy_reset_disable) {
1596+
1597+ /* Enable CRS on TX for half-duplex operation. */
1598+ ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1599+ &phy_data);
1600+ if (ret_val)
1601+ return ret_val;
1602+
1603+ phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1604+ /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
1605+ phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
1606+
1607+ ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1608+ phy_data);
1609+ if (ret_val)
1610+ return ret_val;
1611+
1612+ /* Options:
1613+ * MDI/MDI-X = 0 (default)
1614+ * 0 - Auto for all speeds
1615+ * 1 - MDI mode
1616+ * 2 - MDI-X mode
1617+ * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1618+ */
1619+ ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
1620+ if (ret_val)
1621+ return ret_val;
1622+
1623+ phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1624+
1625+ switch (hw->mdix) {
1626+ case 1:
1627+ phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1628+ break;
1629+ case 2:
1630+ phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1631+ break;
1632+ case 0:
1633+ default:
1634+ phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1635+ break;
12301636 }
1231- } /* !hw->phy_reset_disable */
12321637
1233- /* Check link status. Wait up to 100 microseconds for link to become
1234- * valid.
1235- */
1236- for(i = 0; i < 10; i++) {
1237- ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1238- if(ret_val)
1638+ /* Options:
1639+ * disable_polarity_correction = 0 (default)
1640+ * Automatic Correction for Reversed Cable Polarity
1641+ * 0 - Disabled
1642+ * 1 - Enabled
1643+ */
1644+ phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1645+ if (hw->disable_polarity_correction == 1)
1646+ phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1647+ ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
1648+
1649+ if (ret_val)
12391650 return ret_val;
1240- ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1241- if(ret_val)
1651+
1652+ /* SW Reset the PHY so all changes take effect */
1653+ ret_val = e1000_phy_reset(hw);
1654+ if (ret_val) {
1655+ DEBUGOUT("Error Resetting the PHY\n");
1656+ return ret_val;
1657+ }
1658+ } /* phy_reset_disable */
1659+
1660+ if (hw->mac_type == e1000_80003es2lan) {
1661+ /* Bypass RX and TX FIFO's */
1662+ ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
1663+ E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
1664+ E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
1665+ if (ret_val)
12421666 return ret_val;
12431667
1244- if(phy_data & MII_SR_LINK_STATUS) {
1245- /* We have link, so we need to finish the config process:
1246- * 1) Set up the MAC to the current PHY speed/duplex
1247- * if we are on 82543. If we
1248- * are on newer silicon, we only need to configure
1249- * collision distance in the Transmit Control Register.
1250- * 2) Set up flow control on the MAC to that established with
1251- * the link partner.
1252- */
1253- if(hw->mac_type >= e1000_82544) {
1254- e1000_config_collision_dist(hw);
1255- } else {
1256- ret_val = e1000_config_mac_to_phy(hw);
1257- if(ret_val) {
1258- DEBUGOUT("Error configuring MAC to PHY settings\n");
1259- return ret_val;
1260- }
1261- }
1262- ret_val = e1000_config_fc_after_link_up(hw);
1263- if(ret_val) {
1264- DEBUGOUT("Error Configuring Flow Control\n");
1668+ ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
1669+ if (ret_val)
1670+ return ret_val;
1671+
1672+ phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1673+ ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
1674+
1675+ if (ret_val)
1676+ return ret_val;
1677+
1678+ reg_data = E1000_READ_REG(hw, CTRL_EXT);
1679+ reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1680+ E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
1681+
1682+ ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1683+ &phy_data);
1684+ if (ret_val)
1685+ return ret_val;
1686+
1687+ /* Do not init these registers when the HW is in IAMT mode, since the
1688+ * firmware will have already initialized them. We only initialize
1689+ * them if the HW is not in IAMT mode.
1690+ */
1691+ if (e1000_check_mng_mode(hw) == FALSE) {
1692+ /* Enable Electrical Idle on the PHY */
1693+ phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1694+ ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1695+ phy_data);
1696+ if (ret_val)
12651697 return ret_val;
1266- }
1267- DEBUGOUT("Valid link established!!!\n");
12681698
1269- if(hw->phy_type == e1000_phy_igp) {
1270- ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
1271- if(ret_val) {
1272- DEBUGOUT("Error Configuring DSP after link up\n");
1273- return ret_val;
1274- }
1275- }
1276- DEBUGOUT("Valid link established!!!\n");
1277- return E1000_SUCCESS;
1699+ ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1700+ &phy_data);
1701+ if (ret_val)
1702+ return ret_val;
1703+
1704+ phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1705+ ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1706+ phy_data);
1707+
1708+ if (ret_val)
1709+ return ret_val;
12781710 }
1279- udelay(10);
1711+
1712+ /* Workaround: Disable padding in Kumeran interface in the MAC
1713+ * and in the PHY to avoid CRC errors.
1714+ */
1715+ ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1716+ &phy_data);
1717+ if (ret_val)
1718+ return ret_val;
1719+ phy_data |= GG82563_ICR_DIS_PADDING;
1720+ ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1721+ phy_data);
1722+ if (ret_val)
1723+ return ret_val;
12801724 }
12811725
1282- DEBUGOUT("Unable to establish link!!!\n");
12831726 return E1000_SUCCESS;
12841727 }
12851728
1286-/******************************************************************************
1287-* Configures PHY autoneg and flow control advertisement settings
1729+/********************************************************************
1730+* Copper link setup for e1000_phy_m88 series.
12881731 *
12891732 * hw - Struct containing variables accessed by shared code
1290-******************************************************************************/
1291-int32_t
1292-e1000_phy_setup_autoneg(struct e1000_hw *hw)
1733+*********************************************************************/
1734+static int32_t
1735+e1000_copper_link_mgp_setup(struct e1000_hw *hw)
12931736 {
12941737 int32_t ret_val;
1295- uint16_t mii_autoneg_adv_reg;
1296- uint16_t mii_1000t_ctrl_reg;
1738+ uint16_t phy_data;
12971739
1298- DEBUGFUNC("e1000_phy_setup_autoneg");
1740+ DEBUGFUNC("e1000_copper_link_mgp_setup");
12991741
1300- /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1301- ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1302- if(ret_val)
1303- return ret_val;
1742+ if (hw->phy_reset_disable)
1743+ return E1000_SUCCESS;
13041744
1305- /* Read the MII 1000Base-T Control Register (Address 9). */
1306- ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1307- if(ret_val)
1745+ /* Enable CRS on TX. This must be set for half-duplex operation. */
1746+ ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1747+ if (ret_val)
13081748 return ret_val;
13091749
1310- /* Need to parse both autoneg_advertised and fc and set up
1311- * the appropriate PHY registers. First we will parse for
1312- * autoneg_advertised software override. Since we can advertise
1313- * a plethora of combinations, we need to check each bit
1314- * individually.
1750+ phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1751+
1752+ /* Options:
1753+ * MDI/MDI-X = 0 (default)
1754+ * 0 - Auto for all speeds
1755+ * 1 - MDI mode
1756+ * 2 - MDI-X mode
1757+ * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
13151758 */
1759+ phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
13161760
1317- /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1318- * Advertisement Register (Address 4) and the 1000 mb speed bits in
1319- * the 1000Base-T Control Register (Address 9).
1761+ switch (hw->mdix) {
1762+ case 1:
1763+ phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1764+ break;
1765+ case 2:
1766+ phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1767+ break;
1768+ case 3:
1769+ phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1770+ break;
1771+ case 0:
1772+ default:
1773+ phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1774+ break;
1775+ }
1776+
1777+ /* Options:
1778+ * disable_polarity_correction = 0 (default)
1779+ * Automatic Correction for Reversed Cable Polarity
1780+ * 0 - Disabled
1781+ * 1 - Enabled
13201782 */
1321- mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1322- mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1783+ phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1784+ if (hw->disable_polarity_correction == 1)
1785+ phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1786+ ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1787+ if (ret_val)
1788+ return ret_val;
13231789
1324- DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
1790+ if (hw->phy_revision < M88E1011_I_REV_4) {
1791+ /* Force TX_CLK in the Extended PHY Specific Control Register
1792+ * to 25MHz clock.
1793+ */
1794+ ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1795+ if (ret_val)
1796+ return ret_val;
13251797
1326- /* Do we want to advertise 10 Mb Half Duplex? */
1327- if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
1328- DEBUGOUT("Advertise 10mb Half duplex\n");
1329- mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1330- }
1798+ phy_data |= M88E1000_EPSCR_TX_CLK_25;
13311799
1332- /* Do we want to advertise 10 Mb Full Duplex? */
1333- if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
1334- DEBUGOUT("Advertise 10mb Full duplex\n");
1335- mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1800+ if ((hw->phy_revision == E1000_REVISION_2) &&
1801+ (hw->phy_id == M88E1111_I_PHY_ID)) {
1802+ /* Vidalia Phy, set the downshift counter to 5x */
1803+ phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1804+ phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1805+ ret_val = e1000_write_phy_reg(hw,
1806+ M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1807+ if (ret_val)
1808+ return ret_val;
1809+ } else {
1810+ /* Configure Master and Slave downshift values */
1811+ phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1812+ M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1813+ phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1814+ M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1815+ ret_val = e1000_write_phy_reg(hw,
1816+ M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1817+ if (ret_val)
1818+ return ret_val;
1819+ }
13361820 }
13371821
1338- /* Do we want to advertise 100 Mb Half Duplex? */
1339- if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
1340- DEBUGOUT("Advertise 100mb Half duplex\n");
1341- mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1822+ /* SW Reset the PHY so all changes take effect */
1823+ ret_val = e1000_phy_reset(hw);
1824+ if (ret_val) {
1825+ DEBUGOUT("Error Resetting the PHY\n");
1826+ return ret_val;
13421827 }
13431828
1344- /* Do we want to advertise 100 Mb Full Duplex? */
1345- if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
1346- DEBUGOUT("Advertise 100mb Full duplex\n");
1347- mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1348- }
1829+ return E1000_SUCCESS;
1830+}
13491831
1350- /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1351- if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1352- DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
1353- }
1832+/********************************************************************
1833+* Setup auto-negotiation and flow control advertisements,
1834+* and then perform auto-negotiation.
1835+*
1836+* hw - Struct containing variables accessed by shared code
1837+*********************************************************************/
1838+static int32_t
1839+e1000_copper_link_autoneg(struct e1000_hw *hw)
1840+{
1841+ int32_t ret_val;
1842+ uint16_t phy_data;
13541843
1355- /* Do we want to advertise 1000 Mb Full Duplex? */
1356- if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1357- DEBUGOUT("Advertise 1000mb Full duplex\n");
1358- mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1359- }
1844+ DEBUGFUNC("e1000_copper_link_autoneg");
13601845
1361- /* Check for a software override of the flow control settings, and
1362- * setup the PHY advertisement registers accordingly. If
1363- * auto-negotiation is enabled, then software will have to set the
1364- * "PAUSE" bits to the correct value in the Auto-Negotiation
1365- * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1366- *
1367- * The possible values of the "fc" parameter are:
1368- * 0: Flow control is completely disabled
1369- * 1: Rx flow control is enabled (we can receive pause frames
1370- * but not send pause frames).
1371- * 2: Tx flow control is enabled (we can send pause frames
1372- * but we do not support receiving pause frames).
1373- * 3: Both Rx and TX flow control (symmetric) are enabled.
1374- * other: No software override. The flow control configuration
1375- * in the EEPROM is used.
1846+ /* Perform some bounds checking on the hw->autoneg_advertised
1847+ * parameter. If this variable is zero, then set it to the default.
13761848 */
1377- switch (hw->fc) {
1378- case e1000_fc_none: /* 0 */
1379- /* Flow control (RX & TX) is completely disabled by a
1380- * software over-ride.
1381- */
1382- mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1383- break;
1384- case e1000_fc_rx_pause: /* 1 */
1385- /* RX Flow control is enabled, and TX Flow control is
1386- * disabled, by a software over-ride.
1387- */
1388- /* Since there really isn't a way to advertise that we are
1389- * capable of RX Pause ONLY, we will advertise that we
1390- * support both symmetric and asymmetric RX PAUSE. Later
1391- * (in e1000_config_fc_after_link_up) we will disable the
1392- *hw's ability to send PAUSE frames.
1393- */
1394- mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1395- break;
1396- case e1000_fc_tx_pause: /* 2 */
1397- /* TX Flow control is enabled, and RX Flow control is
1398- * disabled, by a software over-ride.
1399- */
1400- mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1401- mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1402- break;
1403- case e1000_fc_full: /* 3 */
1404- /* Flow control (both RX and TX) is enabled by a software
1405- * over-ride.
1406- */
1407- mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1408- break;
1409- default:
1410- DEBUGOUT("Flow control param set incorrectly\n");
1411- return -E1000_ERR_CONFIG;
1412- }
1849+ hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
14131850
1414- ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1415- if(ret_val)
1851+ /* If autoneg_advertised is zero, we assume it was not defaulted
1852+ * by the calling code so we set to advertise full capability.
1853+ */
1854+ if (hw->autoneg_advertised == 0)
1855+ hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1856+
1857+ /* IFE phy only supports 10/100 */
1858+ if (hw->phy_type == e1000_phy_ife)
1859+ hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1860+
1861+ DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1862+ ret_val = e1000_phy_setup_autoneg(hw);
1863+ if (ret_val) {
1864+ DEBUGOUT("Error Setting up Auto-Negotiation\n");
14161865 return ret_val;
1866+ }
1867+ DEBUGOUT("Restarting Auto-Neg\n");
14171868
1418- DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1869+ /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1870+ * the Auto Neg Restart bit in the PHY control register.
1871+ */
1872+ ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1873+ if (ret_val)
1874+ return ret_val;
14191875
1420- ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
1421-
1422- if(ret_val)
1876+ phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1877+ ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1878+ if (ret_val)
14231879 return ret_val;
14241880
1881+ /* Does the user want to wait for Auto-Neg to complete here, or
1882+ * check at a later time (for example, callback routine).
1883+ */
1884+ if (hw->wait_autoneg_complete) {
1885+ ret_val = e1000_wait_autoneg(hw);
1886+ if (ret_val) {
1887+ DEBUGOUT("Error while waiting for autoneg to complete\n");
1888+ return ret_val;
1889+ }
1890+ }
1891+
1892+ hw->get_link_status = TRUE;
1893+
14251894 return E1000_SUCCESS;
14261895 }
14271896
14281897 /******************************************************************************
1429-* Force PHY speed and duplex settings to hw->forced_speed_duplex
1898+* Config the MAC and the PHY after link is up.
1899+* 1) Set up the MAC to the current PHY speed/duplex
1900+* if we are on 82543. If we
1901+* are on newer silicon, we only need to configure
1902+* collision distance in the Transmit Control Register.
1903+* 2) Set up flow control on the MAC to that established with
1904+* the link partner.
1905+* 3) Config DSP to improve Gigabit link quality for some PHY revisions.
14301906 *
14311907 * hw - Struct containing variables accessed by shared code
14321908 ******************************************************************************/
14331909 static int32_t
1434-e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1910+e1000_copper_link_postconfig(struct e1000_hw *hw)
14351911 {
1436- uint32_t ctrl;
14371912 int32_t ret_val;
1438- uint16_t mii_ctrl_reg;
1439- uint16_t mii_status_reg;
1440- uint16_t phy_data;
1441- uint16_t i;
1913+ DEBUGFUNC("e1000_copper_link_postconfig");
14421914
1443- DEBUGFUNC("e1000_phy_force_speed_duplex");
1915+ if (hw->mac_type >= e1000_82544) {
1916+ e1000_config_collision_dist(hw);
1917+ } else {
1918+ ret_val = e1000_config_mac_to_phy(hw);
1919+ if (ret_val) {
1920+ DEBUGOUT("Error configuring MAC to PHY settings\n");
1921+ return ret_val;
1922+ }
1923+ }
1924+ ret_val = e1000_config_fc_after_link_up(hw);
1925+ if (ret_val) {
1926+ DEBUGOUT("Error Configuring Flow Control\n");
1927+ return ret_val;
1928+ }
14441929
1445- /* Turn off Flow control if we are forcing speed and duplex. */
1446- hw->fc = e1000_fc_none;
1930+ /* Config DSP to improve Giga link quality */
1931+ if (hw->phy_type == e1000_phy_igp) {
1932+ ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
1933+ if (ret_val) {
1934+ DEBUGOUT("Error Configuring DSP after link up\n");
1935+ return ret_val;
1936+ }
1937+ }
14471938
1448- DEBUGOUT1("hw->fc = %d\n", hw->fc);
1939+ return E1000_SUCCESS;
1940+}
14491941
1450- /* Read the Device Control Register. */
1451- ctrl = E1000_READ_REG(hw, CTRL);
1942+/******************************************************************************
1943+* Detects which PHY is present and setup the speed and duplex
1944+*
1945+* hw - Struct containing variables accessed by shared code
1946+******************************************************************************/
1947+static int32_t
1948+e1000_setup_copper_link(struct e1000_hw *hw)
1949+{
1950+ int32_t ret_val;
1951+ uint16_t i;
1952+ uint16_t phy_data;
1953+ uint16_t reg_data;
14521954
1453- /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
1454- ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1455- ctrl &= ~(DEVICE_SPEED_MASK);
1955+ DEBUGFUNC("e1000_setup_copper_link");
1956+
1957+ switch (hw->mac_type) {
1958+ case e1000_80003es2lan:
1959+ case e1000_ich8lan:
1960+ /* Set the mac to wait the maximum time between each
1961+ * iteration and increase the max iterations when
1962+ * polling the phy; this fixes erroneous timeouts at 10Mbps. */
1963+ ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1964+ if (ret_val)
1965+ return ret_val;
1966+ ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
1967+ if (ret_val)
1968+ return ret_val;
1969+ reg_data |= 0x3F;
1970+ ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
1971+ if (ret_val)
1972+ return ret_val;
1973+ default:
1974+ break;
1975+ }
1976+
1977+ /* Check if it is a valid PHY and set PHY mode if necessary. */
1978+ ret_val = e1000_copper_link_preconfig(hw);
1979+ if (ret_val)
1980+ return ret_val;
1981+
1982+ switch (hw->mac_type) {
1983+ case e1000_80003es2lan:
1984+ /* Kumeran registers are written-only */
1985+ reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
1986+ reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
1987+ ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
1988+ reg_data);
1989+ if (ret_val)
1990+ return ret_val;
1991+ break;
1992+ default:
1993+ break;
1994+ }
1995+
1996+ if (hw->phy_type == e1000_phy_igp ||
1997+ hw->phy_type == e1000_phy_igp_3 ||
1998+ hw->phy_type == e1000_phy_igp_2) {
1999+ ret_val = e1000_copper_link_igp_setup(hw);
2000+ if (ret_val)
2001+ return ret_val;
2002+ } else if (hw->phy_type == e1000_phy_m88) {
2003+ ret_val = e1000_copper_link_mgp_setup(hw);
2004+ if (ret_val)
2005+ return ret_val;
2006+ } else if (hw->phy_type == e1000_phy_gg82563) {
2007+ ret_val = e1000_copper_link_ggp_setup(hw);
2008+ if (ret_val)
2009+ return ret_val;
2010+ }
2011+
2012+ if (hw->autoneg) {
2013+ /* Setup autoneg and flow control advertisement
2014+ * and perform autonegotiation */
2015+ ret_val = e1000_copper_link_autoneg(hw);
2016+ if (ret_val)
2017+ return ret_val;
2018+ } else {
2019+ /* PHY will be set to 10H, 10F, 100H,or 100F
2020+ * depending on value from forced_speed_duplex. */
2021+ DEBUGOUT("Forcing speed and duplex\n");
2022+ ret_val = e1000_phy_force_speed_duplex(hw);
2023+ if (ret_val) {
2024+ DEBUGOUT("Error Forcing Speed and Duplex\n");
2025+ return ret_val;
2026+ }
2027+ }
2028+
2029+ /* Check link status. Wait up to 100 microseconds for link to become
2030+ * valid.
2031+ */
2032+ for (i = 0; i < 10; i++) {
2033+ ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2034+ if (ret_val)
2035+ return ret_val;
2036+ ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2037+ if (ret_val)
2038+ return ret_val;
2039+
2040+ if (phy_data & MII_SR_LINK_STATUS) {
2041+ /* Config the MAC and PHY after link is up */
2042+ ret_val = e1000_copper_link_postconfig(hw);
2043+ if (ret_val)
2044+ return ret_val;
2045+
2046+ DEBUGOUT("Valid link established!!!\n");
2047+ return E1000_SUCCESS;
2048+ }
2049+ usec_delay(10);
2050+ }
2051+
2052+ DEBUGOUT("Unable to establish link!!!\n");
2053+ return E1000_SUCCESS;
2054+}
2055+
2056+/******************************************************************************
2057+* Configure the MAC-to-PHY interface for 10/100Mbps
2058+*
2059+* hw - Struct containing variables accessed by shared code
2060+******************************************************************************/
2061+static int32_t
2062+e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
2063+{
2064+ int32_t ret_val = E1000_SUCCESS;
2065+ uint32_t tipg;
2066+ uint16_t reg_data;
2067+
2068+ DEBUGFUNC("e1000_configure_kmrn_for_10_100");
2069+
2070+ reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
2071+ ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2072+ reg_data);
2073+ if (ret_val)
2074+ return ret_val;
2075+
2076+ /* Configure Transmit Inter-Packet Gap */
2077+ tipg = E1000_READ_REG(hw, TIPG);
2078+ tipg &= ~E1000_TIPG_IPGT_MASK;
2079+ tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
2080+ E1000_WRITE_REG(hw, TIPG, tipg);
2081+
2082+ ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
2083+
2084+ if (ret_val)
2085+ return ret_val;
2086+
2087+ if (duplex == HALF_DUPLEX)
2088+ reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
2089+ else
2090+ reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2091+
2092+ ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2093+
2094+ return ret_val;
2095+}
2096+
2097+static int32_t
2098+e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
2099+{
2100+ int32_t ret_val = E1000_SUCCESS;
2101+ uint16_t reg_data;
2102+ uint32_t tipg;
2103+
2104+ DEBUGFUNC("e1000_configure_kmrn_for_1000");
2105+
2106+ reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
2107+ ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2108+ reg_data);
2109+ if (ret_val)
2110+ return ret_val;
2111+
2112+ /* Configure Transmit Inter-Packet Gap */
2113+ tipg = E1000_READ_REG(hw, TIPG);
2114+ tipg &= ~E1000_TIPG_IPGT_MASK;
2115+ tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
2116+ E1000_WRITE_REG(hw, TIPG, tipg);
2117+
2118+ ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
2119+
2120+ if (ret_val)
2121+ return ret_val;
2122+
2123+ reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2124+ ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2125+
2126+ return ret_val;
2127+}
2128+
2129+/******************************************************************************
2130+* Configures PHY autoneg and flow control advertisement settings
2131+*
2132+* hw - Struct containing variables accessed by shared code
2133+******************************************************************************/
2134+int32_t
2135+e1000_phy_setup_autoneg(struct e1000_hw *hw)
2136+{
2137+ int32_t ret_val;
2138+ uint16_t mii_autoneg_adv_reg;
2139+ uint16_t mii_1000t_ctrl_reg;
2140+
2141+ DEBUGFUNC("e1000_phy_setup_autoneg");
2142+
2143+ /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2144+ ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
2145+ if (ret_val)
2146+ return ret_val;
2147+
2148+ if (hw->phy_type != e1000_phy_ife) {
2149+ /* Read the MII 1000Base-T Control Register (Address 9). */
2150+ ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
2151+ if (ret_val)
2152+ return ret_val;
2153+ } else
2154+ mii_1000t_ctrl_reg=0;
2155+
2156+ /* Need to parse both autoneg_advertised and fc and set up
2157+ * the appropriate PHY registers. First we will parse for
2158+ * autoneg_advertised software override. Since we can advertise
2159+ * a plethora of combinations, we need to check each bit
2160+ * individually.
2161+ */
2162+
2163+ /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2164+ * Advertisement Register (Address 4) and the 1000 mb speed bits in
2165+ * the 1000Base-T Control Register (Address 9).
2166+ */
2167+ mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
2168+ mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
2169+
2170+ DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
2171+
2172+ /* Do we want to advertise 10 Mb Half Duplex? */
2173+ if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
2174+ DEBUGOUT("Advertise 10mb Half duplex\n");
2175+ mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
2176+ }
2177+
2178+ /* Do we want to advertise 10 Mb Full Duplex? */
2179+ if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
2180+ DEBUGOUT("Advertise 10mb Full duplex\n");
2181+ mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
2182+ }
2183+
2184+ /* Do we want to advertise 100 Mb Half Duplex? */
2185+ if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
2186+ DEBUGOUT("Advertise 100mb Half duplex\n");
2187+ mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
2188+ }
2189+
2190+ /* Do we want to advertise 100 Mb Full Duplex? */
2191+ if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
2192+ DEBUGOUT("Advertise 100mb Full duplex\n");
2193+ mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
2194+ }
2195+
2196+ /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
2197+ if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
2198+ DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
2199+ }
2200+
2201+ /* Do we want to advertise 1000 Mb Full Duplex? */
2202+ if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
2203+ DEBUGOUT("Advertise 1000mb Full duplex\n");
2204+ mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
2205+ if (hw->phy_type == e1000_phy_ife) {
2206+ DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n");
2207+ }
2208+ }
2209+
2210+ /* Check for a software override of the flow control settings, and
2211+ * setup the PHY advertisement registers accordingly. If
2212+ * auto-negotiation is enabled, then software will have to set the
2213+ * "PAUSE" bits to the correct value in the Auto-Negotiation
2214+ * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
2215+ *
2216+ * The possible values of the "fc" parameter are:
2217+ * 0: Flow control is completely disabled
2218+ * 1: Rx flow control is enabled (we can receive pause frames
2219+ * but not send pause frames).
2220+ * 2: Tx flow control is enabled (we can send pause frames
2221+ * but we do not support receiving pause frames).
2222+ * 3: Both Rx and TX flow control (symmetric) are enabled.
2223+ * other: No software override. The flow control configuration
2224+ * in the EEPROM is used.
2225+ */
2226+ switch (hw->fc) {
2227+ case E1000_FC_NONE: /* 0 */
2228+ /* Flow control (RX & TX) is completely disabled by a
2229+ * software over-ride.
2230+ */
2231+ mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2232+ break;
2233+ case E1000_FC_RX_PAUSE: /* 1 */
2234+ /* RX Flow control is enabled, and TX Flow control is
2235+ * disabled, by a software over-ride.
2236+ */
2237+ /* Since there really isn't a way to advertise that we are
2238+ * capable of RX Pause ONLY, we will advertise that we
2239+ * support both symmetric and asymmetric RX PAUSE. Later
2240+ * (in e1000_config_fc_after_link_up) we will disable the
2241+ *hw's ability to send PAUSE frames.
2242+ */
2243+ mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2244+ break;
2245+ case E1000_FC_TX_PAUSE: /* 2 */
2246+ /* TX Flow control is enabled, and RX Flow control is
2247+ * disabled, by a software over-ride.
2248+ */
2249+ mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
2250+ mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
2251+ break;
2252+ case E1000_FC_FULL: /* 3 */
2253+ /* Flow control (both RX and TX) is enabled by a software
2254+ * over-ride.
2255+ */
2256+ mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2257+ break;
2258+ default:
2259+ DEBUGOUT("Flow control param set incorrectly\n");
2260+ return -E1000_ERR_CONFIG;
2261+ }
2262+
2263+ ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
2264+ if (ret_val)
2265+ return ret_val;
2266+
2267+ DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
2268+
2269+ if (hw->phy_type != e1000_phy_ife) {
2270+ ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
2271+ if (ret_val)
2272+ return ret_val;
2273+ }
2274+
2275+ return E1000_SUCCESS;
2276+}
2277+
2278+/******************************************************************************
2279+* Force PHY speed and duplex settings to hw->forced_speed_duplex
2280+*
2281+* hw - Struct containing variables accessed by shared code
2282+******************************************************************************/
2283+static int32_t
2284+e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2285+{
2286+ uint32_t ctrl;
2287+ int32_t ret_val;
2288+ uint16_t mii_ctrl_reg;
2289+ uint16_t mii_status_reg;
2290+ uint16_t phy_data;
2291+ uint16_t i;
2292+
2293+ DEBUGFUNC("e1000_phy_force_speed_duplex");
2294+
2295+ /* Turn off Flow control if we are forcing speed and duplex. */
2296+ hw->fc = E1000_FC_NONE;
2297+
2298+ DEBUGOUT1("hw->fc = %d\n", hw->fc);
2299+
2300+ /* Read the Device Control Register. */
2301+ ctrl = E1000_READ_REG(hw, CTRL);
2302+
2303+ /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
2304+ ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2305+ ctrl &= ~(DEVICE_SPEED_MASK);
14562306
14572307 /* Clear the Auto Speed Detect Enable bit. */
14582308 ctrl &= ~E1000_CTRL_ASDE;
14592309
14602310 /* Read the MII Control Register. */
14612311 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
1462- if(ret_val)
2312+ if (ret_val)
14632313 return ret_val;
14642314
14652315 /* We need to disable autoneg in order to force link and duplex. */
@@ -1467,8 +2317,8 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
14672317 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
14682318
14692319 /* Are we forcing Full or Half Duplex? */
1470- if(hw->forced_speed_duplex == e1000_100_full ||
1471- hw->forced_speed_duplex == e1000_10_full) {
2320+ if (hw->forced_speed_duplex == e1000_100_full ||
2321+ hw->forced_speed_duplex == e1000_10_full) {
14722322 /* We want to force full duplex so we SET the full duplex bits in the
14732323 * Device and MII Control Registers.
14742324 */
@@ -1485,7 +2335,7 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
14852335 }
14862336
14872337 /* Are we forcing 100Mbps??? */
1488- if(hw->forced_speed_duplex == e1000_100_full ||
2338+ if (hw->forced_speed_duplex == e1000_100_full ||
14892339 hw->forced_speed_duplex == e1000_100_half) {
14902340 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
14912341 ctrl |= E1000_CTRL_SPD_100;
@@ -1505,9 +2355,10 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
15052355 /* Write the configured values back to the Device Control Reg. */
15062356 E1000_WRITE_REG(hw, CTRL, ctrl);
15072357
1508- if (hw->phy_type == e1000_phy_m88) {
2358+ if ((hw->phy_type == e1000_phy_m88) ||
2359+ (hw->phy_type == e1000_phy_gg82563)) {
15092360 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1510- if(ret_val)
2361+ if (ret_val)
15112362 return ret_val;
15122363
15132364 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
@@ -1515,35 +2366,49 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
15152366 */
15162367 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
15172368 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1518- if(ret_val)
2369+ if (ret_val)
15192370 return ret_val;
15202371
15212372 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
15222373
15232374 /* Need to reset the PHY or these changes will be ignored */
15242375 mii_ctrl_reg |= MII_CR_RESET;
2376+
2377+ /* Disable MDI-X support for 10/100 */
2378+ } else if (hw->phy_type == e1000_phy_ife) {
2379+ ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
2380+ if (ret_val)
2381+ return ret_val;
2382+
2383+ phy_data &= ~IFE_PMC_AUTO_MDIX;
2384+ phy_data &= ~IFE_PMC_FORCE_MDIX;
2385+
2386+ ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
2387+ if (ret_val)
2388+ return ret_val;
2389+
15252390 } else {
15262391 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
15272392 * forced whenever speed or duplex are forced.
15282393 */
15292394 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1530- if(ret_val)
2395+ if (ret_val)
15312396 return ret_val;
15322397
15332398 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
15342399 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
15352400
15362401 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1537- if(ret_val)
2402+ if (ret_val)
15382403 return ret_val;
15392404 }
15402405
15412406 /* Write back the modified PHY MII control register. */
15422407 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
1543- if(ret_val)
2408+ if (ret_val)
15442409 return ret_val;
15452410
1546- udelay(1);
2411+ usec_delay(1);
15472412
15482413 /* The wait_autoneg_complete flag may be a little misleading here.
15492414 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
@@ -1552,49 +2417,50 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
15522417 * only if the user has set wait_autoneg_complete to 1, which is
15532418 * the default.
15542419 */
1555- if(hw->wait_autoneg_complete) {
2420+ if (hw->wait_autoneg_complete) {
15562421 /* We will wait for autoneg to complete. */
15572422 DEBUGOUT("Waiting for forced speed/duplex link.\n");
15582423 mii_status_reg = 0;
15592424
15602425 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
1561- for(i = PHY_FORCE_TIME; i > 0; i--) {
2426+ for (i = PHY_FORCE_TIME; i > 0; i--) {
15622427 /* Read the MII Status Register and wait for Auto-Neg Complete bit
15632428 * to be set.
15642429 */
15652430 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1566- if(ret_val)
2431+ if (ret_val)
15672432 return ret_val;
15682433
15692434 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1570- if(ret_val)
2435+ if (ret_val)
15712436 return ret_val;
15722437
1573- if(mii_status_reg & MII_SR_LINK_STATUS) break;
2438+ if (mii_status_reg & MII_SR_LINK_STATUS) break;
15742439 msec_delay(100);
15752440 }
1576- if((i == 0) &&
1577- (hw->phy_type == e1000_phy_m88)) {
2441+ if ((i == 0) &&
2442+ ((hw->phy_type == e1000_phy_m88) ||
2443+ (hw->phy_type == e1000_phy_gg82563))) {
15782444 /* We didn't get link. Reset the DSP and wait again for link. */
15792445 ret_val = e1000_phy_reset_dsp(hw);
1580- if(ret_val) {
2446+ if (ret_val) {
15812447 DEBUGOUT("Error Resetting PHY DSP\n");
15822448 return ret_val;
15832449 }
15842450 }
15852451 /* This loop will early-out if the link condition has been met. */
1586- for(i = PHY_FORCE_TIME; i > 0; i--) {
1587- if(mii_status_reg & MII_SR_LINK_STATUS) break;
2452+ for (i = PHY_FORCE_TIME; i > 0; i--) {
2453+ if (mii_status_reg & MII_SR_LINK_STATUS) break;
15882454 msec_delay(100);
15892455 /* Read the MII Status Register and wait for Auto-Neg Complete bit
15902456 * to be set.
15912457 */
15922458 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1593- if(ret_val)
2459+ if (ret_val)
15942460 return ret_val;
15952461
15962462 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1597- if(ret_val)
2463+ if (ret_val)
15982464 return ret_val;
15992465 }
16002466 }
@@ -1605,34 +2471,54 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
16052471 * defaults back to a 2.5MHz clock when the PHY is reset.
16062472 */
16072473 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1608- if(ret_val)
2474+ if (ret_val)
16092475 return ret_val;
16102476
16112477 phy_data |= M88E1000_EPSCR_TX_CLK_25;
16122478 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1613- if(ret_val)
2479+ if (ret_val)
16142480 return ret_val;
16152481
16162482 /* In addition, because of the s/w reset above, we need to enable CRS on
16172483 * TX. This must be set for both full and half duplex operation.
16182484 */
16192485 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1620- if(ret_val)
2486+ if (ret_val)
16212487 return ret_val;
16222488
16232489 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
16242490 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1625- if(ret_val)
2491+ if (ret_val)
16262492 return ret_val;
16272493
1628- if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
1629- (!hw->autoneg) &&
1630- (hw->forced_speed_duplex == e1000_10_full ||
1631- hw->forced_speed_duplex == e1000_10_half)) {
2494+ if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2495+ (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full ||
2496+ hw->forced_speed_duplex == e1000_10_half)) {
16322497 ret_val = e1000_polarity_reversal_workaround(hw);
1633- if(ret_val)
2498+ if (ret_val)
16342499 return ret_val;
16352500 }
2501+ } else if (hw->phy_type == e1000_phy_gg82563) {
2502+ /* The TX_CLK of the Extended PHY Specific Control Register defaults
2503+ * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if
2504+ * we're not in a forced 10/duplex configuration. */
2505+ ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2506+ if (ret_val)
2507+ return ret_val;
2508+
2509+ phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
2510+ if ((hw->forced_speed_duplex == e1000_10_full) ||
2511+ (hw->forced_speed_duplex == e1000_10_half))
2512+ phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
2513+ else
2514+ phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
2515+
2516+ /* Also due to the reset, we need to enable CRS on Tx. */
2517+ phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2518+
2519+ ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2520+ if (ret_val)
2521+ return ret_val;
16362522 }
16372523 return E1000_SUCCESS;
16382524 }
@@ -1648,14 +2534,19 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
16482534 void
16492535 e1000_config_collision_dist(struct e1000_hw *hw)
16502536 {
1651- uint32_t tctl;
2537+ uint32_t tctl, coll_dist;
16522538
16532539 DEBUGFUNC("e1000_config_collision_dist");
16542540
2541+ if (hw->mac_type < e1000_82543)
2542+ coll_dist = E1000_COLLISION_DISTANCE_82542;
2543+ else
2544+ coll_dist = E1000_COLLISION_DISTANCE;
2545+
16552546 tctl = E1000_READ_REG(hw, TCTL);
16562547
16572548 tctl &= ~E1000_TCTL_COLD;
1658- tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
2549+ tctl |= coll_dist << E1000_COLD_SHIFT;
16592550
16602551 E1000_WRITE_REG(hw, TCTL, tctl);
16612552 E1000_WRITE_FLUSH(hw);
@@ -1679,6 +2570,11 @@ e1000_config_mac_to_phy(struct e1000_hw *hw)
16792570
16802571 DEBUGFUNC("e1000_config_mac_to_phy");
16812572
2573+ /* 82544 or newer MAC, Auto Speed Detection takes care of
2574+ * MAC speed/duplex configuration.*/
2575+ if (hw->mac_type >= e1000_82544)
2576+ return E1000_SUCCESS;
2577+
16822578 /* Read the Device Control Register and set the bits to Force Speed
16832579 * and Duplex.
16842580 */
@@ -1689,45 +2585,25 @@ e1000_config_mac_to_phy(struct e1000_hw *hw)
16892585 /* Set up duplex in the Device Control and Transmit Control
16902586 * registers depending on negotiated values.
16912587 */
1692- if (hw->phy_type == e1000_phy_igp) {
1693- ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
1694- &phy_data);
1695- if(ret_val)
1696- return ret_val;
1697-
1698- if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl |= E1000_CTRL_FD;
1699- else ctrl &= ~E1000_CTRL_FD;
1700-
1701- e1000_config_collision_dist(hw);
2588+ ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2589+ if (ret_val)
2590+ return ret_val;
17022591
1703- /* Set up speed in the Device Control register depending on
1704- * negotiated values.
1705- */
1706- if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1707- IGP01E1000_PSSR_SPEED_1000MBPS)
1708- ctrl |= E1000_CTRL_SPD_1000;
1709- else if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1710- IGP01E1000_PSSR_SPEED_100MBPS)
1711- ctrl |= E1000_CTRL_SPD_100;
1712- } else {
1713- ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
1714- &phy_data);
1715- if(ret_val)
1716- return ret_val;
2592+ if (phy_data & M88E1000_PSSR_DPLX)
2593+ ctrl |= E1000_CTRL_FD;
2594+ else
2595+ ctrl &= ~E1000_CTRL_FD;
17172596
1718- if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD;
1719- else ctrl &= ~E1000_CTRL_FD;
2597+ e1000_config_collision_dist(hw);
17202598
1721- e1000_config_collision_dist(hw);
2599+ /* Set up speed in the Device Control register depending on
2600+ * negotiated values.
2601+ */
2602+ if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2603+ ctrl |= E1000_CTRL_SPD_1000;
2604+ else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
2605+ ctrl |= E1000_CTRL_SPD_100;
17222606
1723- /* Set up speed in the Device Control register depending on
1724- * negotiated values.
1725- */
1726- if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1727- ctrl |= E1000_CTRL_SPD_1000;
1728- else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1729- ctrl |= E1000_CTRL_SPD_100;
1730- }
17312607 /* Write the configured values back to the Device Control Reg. */
17322608 E1000_WRITE_REG(hw, CTRL, ctrl);
17332609 return E1000_SUCCESS;
@@ -1773,18 +2649,18 @@ e1000_force_mac_fc(struct e1000_hw *hw)
17732649 */
17742650
17752651 switch (hw->fc) {
1776- case e1000_fc_none:
2652+ case E1000_FC_NONE:
17772653 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
17782654 break;
1779- case e1000_fc_rx_pause:
2655+ case E1000_FC_RX_PAUSE:
17802656 ctrl &= (~E1000_CTRL_TFCE);
17812657 ctrl |= E1000_CTRL_RFCE;
17822658 break;
1783- case e1000_fc_tx_pause:
2659+ case E1000_FC_TX_PAUSE:
17842660 ctrl &= (~E1000_CTRL_RFCE);
17852661 ctrl |= E1000_CTRL_TFCE;
17862662 break;
1787- case e1000_fc_full:
2663+ case E1000_FC_FULL:
17882664 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
17892665 break;
17902666 default:
@@ -1793,7 +2669,7 @@ e1000_force_mac_fc(struct e1000_hw *hw)
17932669 }
17942670
17952671 /* Disable TX Flow Control for 82542 (rev 2.0) */
1796- if(hw->mac_type == e1000_82542_rev2_0)
2672+ if (hw->mac_type == e1000_82542_rev2_0)
17972673 ctrl &= (~E1000_CTRL_TFCE);
17982674
17992675 E1000_WRITE_REG(hw, CTRL, ctrl);
@@ -1811,7 +2687,7 @@ e1000_force_mac_fc(struct e1000_hw *hw)
18112687 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
18122688 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
18132689 *****************************************************************************/
1814-int32_t
2690+static int32_t
18152691 e1000_config_fc_after_link_up(struct e1000_hw *hw)
18162692 {
18172693 int32_t ret_val;
@@ -1827,11 +2703,12 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
18272703 * so we had to force link. In this case, we need to force the
18282704 * configuration of the MAC to match the "fc" parameter.
18292705 */
1830- if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
1831- ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed)) ||
1832- ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
2706+ if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
2707+ ((hw->media_type == e1000_media_type_internal_serdes) &&
2708+ (hw->autoneg_failed)) ||
2709+ ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
18332710 ret_val = e1000_force_mac_fc(hw);
1834- if(ret_val) {
2711+ if (ret_val) {
18352712 DEBUGOUT("Error forcing flow control settings\n");
18362713 return ret_val;
18372714 }
@@ -1842,19 +2719,19 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
18422719 * has completed, and if so, how the PHY and link partner has
18432720 * flow control configured.
18442721 */
1845- if((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2722+ if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
18462723 /* Read the MII Status Register and check to see if AutoNeg
18472724 * has completed. We read this twice because this reg has
18482725 * some "sticky" (latched) bits.
18492726 */
18502727 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1851- if(ret_val)
2728+ if (ret_val)
18522729 return ret_val;
18532730 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1854- if(ret_val)
2731+ if (ret_val)
18552732 return ret_val;
18562733
1857- if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2734+ if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
18582735 /* The AutoNeg process has completed, so we now need to
18592736 * read both the Auto Negotiation Advertisement Register
18602737 * (Address 4) and the Auto_Negotiation Base Page Ability
@@ -1863,11 +2740,11 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
18632740 */
18642741 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
18652742 &mii_nway_adv_reg);
1866- if(ret_val)
2743+ if (ret_val)
18672744 return ret_val;
18682745 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
18692746 &mii_nway_lp_ability_reg);
1870- if(ret_val)
2747+ if (ret_val)
18712748 return ret_val;
18722749
18732750 /* Two bits in the Auto Negotiation Advertisement Register
@@ -1882,14 +2759,14 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
18822759 * LOCAL DEVICE | LINK PARTNER
18832760 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
18842761 *-------|---------|-------|---------|--------------------
1885- * 0 | 0 | DC | DC | e1000_fc_none
1886- * 0 | 1 | 0 | DC | e1000_fc_none
1887- * 0 | 1 | 1 | 0 | e1000_fc_none
1888- * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1889- * 1 | 0 | 0 | DC | e1000_fc_none
1890- * 1 | DC | 1 | DC | e1000_fc_full
1891- * 1 | 1 | 0 | 0 | e1000_fc_none
1892- * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
2762+ * 0 | 0 | DC | DC | E1000_FC_NONE
2763+ * 0 | 1 | 0 | DC | E1000_FC_NONE
2764+ * 0 | 1 | 1 | 0 | E1000_FC_NONE
2765+ * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2766+ * 1 | 0 | 0 | DC | E1000_FC_NONE
2767+ * 1 | DC | 1 | DC | E1000_FC_FULL
2768+ * 1 | 1 | 0 | 0 | E1000_FC_NONE
2769+ * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
18932770 *
18942771 */
18952772 /* Are both PAUSE bits set to 1? If so, this implies
@@ -1901,23 +2778,23 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
19012778 * LOCAL DEVICE | LINK PARTNER
19022779 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
19032780 *-------|---------|-------|---------|--------------------
1904- * 1 | DC | 1 | DC | e1000_fc_full
2781+ * 1 | DC | 1 | DC | E1000_FC_FULL
19052782 *
19062783 */
1907- if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1908- (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2784+ if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2785+ (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
19092786 /* Now we need to check if the user selected RX ONLY
19102787 * of pause frames. In this case, we had to advertise
19112788 * FULL flow control because we could not advertise RX
19122789 * ONLY. Hence, we must now check to see if we need to
19132790 * turn OFF the TRANSMISSION of PAUSE frames.
19142791 */
1915- if(hw->original_fc == e1000_fc_full) {
1916- hw->fc = e1000_fc_full;
1917- DEBUGOUT("Flow Control = FULL.\r\n");
2792+ if (hw->original_fc == E1000_FC_FULL) {
2793+ hw->fc = E1000_FC_FULL;
2794+ DEBUGOUT("Flow Control = FULL.\n");
19182795 } else {
1919- hw->fc = e1000_fc_rx_pause;
1920- DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2796+ hw->fc = E1000_FC_RX_PAUSE;
2797+ DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
19212798 }
19222799 }
19232800 /* For receiving PAUSE frames ONLY.
@@ -1925,30 +2802,30 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
19252802 * LOCAL DEVICE | LINK PARTNER
19262803 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
19272804 *-------|---------|-------|---------|--------------------
1928- * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
2805+ * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
19292806 *
19302807 */
1931- else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1932- (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1933- (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1934- (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1935- hw->fc = e1000_fc_tx_pause;
1936- DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
2808+ else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2809+ (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2810+ (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2811+ (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2812+ hw->fc = E1000_FC_TX_PAUSE;
2813+ DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
19372814 }
19382815 /* For transmitting PAUSE frames ONLY.
19392816 *
19402817 * LOCAL DEVICE | LINK PARTNER
19412818 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
19422819 *-------|---------|-------|---------|--------------------
1943- * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
2820+ * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
19442821 *
19452822 */
1946- else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1947- (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1948- !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1949- (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1950- hw->fc = e1000_fc_rx_pause;
1951- DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2823+ else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2824+ (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2825+ !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2826+ (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2827+ hw->fc = E1000_FC_RX_PAUSE;
2828+ DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
19522829 }
19532830 /* Per the IEEE spec, at this point flow control should be
19542831 * disabled. However, we want to consider that we could
@@ -1970,14 +2847,14 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
19702847 * be asked to delay transmission of packets than asking
19712848 * our link partner to pause transmission of frames.
19722849 */
1973- else if((hw->original_fc == e1000_fc_none ||
1974- hw->original_fc == e1000_fc_tx_pause) ||
1975- hw->fc_strict_ieee) {
1976- hw->fc = e1000_fc_none;
1977- DEBUGOUT("Flow Control = NONE.\r\n");
2850+ else if ((hw->original_fc == E1000_FC_NONE||
2851+ hw->original_fc == E1000_FC_TX_PAUSE) ||
2852+ hw->fc_strict_ieee) {
2853+ hw->fc = E1000_FC_NONE;
2854+ DEBUGOUT("Flow Control = NONE.\n");
19782855 } else {
1979- hw->fc = e1000_fc_rx_pause;
1980- DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2856+ hw->fc = E1000_FC_RX_PAUSE;
2857+ DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
19812858 }
19822859
19832860 /* Now we need to do one last check... If we auto-
@@ -1985,24 +2862,24 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
19852862 * enabled per IEEE 802.3 spec.
19862863 */
19872864 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
1988- if(ret_val) {
2865+ if (ret_val) {
19892866 DEBUGOUT("Error getting link speed and duplex\n");
19902867 return ret_val;
19912868 }
19922869
1993- if(duplex == HALF_DUPLEX)
1994- hw->fc = e1000_fc_none;
2870+ if (duplex == HALF_DUPLEX)
2871+ hw->fc = E1000_FC_NONE;
19952872
19962873 /* Now we call a subroutine to actually force the MAC
19972874 * controller to use the correct flow control settings.
19982875 */
19992876 ret_val = e1000_force_mac_fc(hw);
2000- if(ret_val) {
2877+ if (ret_val) {
20012878 DEBUGOUT("Error forcing flow control settings\n");
20022879 return ret_val;
20032880 }
20042881 } else {
2005- DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
2882+ DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
20062883 }
20072884 }
20082885 return E1000_SUCCESS;
@@ -2036,13 +2913,13 @@ e1000_check_for_link(struct e1000_hw *hw)
20362913 * set when the optics detect a signal. On older adapters, it will be
20372914 * cleared when there is a signal. This applies to fiber media only.
20382915 */
2039- if((hw->media_type == e1000_media_type_fiber) ||
2040- (hw->media_type == e1000_media_type_internal_serdes)) {
2916+ if ((hw->media_type == e1000_media_type_fiber) ||
2917+ (hw->media_type == e1000_media_type_internal_serdes)) {
20412918 rxcw = E1000_READ_REG(hw, RXCW);
20422919
2043- if(hw->media_type == e1000_media_type_fiber) {
2920+ if (hw->media_type == e1000_media_type_fiber) {
20442921 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2045- if(status & E1000_STATUS_LU)
2922+ if (status & E1000_STATUS_LU)
20462923 hw->get_link_status = FALSE;
20472924 }
20482925 }
@@ -2053,20 +2930,20 @@ e1000_check_for_link(struct e1000_hw *hw)
20532930 * receive a Link Status Change interrupt or we have Rx Sequence
20542931 * Errors.
20552932 */
2056- if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2933+ if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
20572934 /* First we want to see if the MII Status Register reports
20582935 * link. If so, then we want to get the current speed/duplex
20592936 * of the PHY.
20602937 * Read the register twice since the link bit is sticky.
20612938 */
20622939 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2063- if(ret_val)
2940+ if (ret_val)
20642941 return ret_val;
20652942 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2066- if(ret_val)
2943+ if (ret_val)
20672944 return ret_val;
20682945
2069- if(phy_data & MII_SR_LINK_STATUS) {
2946+ if (phy_data & MII_SR_LINK_STATUS) {
20702947 hw->get_link_status = FALSE;
20712948 /* Check if there was DownShift, must be checked immediately after
20722949 * link-up */
@@ -2080,10 +2957,10 @@ e1000_check_for_link(struct e1000_hw *hw)
20802957 * happen due to the execution of this workaround.
20812958 */
20822959
2083- if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2084- (!hw->autoneg) &&
2085- (hw->forced_speed_duplex == e1000_10_full ||
2086- hw->forced_speed_duplex == e1000_10_half)) {
2960+ if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2961+ (!hw->autoneg) &&
2962+ (hw->forced_speed_duplex == e1000_10_full ||
2963+ hw->forced_speed_duplex == e1000_10_half)) {
20872964 E1000_WRITE_REG(hw, IMC, 0xffffffff);
20882965 ret_val = e1000_polarity_reversal_workaround(hw);
20892966 icr = E1000_READ_REG(hw, ICR);
@@ -2100,7 +2977,7 @@ e1000_check_for_link(struct e1000_hw *hw)
21002977 /* If we are forcing speed/duplex, then we simply return since
21012978 * we have already determined whether we have link or not.
21022979 */
2103- if(!hw->autoneg) return -E1000_ERR_CONFIG;
2980+ if (!hw->autoneg) return -E1000_ERR_CONFIG;
21042981
21052982 /* optimize the dsp settings for the igp phy */
21062983 e1000_config_dsp_after_link_change(hw, TRUE);
@@ -2113,11 +2990,11 @@ e1000_check_for_link(struct e1000_hw *hw)
21132990 * speed/duplex on the MAC to the current PHY speed/duplex
21142991 * settings.
21152992 */
2116- if(hw->mac_type >= e1000_82544)
2993+ if (hw->mac_type >= e1000_82544)
21172994 e1000_config_collision_dist(hw);
21182995 else {
21192996 ret_val = e1000_config_mac_to_phy(hw);
2120- if(ret_val) {
2997+ if (ret_val) {
21212998 DEBUGOUT("Error configuring MAC to PHY settings\n");
21222999 return ret_val;
21233000 }
@@ -2128,7 +3005,7 @@ e1000_check_for_link(struct e1000_hw *hw)
21283005 * have had to re-autoneg with a different link partner.
21293006 */
21303007 ret_val = e1000_config_fc_after_link_up(hw);
2131- if(ret_val) {
3008+ if (ret_val) {
21323009 DEBUGOUT("Error configuring flow control\n");
21333010 return ret_val;
21343011 }
@@ -2140,14 +3017,18 @@ e1000_check_for_link(struct e1000_hw *hw)
21403017 * at gigabit speed, then TBI compatibility is not needed. If we are
21413018 * at gigabit speed, we turn on TBI compatibility.
21423019 */
2143- if(hw->tbi_compatibility_en) {
3020+ if (hw->tbi_compatibility_en) {
21443021 uint16_t speed, duplex;
2145- e1000_get_speed_and_duplex(hw, &speed, &duplex);
2146- if(speed != SPEED_1000) {
3022+ ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
3023+ if (ret_val) {
3024+ DEBUGOUT("Error getting link speed and duplex\n");
3025+ return ret_val;
3026+ }
3027+ if (speed != SPEED_1000) {
21473028 /* If link speed is not set to gigabit speed, we do not need
21483029 * to enable TBI compatibility.
21493030 */
2150- if(hw->tbi_compatibility_on) {
3031+ if (hw->tbi_compatibility_on) {
21513032 /* If we previously were in the mode, turn it off. */
21523033 rctl = E1000_READ_REG(hw, RCTL);
21533034 rctl &= ~E1000_RCTL_SBP;
@@ -2160,7 +3041,7 @@ e1000_check_for_link(struct e1000_hw *hw)
21603041 * packets. Some frames have an additional byte on the end and
21613042 * will look like CRC errors to to the hardware.
21623043 */
2163- if(!hw->tbi_compatibility_on) {
3044+ if (!hw->tbi_compatibility_on) {
21643045 hw->tbi_compatibility_on = TRUE;
21653046 rctl = E1000_READ_REG(hw, RCTL);
21663047 rctl |= E1000_RCTL_SBP;
@@ -2176,16 +3057,16 @@ e1000_check_for_link(struct e1000_hw *hw)
21763057 * auto-negotiation time to complete, in case the cable was just plugged
21773058 * in. The autoneg_failed flag does this.
21783059 */
2179- else if((((hw->media_type == e1000_media_type_fiber) &&
3060+ else if ((((hw->media_type == e1000_media_type_fiber) &&
21803061 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
2181- (hw->media_type == e1000_media_type_internal_serdes)) &&
2182- (!(status & E1000_STATUS_LU)) &&
2183- (!(rxcw & E1000_RXCW_C))) {
2184- if(hw->autoneg_failed == 0) {
3062+ (hw->media_type == e1000_media_type_internal_serdes)) &&
3063+ (!(status & E1000_STATUS_LU)) &&
3064+ (!(rxcw & E1000_RXCW_C))) {
3065+ if (hw->autoneg_failed == 0) {
21853066 hw->autoneg_failed = 1;
21863067 return 0;
21873068 }
2188- DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
3069+ DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
21893070
21903071 /* Disable auto-negotiation in the TXCW register */
21913072 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
@@ -2197,7 +3078,7 @@ e1000_check_for_link(struct e1000_hw *hw)
21973078
21983079 /* Configure Flow Control after forcing link up. */
21993080 ret_val = e1000_config_fc_after_link_up(hw);
2200- if(ret_val) {
3081+ if (ret_val) {
22013082 DEBUGOUT("Error configuring flow control\n");
22023083 return ret_val;
22033084 }
@@ -2207,10 +3088,10 @@ e1000_check_for_link(struct e1000_hw *hw)
22073088 * Device Control register in an attempt to auto-negotiate with our link
22083089 * partner.
22093090 */
2210- else if(((hw->media_type == e1000_media_type_fiber) ||
2211- (hw->media_type == e1000_media_type_internal_serdes)) &&
2212- (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
2213- DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
3091+ else if (((hw->media_type == e1000_media_type_fiber) ||
3092+ (hw->media_type == e1000_media_type_internal_serdes)) &&
3093+ (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3094+ DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
22143095 E1000_WRITE_REG(hw, TXCW, hw->txcw);
22153096 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
22163097
@@ -2219,12 +3100,12 @@ e1000_check_for_link(struct e1000_hw *hw)
22193100 /* If we force link for non-auto-negotiation switch, check link status
22203101 * based on MAC synchronization for internal serdes media type.
22213102 */
2222- else if((hw->media_type == e1000_media_type_internal_serdes) &&
2223- !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
3103+ else if ((hw->media_type == e1000_media_type_internal_serdes) &&
3104+ !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
22243105 /* SYNCH bit and IV bit are sticky. */
2225- udelay(10);
2226- if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
2227- if(!(rxcw & E1000_RXCW_IV)) {
3106+ usec_delay(10);
3107+ if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
3108+ if (!(rxcw & E1000_RXCW_IV)) {
22283109 hw->serdes_link_down = FALSE;
22293110 DEBUGOUT("SERDES: Link is up.\n");
22303111 }
@@ -2233,8 +3114,8 @@ e1000_check_for_link(struct e1000_hw *hw)
22333114 DEBUGOUT("SERDES: Link is down.\n");
22343115 }
22353116 }
2236- if((hw->media_type == e1000_media_type_internal_serdes) &&
2237- (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
3117+ if ((hw->media_type == e1000_media_type_internal_serdes) &&
3118+ (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
22383119 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
22393120 }
22403121 return E1000_SUCCESS;
@@ -2258,12 +3139,12 @@ e1000_get_speed_and_duplex(struct e1000_hw *hw,
22583139
22593140 DEBUGFUNC("e1000_get_speed_and_duplex");
22603141
2261- if(hw->mac_type >= e1000_82543) {
3142+ if (hw->mac_type >= e1000_82543) {
22623143 status = E1000_READ_REG(hw, STATUS);
2263- if(status & E1000_STATUS_SPEED_1000) {
3144+ if (status & E1000_STATUS_SPEED_1000) {
22643145 *speed = SPEED_1000;
22653146 DEBUGOUT("1000 Mbs, ");
2266- } else if(status & E1000_STATUS_SPEED_100) {
3147+ } else if (status & E1000_STATUS_SPEED_100) {
22673148 *speed = SPEED_100;
22683149 DEBUGOUT("100 Mbs, ");
22693150 } else {
@@ -2271,15 +3152,15 @@ e1000_get_speed_and_duplex(struct e1000_hw *hw,
22713152 DEBUGOUT("10 Mbs, ");
22723153 }
22733154
2274- if(status & E1000_STATUS_FD) {
3155+ if (status & E1000_STATUS_FD) {
22753156 *duplex = FULL_DUPLEX;
2276- DEBUGOUT("Full Duplex\r\n");
3157+ DEBUGOUT("Full Duplex\n");
22773158 } else {
22783159 *duplex = HALF_DUPLEX;
2279- DEBUGOUT(" Half Duplex\r\n");
3160+ DEBUGOUT(" Half Duplex\n");
22803161 }
22813162 } else {
2282- DEBUGOUT("1000 Mbs, Full Duplex\r\n");
3163+ DEBUGOUT("1000 Mbs, Full Duplex\n");
22833164 *speed = SPEED_1000;
22843165 *duplex = FULL_DUPLEX;
22853166 }
@@ -2288,23 +3169,39 @@ e1000_get_speed_and_duplex(struct e1000_hw *hw,
22883169 * if it is operating at half duplex. Here we set the duplex settings to
22893170 * match the duplex in the link partner's capabilities.
22903171 */
2291- if(hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3172+ if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
22923173 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
2293- if(ret_val)
3174+ if (ret_val)
22943175 return ret_val;
22953176
2296- if(!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3177+ if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
22973178 *duplex = HALF_DUPLEX;
22983179 else {
22993180 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
2300- if(ret_val)
3181+ if (ret_val)
23013182 return ret_val;
2302- if((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
3183+ if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
23033184 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
23043185 *duplex = HALF_DUPLEX;
23053186 }
23063187 }
23073188
3189+ if ((hw->mac_type == e1000_80003es2lan) &&
3190+ (hw->media_type == e1000_media_type_copper)) {
3191+ if (*speed == SPEED_1000)
3192+ ret_val = e1000_configure_kmrn_for_1000(hw);
3193+ else
3194+ ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3195+ if (ret_val)
3196+ return ret_val;
3197+ }
3198+
3199+ if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
3200+ ret_val = e1000_kumeran_lock_loss_workaround(hw);
3201+ if (ret_val)
3202+ return ret_val;
3203+ }
3204+
23083205 return E1000_SUCCESS;
23093206 }
23103207
@@ -2313,7 +3210,7 @@ e1000_get_speed_and_duplex(struct e1000_hw *hw,
23133210 *
23143211 * hw - Struct containing variables accessed by shared code
23153212 ******************************************************************************/
2316-int32_t
3213+static int32_t
23173214 e1000_wait_autoneg(struct e1000_hw *hw)
23183215 {
23193216 int32_t ret_val;
@@ -2324,17 +3221,17 @@ e1000_wait_autoneg(struct e1000_hw *hw)
23243221 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
23253222
23263223 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2327- for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
3224+ for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
23283225 /* Read the MII Status Register and wait for Auto-Neg
23293226 * Complete bit to be set.
23303227 */
23313228 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2332- if(ret_val)
3229+ if (ret_val)
23333230 return ret_val;
23343231 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2335- if(ret_val)
3232+ if (ret_val)
23363233 return ret_val;
2337- if(phy_data & MII_SR_AUTONEG_COMPLETE) {
3234+ if (phy_data & MII_SR_AUTONEG_COMPLETE) {
23383235 return E1000_SUCCESS;
23393236 }
23403237 msec_delay(100);
@@ -2357,7 +3254,7 @@ e1000_raise_mdi_clk(struct e1000_hw *hw,
23573254 */
23583255 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
23593256 E1000_WRITE_FLUSH(hw);
2360- udelay(10);
3257+ usec_delay(10);
23613258 }
23623259
23633260 /******************************************************************************
@@ -2375,7 +3272,7 @@ e1000_lower_mdi_clk(struct e1000_hw *hw,
23753272 */
23763273 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
23773274 E1000_WRITE_FLUSH(hw);
2378- udelay(10);
3275+ usec_delay(10);
23793276 }
23803277
23813278 /******************************************************************************
@@ -2407,19 +3304,21 @@ e1000_shift_out_mdi_bits(struct e1000_hw *hw,
24073304 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
24083305 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
24093306
2410- while(mask) {
3307+ while (mask) {
24113308 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
24123309 * then raising and lowering the Management Data Clock. A "0" is
24133310 * shifted out to the PHY by setting the MDIO bit to "0" and then
24143311 * raising and lowering the clock.
24153312 */
2416- if(data & mask) ctrl |= E1000_CTRL_MDIO;
2417- else ctrl &= ~E1000_CTRL_MDIO;
3313+ if (data & mask)
3314+ ctrl |= E1000_CTRL_MDIO;
3315+ else
3316+ ctrl &= ~E1000_CTRL_MDIO;
24183317
24193318 E1000_WRITE_REG(hw, CTRL, ctrl);
24203319 E1000_WRITE_FLUSH(hw);
24213320
2422- udelay(10);
3321+ usec_delay(10);
24233322
24243323 e1000_raise_mdi_clk(hw, &ctrl);
24253324 e1000_lower_mdi_clk(hw, &ctrl);
@@ -2465,12 +3364,13 @@ e1000_shift_in_mdi_bits(struct e1000_hw *hw)
24653364 e1000_raise_mdi_clk(hw, &ctrl);
24663365 e1000_lower_mdi_clk(hw, &ctrl);
24673366
2468- for(data = 0, i = 0; i < 16; i++) {
3367+ for (data = 0, i = 0; i < 16; i++) {
24693368 data = data << 1;
24703369 e1000_raise_mdi_clk(hw, &ctrl);
24713370 ctrl = E1000_READ_REG(hw, CTRL);
24723371 /* Check to see if we shifted in a "1". */
2473- if(ctrl & E1000_CTRL_MDIO) data |= 1;
3372+ if (ctrl & E1000_CTRL_MDIO)
3373+ data |= 1;
24743374 e1000_lower_mdi_clk(hw, &ctrl);
24753375 }
24763376
@@ -2480,6 +3380,80 @@ e1000_shift_in_mdi_bits(struct e1000_hw *hw)
24803380 return data;
24813381 }
24823382
3383+static int32_t
3384+e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
3385+{
3386+ uint32_t swfw_sync = 0;
3387+ uint32_t swmask = mask;
3388+ uint32_t fwmask = mask << 16;
3389+ int32_t timeout = 200;
3390+
3391+ DEBUGFUNC("e1000_swfw_sync_acquire");
3392+
3393+ if (hw->swfwhw_semaphore_present)
3394+ return e1000_get_software_flag(hw);
3395+
3396+ if (!hw->swfw_sync_present)
3397+ return e1000_get_hw_eeprom_semaphore(hw);
3398+
3399+ while (timeout) {
3400+ if (e1000_get_hw_eeprom_semaphore(hw))
3401+ return -E1000_ERR_SWFW_SYNC;
3402+
3403+ swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3404+ if (!(swfw_sync & (fwmask | swmask))) {
3405+ break;
3406+ }
3407+
3408+ /* firmware currently using resource (fwmask) */
3409+ /* or other software thread currently using resource (swmask) */
3410+ e1000_put_hw_eeprom_semaphore(hw);
3411+ msec_delay_irq(5);
3412+ timeout--;
3413+ }
3414+
3415+ if (!timeout) {
3416+ DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
3417+ return -E1000_ERR_SWFW_SYNC;
3418+ }
3419+
3420+ swfw_sync |= swmask;
3421+ E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3422+
3423+ e1000_put_hw_eeprom_semaphore(hw);
3424+ return E1000_SUCCESS;
3425+}
3426+
3427+static void
3428+e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
3429+{
3430+ uint32_t swfw_sync;
3431+ uint32_t swmask = mask;
3432+
3433+ DEBUGFUNC("e1000_swfw_sync_release");
3434+
3435+ if (hw->swfwhw_semaphore_present) {
3436+ e1000_release_software_flag(hw);
3437+ return;
3438+ }
3439+
3440+ if (!hw->swfw_sync_present) {
3441+ e1000_put_hw_eeprom_semaphore(hw);
3442+ return;
3443+ }
3444+
3445+ /* if (e1000_get_hw_eeprom_semaphore(hw))
3446+ * return -E1000_ERR_SWFW_SYNC; */
3447+ while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
3448+ /* empty */
3449+
3450+ swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3451+ swfw_sync &= ~swmask;
3452+ E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3453+
3454+ e1000_put_hw_eeprom_semaphore(hw);
3455+}
3456+
24833457 /*****************************************************************************
24843458 * Reads the value from a PHY register, if the value is on a specific non zero
24853459 * page, sets the page first.
@@ -2492,28 +3466,61 @@ e1000_read_phy_reg(struct e1000_hw *hw,
24923466 uint16_t *phy_data)
24933467 {
24943468 uint32_t ret_val;
3469+ uint16_t swfw;
24953470
24963471 DEBUGFUNC("e1000_read_phy_reg");
24973472
3473+ if ((hw->mac_type == e1000_80003es2lan) &&
3474+ (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3475+ swfw = E1000_SWFW_PHY1_SM;
3476+ } else {
3477+ swfw = E1000_SWFW_PHY0_SM;
3478+ }
3479+ if (e1000_swfw_sync_acquire(hw, swfw))
3480+ return -E1000_ERR_SWFW_SYNC;
24983481
2499- if(hw->phy_type == e1000_phy_igp &&
3482+ if ((hw->phy_type == e1000_phy_igp ||
3483+ hw->phy_type == e1000_phy_igp_3 ||
3484+ hw->phy_type == e1000_phy_igp_2) &&
25003485 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
25013486 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
25023487 (uint16_t)reg_addr);
2503- if(ret_val) {
3488+ if (ret_val) {
3489+ e1000_swfw_sync_release(hw, swfw);
25043490 return ret_val;
25053491 }
3492+ } else if (hw->phy_type == e1000_phy_gg82563) {
3493+ if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3494+ (hw->mac_type == e1000_80003es2lan)) {
3495+ /* Select Configuration Page */
3496+ if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3497+ ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3498+ (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3499+ } else {
3500+ /* Use Alternative Page Select register to access
3501+ * registers 30 and 31
3502+ */
3503+ ret_val = e1000_write_phy_reg_ex(hw,
3504+ GG82563_PHY_PAGE_SELECT_ALT,
3505+ (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3506+ }
3507+
3508+ if (ret_val) {
3509+ e1000_swfw_sync_release(hw, swfw);
3510+ return ret_val;
3511+ }
3512+ }
25063513 }
25073514
25083515 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
25093516 phy_data);
25103517
3518+ e1000_swfw_sync_release(hw, swfw);
25113519 return ret_val;
25123520 }
25133521
2514-int32_t
2515-e1000_read_phy_reg_ex(struct e1000_hw *hw,
2516- uint32_t reg_addr,
3522+static int32_t
3523+e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
25173524 uint16_t *phy_data)
25183525 {
25193526 uint32_t i;
@@ -2522,12 +3529,12 @@ e1000_read_phy_reg_ex(struct e1000_hw *hw,
25223529
25233530 DEBUGFUNC("e1000_read_phy_reg_ex");
25243531
2525- if(reg_addr > MAX_PHY_REG_ADDRESS) {
3532+ if (reg_addr > MAX_PHY_REG_ADDRESS) {
25263533 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
25273534 return -E1000_ERR_PARAM;
25283535 }
25293536
2530- if(hw->mac_type > e1000_82543) {
3537+ if (hw->mac_type > e1000_82543) {
25313538 /* Set up Op-code, Phy Address, and register address in the MDI
25323539 * Control register. The MAC will take care of interfacing with the
25333540 * PHY to retrieve the desired data.
@@ -2539,16 +3546,16 @@ e1000_read_phy_reg_ex(struct e1000_hw *hw,
25393546 E1000_WRITE_REG(hw, MDIC, mdic);
25403547
25413548 /* Poll the ready bit to see if the MDI read completed */
2542- for(i = 0; i < 64; i++) {
2543- udelay(50);
3549+ for (i = 0; i < 64; i++) {
3550+ usec_delay(50);
25443551 mdic = E1000_READ_REG(hw, MDIC);
2545- if(mdic & E1000_MDIC_READY) break;
3552+ if (mdic & E1000_MDIC_READY) break;
25463553 }
2547- if(!(mdic & E1000_MDIC_READY)) {
3554+ if (!(mdic & E1000_MDIC_READY)) {
25483555 DEBUGOUT("MDI Read did not complete\n");
25493556 return -E1000_ERR_PHY;
25503557 }
2551- if(mdic & E1000_MDIC_ERROR) {
3558+ if (mdic & E1000_MDIC_ERROR) {
25523559 DEBUGOUT("MDI Error\n");
25533560 return -E1000_ERR_PHY;
25543561 }
@@ -2593,34 +3600,66 @@ e1000_read_phy_reg_ex(struct e1000_hw *hw,
25933600 * data - data to write to the PHY
25943601 ******************************************************************************/
25953602 int32_t
2596-e1000_write_phy_reg(struct e1000_hw *hw,
2597- uint32_t reg_addr,
3603+e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
25983604 uint16_t phy_data)
25993605 {
26003606 uint32_t ret_val;
3607+ uint16_t swfw;
26013608
26023609 DEBUGFUNC("e1000_write_phy_reg");
26033610
3611+ if ((hw->mac_type == e1000_80003es2lan) &&
3612+ (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3613+ swfw = E1000_SWFW_PHY1_SM;
3614+ } else {
3615+ swfw = E1000_SWFW_PHY0_SM;
3616+ }
3617+ if (e1000_swfw_sync_acquire(hw, swfw))
3618+ return -E1000_ERR_SWFW_SYNC;
26043619
2605- if(hw->phy_type == e1000_phy_igp &&
3620+ if ((hw->phy_type == e1000_phy_igp ||
3621+ hw->phy_type == e1000_phy_igp_3 ||
3622+ hw->phy_type == e1000_phy_igp_2) &&
26063623 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
26073624 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
26083625 (uint16_t)reg_addr);
2609- if(ret_val) {
3626+ if (ret_val) {
3627+ e1000_swfw_sync_release(hw, swfw);
26103628 return ret_val;
26113629 }
3630+ } else if (hw->phy_type == e1000_phy_gg82563) {
3631+ if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3632+ (hw->mac_type == e1000_80003es2lan)) {
3633+ /* Select Configuration Page */
3634+ if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3635+ ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3636+ (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3637+ } else {
3638+ /* Use Alternative Page Select register to access
3639+ * registers 30 and 31
3640+ */
3641+ ret_val = e1000_write_phy_reg_ex(hw,
3642+ GG82563_PHY_PAGE_SELECT_ALT,
3643+ (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3644+ }
3645+
3646+ if (ret_val) {
3647+ e1000_swfw_sync_release(hw, swfw);
3648+ return ret_val;
3649+ }
3650+ }
26123651 }
26133652
26143653 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
26153654 phy_data);
26163655
3656+ e1000_swfw_sync_release(hw, swfw);
26173657 return ret_val;
26183658 }
26193659
2620-int32_t
2621-e1000_write_phy_reg_ex(struct e1000_hw *hw,
2622- uint32_t reg_addr,
2623- uint16_t phy_data)
3660+static int32_t
3661+e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
3662+ uint16_t phy_data)
26243663 {
26253664 uint32_t i;
26263665 uint32_t mdic = 0;
@@ -2628,12 +3667,12 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw,
26283667
26293668 DEBUGFUNC("e1000_write_phy_reg_ex");
26303669
2631- if(reg_addr > MAX_PHY_REG_ADDRESS) {
3670+ if (reg_addr > MAX_PHY_REG_ADDRESS) {
26323671 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
26333672 return -E1000_ERR_PARAM;
26343673 }
26353674
2636- if(hw->mac_type > e1000_82543) {
3675+ if (hw->mac_type > e1000_82543) {
26373676 /* Set up Op-code, Phy Address, register address, and data intended
26383677 * for the PHY register in the MDI Control register. The MAC will take
26393678 * care of interfacing with the PHY to send the desired data.
@@ -2646,12 +3685,12 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw,
26463685 E1000_WRITE_REG(hw, MDIC, mdic);
26473686
26483687 /* Poll the ready bit to see if the MDI read completed */
2649- for(i = 0; i < 640; i++) {
2650- udelay(5);
3688+ for (i = 0; i < 641; i++) {
3689+ usec_delay(5);
26513690 mdic = E1000_READ_REG(hw, MDIC);
2652- if(mdic & E1000_MDIC_READY) break;
3691+ if (mdic & E1000_MDIC_READY) break;
26533692 }
2654- if(!(mdic & E1000_MDIC_READY)) {
3693+ if (!(mdic & E1000_MDIC_READY)) {
26553694 DEBUGOUT("MDI Write did not complete\n");
26563695 return -E1000_ERR_PHY;
26573696 }
@@ -2680,31 +3719,122 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw,
26803719 return E1000_SUCCESS;
26813720 }
26823721
3722+static int32_t
3723+e1000_read_kmrn_reg(struct e1000_hw *hw,
3724+ uint32_t reg_addr,
3725+ uint16_t *data)
3726+{
3727+ uint32_t reg_val;
3728+ uint16_t swfw;
3729+ DEBUGFUNC("e1000_read_kmrn_reg");
3730+
3731+ if ((hw->mac_type == e1000_80003es2lan) &&
3732+ (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3733+ swfw = E1000_SWFW_PHY1_SM;
3734+ } else {
3735+ swfw = E1000_SWFW_PHY0_SM;
3736+ }
3737+ if (e1000_swfw_sync_acquire(hw, swfw))
3738+ return -E1000_ERR_SWFW_SYNC;
3739+
3740+ /* Write register address */
3741+ reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3742+ E1000_KUMCTRLSTA_OFFSET) |
3743+ E1000_KUMCTRLSTA_REN;
3744+ E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3745+ usec_delay(2);
3746+
3747+ /* Read the data returned */
3748+ reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
3749+ *data = (uint16_t)reg_val;
3750+
3751+ e1000_swfw_sync_release(hw, swfw);
3752+ return E1000_SUCCESS;
3753+}
3754+
3755+static int32_t
3756+e1000_write_kmrn_reg(struct e1000_hw *hw,
3757+ uint32_t reg_addr,
3758+ uint16_t data)
3759+{
3760+ uint32_t reg_val;
3761+ uint16_t swfw;
3762+ DEBUGFUNC("e1000_write_kmrn_reg");
3763+
3764+ if ((hw->mac_type == e1000_80003es2lan) &&
3765+ (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3766+ swfw = E1000_SWFW_PHY1_SM;
3767+ } else {
3768+ swfw = E1000_SWFW_PHY0_SM;
3769+ }
3770+ if (e1000_swfw_sync_acquire(hw, swfw))
3771+ return -E1000_ERR_SWFW_SYNC;
3772+
3773+ reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3774+ E1000_KUMCTRLSTA_OFFSET) | data;
3775+ E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3776+ usec_delay(2);
3777+
3778+ e1000_swfw_sync_release(hw, swfw);
3779+ return E1000_SUCCESS;
3780+}
3781+
26833782 /******************************************************************************
26843783 * Returns the PHY to the power-on reset state
26853784 *
26863785 * hw - Struct containing variables accessed by shared code
26873786 ******************************************************************************/
2688-void
3787+int32_t
26893788 e1000_phy_hw_reset(struct e1000_hw *hw)
26903789 {
26913790 uint32_t ctrl, ctrl_ext;
26923791 uint32_t led_ctrl;
3792+ int32_t ret_val;
3793+ uint16_t swfw;
26933794
26943795 DEBUGFUNC("e1000_phy_hw_reset");
26953796
3797+ /* In the case of the phy reset being blocked, it's not an error, we
3798+ * simply return success without performing the reset. */
3799+ ret_val = e1000_check_phy_reset_block(hw);
3800+ if (ret_val)
3801+ return E1000_SUCCESS;
3802+
26963803 DEBUGOUT("Resetting Phy...\n");
26973804
2698- if(hw->mac_type > e1000_82543) {
3805+ if (hw->mac_type > e1000_82543) {
3806+ if ((hw->mac_type == e1000_80003es2lan) &&
3807+ (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3808+ swfw = E1000_SWFW_PHY1_SM;
3809+ } else {
3810+ swfw = E1000_SWFW_PHY0_SM;
3811+ }
3812+ if (e1000_swfw_sync_acquire(hw, swfw)) {
3813+ DEBUGOUT("Unable to acquire swfw sync\n");
3814+ return -E1000_ERR_SWFW_SYNC;
3815+ }
26993816 /* Read the device control register and assert the E1000_CTRL_PHY_RST
27003817 * bit. Then, take it out of reset.
3818+ * For pre-e1000_82571 hardware, we delay for 10ms between the assert
3819+ * and deassert. For e1000_82571 hardware and later, we instead delay
3820+ * for 50us between and 10ms after the deassertion.
27013821 */
27023822 ctrl = E1000_READ_REG(hw, CTRL);
27033823 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
27043824 E1000_WRITE_FLUSH(hw);
2705- msec_delay(10);
3825+
3826+ if (hw->mac_type < e1000_82571)
3827+ msec_delay(10);
3828+ else
3829+ usec_delay(100);
3830+
27063831 E1000_WRITE_REG(hw, CTRL, ctrl);
27073832 E1000_WRITE_FLUSH(hw);
3833+
3834+ if (hw->mac_type >= e1000_82571)
3835+ msec_delay_irq(10);
3836+
3837+ e1000_swfw_sync_release(hw, swfw);
27083838 } else {
27093839 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
27103840 * bit to put the PHY into reset. Then, take it out of reset.
@@ -2719,15 +3849,26 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
27193849 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
27203850 E1000_WRITE_FLUSH(hw);
27213851 }
2722- udelay(150);
3852+ usec_delay(150);
27233853
2724- if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
3854+ if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
27253855 /* Configure activity LED after PHY reset */
27263856 led_ctrl = E1000_READ_REG(hw, LEDCTL);
27273857 led_ctrl &= IGP_ACTIVITY_LED_MASK;
27283858 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
27293859 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
27303860 }
3861+
3862+ /* Wait for FW to finish PHY configuration. */
3863+ ret_val = e1000_get_phy_cfg_done(hw);
3864+ if (ret_val != E1000_SUCCESS)
3865+ return ret_val;
3866+ e1000_release_software_semaphore(hw);
3867+
3868+ if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3))
3869+ ret_val = e1000_init_lcd_from_nvm(hw);
3870+
3871+ return ret_val;
27313872 }
27323873
27333874 /******************************************************************************
@@ -2745,31 +3886,157 @@ e1000_phy_reset(struct e1000_hw *hw)
27453886
27463887 DEBUGFUNC("e1000_phy_reset");
27473888
2748- if(hw->mac_type != e1000_82541_rev_2) {
3889+ /* In the case of the phy reset being blocked, it's not an error, we
3890+ * simply return success without performing the reset. */
3891+ ret_val = e1000_check_phy_reset_block(hw);
3892+ if (ret_val)
3893+ return E1000_SUCCESS;
3894+
3895+ switch (hw->phy_type) {
3896+ case e1000_phy_igp:
3897+ case e1000_phy_igp_2:
3898+ case e1000_phy_igp_3:
3899+ case e1000_phy_ife:
3900+ ret_val = e1000_phy_hw_reset(hw);
3901+ if (ret_val)
3902+ return ret_val;
3903+ break;
3904+ default:
27493905 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2750- if(ret_val)
3906+ if (ret_val)
27513907 return ret_val;
27523908
27533909 phy_data |= MII_CR_RESET;
27543910 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
2755- if(ret_val)
3911+ if (ret_val)
27563912 return ret_val;
27573913
2758- udelay(1);
2759- } else e1000_phy_hw_reset(hw);
3914+ usec_delay(1);
3915+ break;
3916+ }
27603917
2761- if(hw->phy_type == e1000_phy_igp)
3918+ if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
27623919 e1000_phy_init_script(hw);
27633920
27643921 return E1000_SUCCESS;
27653922 }
27663923
27673924 /******************************************************************************
3925+* Work-around for 82566 power-down: on D3 entry-
3926+* 1) disable gigabit link
3927+* 2) write VR power-down enable
3928+* 3) read it back
3929+* if successful continue, else issue LCD reset and repeat
3930+*
3931+* hw - struct containing variables accessed by shared code
3932+******************************************************************************/
3933+void
3934+e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3935+{
3936+ int32_t reg;
3937+ uint16_t phy_data;
3938+ int32_t retry = 0;
3939+
3940+ DEBUGFUNC("e1000_phy_powerdown_workaround");
3941+
3942+ if (hw->phy_type != e1000_phy_igp_3)
3943+ return;
3944+
3945+ do {
3946+ /* Disable link */
3947+ reg = E1000_READ_REG(hw, PHY_CTRL);
3948+ E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3949+ E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3950+
3951+ /* Write VR power-down enable - bits 9:8 should be 10b */
3952+ e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3953+ phy_data |= (1 << 9);
3954+ phy_data &= ~(1 << 8);
3955+ e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data);
3956+
3957+ /* Read it back and test */
3958+ e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3959+ if (((phy_data & IGP3_VR_CTRL_MODE_MASK) == IGP3_VR_CTRL_MODE_SHUT) || retry)
3960+ break;
3961+
3962+ /* Issue PHY reset and repeat at most one more time */
3963+ reg = E1000_READ_REG(hw, CTRL);
3964+ E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST);
3965+ retry++;
3966+ } while (retry);
3967+
3968+ return;
3969+
3970+}
3971+
3972+/******************************************************************************
3973+* Work-around for 82566 Kumeran PCS lock loss:
3974+* On link status change (i.e. PCI reset, speed change) and link is up and
3975+* speed is gigabit-
3976+* 0) if workaround is optionally disabled do nothing
3977+* 1) wait 1ms for Kumeran link to come up
3978+* 2) check Kumeran Diagnostic register PCS lock loss bit
3979+* 3) if not set the link is locked (all is good), otherwise...
3980+* 4) reset the PHY
3981+* 5) repeat up to 10 times
3982+* Note: this is only called for IGP3 copper when speed is 1gb.
3983+*
3984+* hw - struct containing variables accessed by shared code
3985+******************************************************************************/
3986+static int32_t
3987+e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
3988+{
3989+ int32_t ret_val;
3990+ int32_t reg;
3991+ int32_t cnt;
3992+ uint16_t phy_data;
3993+
3994+ if (hw->kmrn_lock_loss_workaround_disabled)
3995+ return E1000_SUCCESS;
3996+
3997+ /* Make sure link is up before proceeding. If not just return.
3998+ * Attempting this while link is negotiating fouled up link
3999+ * stability */
4000+ ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4001+ ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4002+
4003+ if (phy_data & MII_SR_LINK_STATUS) {
4004+ for (cnt = 0; cnt < 10; cnt++) {
4005+ /* read once to clear */
4006+ ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
4007+ if (ret_val)
4008+ return ret_val;
4009+ /* and again to get new status */
4010+ ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
4011+ if (ret_val)
4012+ return ret_val;
4013+
4014+ /* check for PCS lock */
4015+ if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4016+ return E1000_SUCCESS;
4017+
4018+ /* Issue PHY reset */
4019+ e1000_phy_hw_reset(hw);
4020+ msec_delay_irq(5);
4021+ }
4022+ /* Disable GigE link negotiation */
4023+ reg = E1000_READ_REG(hw, PHY_CTRL);
4024+ E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
4025+ E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4026+
4027+ /* unable to acquire PCS lock */
4028+ return E1000_ERR_PHY;
4029+ }
4030+
4031+ return E1000_SUCCESS;
4032+}
4033+
4034+/******************************************************************************
27684035 * Probes the expected PHY address for known PHY IDs
27694036 *
27704037 * hw - Struct containing variables accessed by shared code
27714038 ******************************************************************************/
2772-int32_t
4039+static int32_t
27734040 e1000_detect_gig_phy(struct e1000_hw *hw)
27744041 {
27754042 int32_t phy_init_status, ret_val;
@@ -2778,39 +4045,73 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
27784045
27794046 DEBUGFUNC("e1000_detect_gig_phy");
27804047
4048+ if (hw->phy_id != 0)
4049+ return E1000_SUCCESS;
4050+
4051+ /* The 82571 firmware may still be configuring the PHY. In this
4052+ * case, we cannot access the PHY until the configuration is done. So
4053+ * we explicitly set the PHY values. */
4054+ if (hw->mac_type == e1000_82571 ||
4055+ hw->mac_type == e1000_82572) {
4056+ hw->phy_id = IGP01E1000_I_PHY_ID;
4057+ hw->phy_type = e1000_phy_igp_2;
4058+ return E1000_SUCCESS;
4059+ }
4060+
4061+ /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work-
4062+ * around that forces PHY page 0 to be set or the reads fail. The rest of
4063+ * the code in this routine uses e1000_read_phy_reg to read the PHY ID.
4064+ * So for ESB-2 we need to have this set so our reads won't fail. If the
4065+ * attached PHY is not a e1000_phy_gg82563, the routines below will figure
4066+ * this out as well. */
4067+ if (hw->mac_type == e1000_80003es2lan)
4068+ hw->phy_type = e1000_phy_gg82563;
4069+
27814070 /* Read the PHY ID Registers to identify which PHY is onboard. */
27824071 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
2783- if(ret_val)
4072+ if (ret_val)
27844073 return ret_val;
27854074
27864075 hw->phy_id = (uint32_t) (phy_id_high << 16);
2787- udelay(20);
4076+ usec_delay(20);
27884077 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
2789- if(ret_val)
4078+ if (ret_val)
27904079 return ret_val;
27914080
27924081 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
27934082 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
27944083
2795- switch(hw->mac_type) {
4084+ switch (hw->mac_type) {
27964085 case e1000_82543:
2797- if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
4086+ if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
27984087 break;
27994088 case e1000_82544:
2800- if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
4089+ if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
28014090 break;
28024091 case e1000_82540:
28034092 case e1000_82545:
28044093 case e1000_82545_rev_3:
28054094 case e1000_82546:
28064095 case e1000_82546_rev_3:
2807- if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
4096+ if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
28084097 break;
28094098 case e1000_82541:
28104099 case e1000_82541_rev_2:
28114100 case e1000_82547:
28124101 case e1000_82547_rev_2:
2813- if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
4102+ if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
4103+ break;
4104+ case e1000_82573:
4105+ if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
4106+ break;
4107+ case e1000_80003es2lan:
4108+ if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
4109+ break;
4110+ case e1000_ich8lan:
4111+ if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE;
4112+ if (hw->phy_id == IFE_E_PHY_ID) match = TRUE;
4113+ if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE;
4114+ if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE;
28144115 break;
28154116 default:
28164117 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
@@ -2838,14 +4139,16 @@ e1000_phy_reset_dsp(struct e1000_hw *hw)
28384139 DEBUGFUNC("e1000_phy_reset_dsp");
28394140
28404141 do {
2841- ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
2842- if(ret_val) break;
4142+ if (hw->phy_type != e1000_phy_gg82563) {
4143+ ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
4144+ if (ret_val) break;
4145+ }
28434146 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
2844- if(ret_val) break;
4147+ if (ret_val) break;
28454148 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
2846- if(ret_val) break;
4149+ if (ret_val) break;
28474150 ret_val = E1000_SUCCESS;
2848- } while(0);
4151+ } while (0);
28494152
28504153 return ret_val;
28514154 }
@@ -2856,18 +4159,19 @@ e1000_phy_reset_dsp(struct e1000_hw *hw)
28564159 * hw - Struct containing variables accessed by shared code
28574160 * phy_info - PHY information structure
28584161 ******************************************************************************/
2859-int32_t
4162+static int32_t
28604163 e1000_phy_igp_get_info(struct e1000_hw *hw,
28614164 struct e1000_phy_info *phy_info)
28624165 {
28634166 int32_t ret_val;
2864- uint16_t phy_data, polarity, min_length, max_length, average;
4167+ uint16_t phy_data, min_length, max_length, average;
4168+ e1000_rev_polarity polarity;
28654169
28664170 DEBUGFUNC("e1000_phy_igp_get_info");
28674171
28684172 /* The downshift status is checked only once, after link is established,
28694173 * and it stored in the hw->speed_downgraded parameter. */
2870- phy_info->downshift = hw->speed_downgraded;
4174+ phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
28714175
28724176 /* IGP01E1000 does not need to support it. */
28734177 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
@@ -2877,45 +4181,47 @@ e1000_phy_igp_get_info(struct e1000_hw *hw,
28774181
28784182 /* Check polarity status */
28794183 ret_val = e1000_check_polarity(hw, &polarity);
2880- if(ret_val)
4184+ if (ret_val)
28814185 return ret_val;
28824186
28834187 phy_info->cable_polarity = polarity;
28844188
28854189 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
2886- if(ret_val)
4190+ if (ret_val)
28874191 return ret_val;
28884192
2889- phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >>
2890- IGP01E1000_PSSR_MDIX_SHIFT;
4193+ phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >>
4194+ IGP01E1000_PSSR_MDIX_SHIFT);
28914195
2892- if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
4196+ if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
28934197 IGP01E1000_PSSR_SPEED_1000MBPS) {
28944198 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
28954199 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
2896- if(ret_val)
4200+ if (ret_val)
28974201 return ret_val;
28984202
2899- phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
2900- SR_1000T_LOCAL_RX_STATUS_SHIFT;
2901- phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
2902- SR_1000T_REMOTE_RX_STATUS_SHIFT;
4203+ phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4204+ SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4205+ e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4206+ phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4207+ SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4208+ e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
29034209
29044210 /* Get cable length */
29054211 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
2906- if(ret_val)
4212+ if (ret_val)
29074213 return ret_val;
29084214
2909- /* transalte to old method */
4215+ /* Translate to old method */
29104216 average = (max_length + min_length) / 2;
29114217
2912- if(average <= e1000_igp_cable_length_50)
4218+ if (average <= e1000_igp_cable_length_50)
29134219 phy_info->cable_length = e1000_cable_length_50;
2914- else if(average <= e1000_igp_cable_length_80)
4220+ else if (average <= e1000_igp_cable_length_80)
29154221 phy_info->cable_length = e1000_cable_length_50_80;
2916- else if(average <= e1000_igp_cable_length_110)
4222+ else if (average <= e1000_igp_cable_length_110)
29174223 phy_info->cable_length = e1000_cable_length_80_110;
2918- else if(average <= e1000_igp_cable_length_140)
4224+ else if (average <= e1000_igp_cable_length_140)
29194225 phy_info->cable_length = e1000_cable_length_110_140;
29204226 else
29214227 phy_info->cable_length = e1000_cable_length_140;
@@ -2925,64 +4231,129 @@ e1000_phy_igp_get_info(struct e1000_hw *hw,
29254231 }
29264232
29274233 /******************************************************************************
4234+* Get PHY information from various PHY registers for ife PHY only.
4235+*
4236+* hw - Struct containing variables accessed by shared code
4237+* phy_info - PHY information structure
4238+******************************************************************************/
4239+static int32_t
4240+e1000_phy_ife_get_info(struct e1000_hw *hw,
4241+ struct e1000_phy_info *phy_info)
4242+{
4243+ int32_t ret_val;
4244+ uint16_t phy_data;
4245+ e1000_rev_polarity polarity;
4246+
4247+ DEBUGFUNC("e1000_phy_ife_get_info");
4248+
4249+ phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4250+ phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4251+
4252+ ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
4253+ if (ret_val)
4254+ return ret_val;
4255+ phy_info->polarity_correction =
4256+ ((phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >>
4257+ IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT) ?
4258+ e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
4259+
4260+ if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) {
4261+ ret_val = e1000_check_polarity(hw, &polarity);
4262+ if (ret_val)
4263+ return ret_val;
4264+ } else {
4265+ /* Polarity is forced. */
4266+ polarity = ((phy_data & IFE_PSC_FORCE_POLARITY) >>
4267+ IFE_PSC_FORCE_POLARITY_SHIFT) ?
4268+ e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
4269+ }
4270+ phy_info->cable_polarity = polarity;
4271+
4272+ ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
4273+ if (ret_val)
4274+ return ret_val;
4275+
4276+ phy_info->mdix_mode = (e1000_auto_x_mode)
4277+ ((phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >>
4278+ IFE_PMC_MDIX_MODE_SHIFT);
4279+
4280+ return E1000_SUCCESS;
4281+}
4282+
4283+/******************************************************************************
29284284 * Get PHY information from various PHY registers fot m88 PHY only.
29294285 *
29304286 * hw - Struct containing variables accessed by shared code
29314287 * phy_info - PHY information structure
29324288 ******************************************************************************/
2933-int32_t
4289+static int32_t
29344290 e1000_phy_m88_get_info(struct e1000_hw *hw,
29354291 struct e1000_phy_info *phy_info)
29364292 {
29374293 int32_t ret_val;
2938- uint16_t phy_data, polarity;
4294+ uint16_t phy_data;
4295+ e1000_rev_polarity polarity;
29394296
29404297 DEBUGFUNC("e1000_phy_m88_get_info");
29414298
29424299 /* The downshift status is checked only once, after link is established,
29434300 * and it stored in the hw->speed_downgraded parameter. */
2944- phy_info->downshift = hw->speed_downgraded;
4301+ phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
29454302
29464303 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2947- if(ret_val)
4304+ if (ret_val)
29484305 return ret_val;
29494306
29504307 phy_info->extended_10bt_distance =
2951- (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
2952- M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT;
4308+ ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
4309+ M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
4310+ e1000_10bt_ext_dist_enable_lower : e1000_10bt_ext_dist_enable_normal;
4311+
29534312 phy_info->polarity_correction =
2954- (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
2955- M88E1000_PSCR_POLARITY_REVERSAL_SHIFT;
4313+ ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
4314+ M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
4315+ e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
29564316
29574317 /* Check polarity status */
29584318 ret_val = e1000_check_polarity(hw, &polarity);
2959- if(ret_val)
2960- return ret_val;
4319+ if (ret_val)
4320+ return ret_val;
29614321 phy_info->cable_polarity = polarity;
29624322
29634323 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2964- if(ret_val)
4324+ if (ret_val)
29654325 return ret_val;
29664326
2967- phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
2968- M88E1000_PSSR_MDIX_SHIFT;
4327+ phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >>
4328+ M88E1000_PSSR_MDIX_SHIFT);
29694329
29704330 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
29714331 /* Cable Length Estimation and Local/Remote Receiver Information
29724332 * are only valid at 1000 Mbps.
29734333 */
2974- phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2975- M88E1000_PSSR_CABLE_LENGTH_SHIFT);
4334+ if (hw->phy_type != e1000_phy_gg82563) {
4335+ phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4336+ M88E1000_PSSR_CABLE_LENGTH_SHIFT);
4337+ } else {
4338+ ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
4339+ &phy_data);
4340+ if (ret_val)
4341+ return ret_val;
4342+
4343+ phy_info->cable_length = (e1000_cable_length)(phy_data & GG82563_DSPD_CABLE_LENGTH);
4344+ }
29764345
29774346 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
2978- if(ret_val)
4347+ if (ret_val)
29794348 return ret_val;
29804349
2981- phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
2982- SR_1000T_LOCAL_RX_STATUS_SHIFT;
4350+ phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4351+ SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4352+ e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4353+ phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4354+ SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4355+ e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
29834356
2984- phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
2985- SR_1000T_REMOTE_RX_STATUS_SHIFT;
29864357 }
29874358
29884359 return E1000_SUCCESS;
@@ -3012,26 +4383,30 @@ e1000_phy_get_info(struct e1000_hw *hw,
30124383 phy_info->local_rx = e1000_1000t_rx_status_undefined;
30134384 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
30144385
3015- if(hw->media_type != e1000_media_type_copper) {
4386+ if (hw->media_type != e1000_media_type_copper) {
30164387 DEBUGOUT("PHY info is only valid for copper media\n");
30174388 return -E1000_ERR_CONFIG;
30184389 }
30194390
30204391 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3021- if(ret_val)
4392+ if (ret_val)
30224393 return ret_val;
30234394
30244395 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3025- if(ret_val)
4396+ if (ret_val)
30264397 return ret_val;
30274398
3028- if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
4399+ if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
30294400 DEBUGOUT("PHY info is only valid if link is up\n");
30304401 return -E1000_ERR_CONFIG;
30314402 }
30324403
3033- if(hw->phy_type == e1000_phy_igp)
4404+ if (hw->phy_type == e1000_phy_igp ||
4405+ hw->phy_type == e1000_phy_igp_3 ||
4406+ hw->phy_type == e1000_phy_igp_2)
30344407 return e1000_phy_igp_get_info(hw, phy_info);
4408+ else if (hw->phy_type == e1000_phy_ife)
4409+ return e1000_phy_ife_get_info(hw, phy_info);
30354410 else
30364411 return e1000_phy_m88_get_info(hw, phy_info);
30374412 }
@@ -3041,7 +4416,7 @@ e1000_validate_mdi_setting(struct e1000_hw *hw)
30414416 {
30424417 DEBUGFUNC("e1000_validate_mdi_settings");
30434418
3044- if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
4419+ if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
30454420 DEBUGOUT("Invalid MDI setting detected\n");
30464421 hw->mdix = 1;
30474422 return -E1000_ERR_CONFIG;
@@ -3052,15 +4427,17 @@ e1000_validate_mdi_setting(struct e1000_hw *hw)
30524427
30534428 /******************************************************************************
30544429 * Sets up eeprom variables in the hw struct. Must be called after mac_type
3055- * is configured.
4430+ * is configured. Additionally, if this is ICH8, the flash controller GbE
4431+ * registers must be mapped, or this will crash.
30564432 *
30574433 * hw - Struct containing variables accessed by shared code
30584434 *****************************************************************************/
3059-void
4435+int32_t
30604436 e1000_init_eeprom_params(struct e1000_hw *hw)
30614437 {
30624438 struct e1000_eeprom_info *eeprom = &hw->eeprom;
30634439 uint32_t eecd = E1000_READ_REG(hw, EECD);
4440+ int32_t ret_val = E1000_SUCCESS;
30644441 uint16_t eeprom_size;
30654442
30664443 DEBUGFUNC("e1000_init_eeprom_params");
@@ -3075,6 +4452,8 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
30754452 eeprom->opcode_bits = 3;
30764453 eeprom->address_bits = 6;
30774454 eeprom->delay_usec = 50;
4455+ eeprom->use_eerd = FALSE;
4456+ eeprom->use_eewr = FALSE;
30784457 break;
30794458 case e1000_82540:
30804459 case e1000_82545:
@@ -3084,13 +4463,15 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
30844463 eeprom->type = e1000_eeprom_microwire;
30854464 eeprom->opcode_bits = 3;
30864465 eeprom->delay_usec = 50;
3087- if(eecd & E1000_EECD_SIZE) {
4466+ if (eecd & E1000_EECD_SIZE) {
30884467 eeprom->word_size = 256;
30894468 eeprom->address_bits = 8;
30904469 } else {
30914470 eeprom->word_size = 64;
30924471 eeprom->address_bits = 6;
30934472 }
4473+ eeprom->use_eerd = FALSE;
4474+ eeprom->use_eewr = FALSE;
30944475 break;
30954476 case e1000_82541:
30964477 case e1000_82541_rev_2:
@@ -3119,42 +4500,119 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
31194500 eeprom->address_bits = 6;
31204501 }
31214502 }
4503+ eeprom->use_eerd = FALSE;
4504+ eeprom->use_eewr = FALSE;
31224505 break;
3123- default:
4506+ case e1000_82571:
4507+ case e1000_82572:
4508+ eeprom->type = e1000_eeprom_spi;
4509+ eeprom->opcode_bits = 8;
4510+ eeprom->delay_usec = 1;
4511+ if (eecd & E1000_EECD_ADDR_BITS) {
4512+ eeprom->page_size = 32;
4513+ eeprom->address_bits = 16;
4514+ } else {
4515+ eeprom->page_size = 8;
4516+ eeprom->address_bits = 8;
4517+ }
4518+ eeprom->use_eerd = FALSE;
4519+ eeprom->use_eewr = FALSE;
31244520 break;
3125- }
4521+ case e1000_82573:
4522+ eeprom->type = e1000_eeprom_spi;
4523+ eeprom->opcode_bits = 8;
4524+ eeprom->delay_usec = 1;
4525+ if (eecd & E1000_EECD_ADDR_BITS) {
4526+ eeprom->page_size = 32;
4527+ eeprom->address_bits = 16;
4528+ } else {
4529+ eeprom->page_size = 8;
4530+ eeprom->address_bits = 8;
4531+ }
4532+ eeprom->use_eerd = TRUE;
4533+ eeprom->use_eewr = TRUE;
4534+ if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
4535+ eeprom->type = e1000_eeprom_flash;
4536+ eeprom->word_size = 2048;
4537+
4538+ /* Ensure that the Autonomous FLASH update bit is cleared due to
4539+ * Flash update issue on parts which use a FLASH for NVM. */
4540+ eecd &= ~E1000_EECD_AUPDEN;
4541+ E1000_WRITE_REG(hw, EECD, eecd);
4542+ }
4543+ break;
4544+ case e1000_80003es2lan:
4545+ eeprom->type = e1000_eeprom_spi;
4546+ eeprom->opcode_bits = 8;
4547+ eeprom->delay_usec = 1;
4548+ if (eecd & E1000_EECD_ADDR_BITS) {
4549+ eeprom->page_size = 32;
4550+ eeprom->address_bits = 16;
4551+ } else {
4552+ eeprom->page_size = 8;
4553+ eeprom->address_bits = 8;
4554+ }
4555+ eeprom->use_eerd = TRUE;
4556+ eeprom->use_eewr = FALSE;
4557+ break;
4558+ case e1000_ich8lan:
4559+ {
4560+ int32_t i = 0;
4561+ uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG);
4562+
4563+ eeprom->type = e1000_eeprom_ich8;
4564+ eeprom->use_eerd = FALSE;
4565+ eeprom->use_eewr = FALSE;
4566+ eeprom->word_size = E1000_SHADOW_RAM_WORDS;
4567+
4568+ /* Zero the shadow RAM structure. But don't load it from NVM
4569+ * so as to save time for driver init */
4570+ if (hw->eeprom_shadow_ram != NULL) {
4571+ for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4572+ hw->eeprom_shadow_ram[i].modified = FALSE;
4573+ hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
4574+ }
4575+ }
31264576
3127- if (eeprom->type == e1000_eeprom_spi) {
3128- eeprom->word_size = 64;
3129- if (e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size) == 0) {
3130- eeprom_size &= EEPROM_SIZE_MASK;
4577+ hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
4578+ ICH_FLASH_SECTOR_SIZE;
31314579
3132- switch (eeprom_size) {
3133- case EEPROM_SIZE_16KB:
3134- eeprom->word_size = 8192;
3135- break;
3136- case EEPROM_SIZE_8KB:
3137- eeprom->word_size = 4096;
3138- break;
3139- case EEPROM_SIZE_4KB:
3140- eeprom->word_size = 2048;
3141- break;
3142- case EEPROM_SIZE_2KB:
3143- eeprom->word_size = 1024;
3144- break;
3145- case EEPROM_SIZE_1KB:
3146- eeprom->word_size = 512;
3147- break;
3148- case EEPROM_SIZE_512B:
3149- eeprom->word_size = 256;
3150- break;
3151- case EEPROM_SIZE_128B:
3152- default:
3153- eeprom->word_size = 64;
3154- break;
3155- }
4580+ hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1;
4581+ hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
4582+
4583+ hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
4584+
4585+ hw->flash_bank_size /= 2 * sizeof(uint16_t);
4586+ break;
4587+ }
4588+ default:
4589+ break;
4590+ }
4591+
4592+ if (eeprom->type == e1000_eeprom_spi) {
4593+ /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
4594+ * 32KB (incremented by powers of 2).
4595+ */
4596+ if (hw->mac_type <= e1000_82547_rev_2) {
4597+ /* Set to default value for initial eeprom read. */
4598+ eeprom->word_size = 64;
4599+ ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
4600+ if (ret_val)
4601+ return ret_val;
4602+ eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
4603+ /* 256B eeprom size was not supported in earlier hardware, so we
4604+ * bump eeprom_size up one to ensure that "1" (which maps to 256B)
4605+ * is never the result used in the shifting logic below. */
4606+ if (eeprom_size)
4607+ eeprom_size++;
4608+ } else {
4609+ eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
4610+ E1000_EECD_SIZE_EX_SHIFT);
31564611 }
4612+
4613+ eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
31574614 }
4615+ return ret_val;
31584616 }
31594617
31604618 /******************************************************************************
@@ -3173,7 +4631,7 @@ e1000_raise_ee_clk(struct e1000_hw *hw,
31734631 *eecd = *eecd | E1000_EECD_SK;
31744632 E1000_WRITE_REG(hw, EECD, *eecd);
31754633 E1000_WRITE_FLUSH(hw);
3176- udelay(hw->eeprom.delay_usec);
4634+ usec_delay(hw->eeprom.delay_usec);
31774635 }
31784636
31794637 /******************************************************************************
@@ -3192,7 +4650,7 @@ e1000_lower_ee_clk(struct e1000_hw *hw,
31924650 *eecd = *eecd & ~E1000_EECD_SK;
31934651 E1000_WRITE_REG(hw, EECD, *eecd);
31944652 E1000_WRITE_FLUSH(hw);
3195- udelay(hw->eeprom.delay_usec);
4653+ usec_delay(hw->eeprom.delay_usec);
31964654 }
31974655
31984656 /******************************************************************************
@@ -3230,20 +4688,20 @@ e1000_shift_out_ee_bits(struct e1000_hw *hw,
32304688 */
32314689 eecd &= ~E1000_EECD_DI;
32324690
3233- if(data & mask)
4691+ if (data & mask)
32344692 eecd |= E1000_EECD_DI;
32354693
32364694 E1000_WRITE_REG(hw, EECD, eecd);
32374695 E1000_WRITE_FLUSH(hw);
32384696
3239- udelay(eeprom->delay_usec);
4697+ usec_delay(eeprom->delay_usec);
32404698
32414699 e1000_raise_ee_clk(hw, &eecd);
32424700 e1000_lower_ee_clk(hw, &eecd);
32434701
32444702 mask = mask >> 1;
32454703
3246- } while(mask);
4704+ } while (mask);
32474705
32484706 /* We leave the "DI" bit set to "0" when we leave this routine. */
32494707 eecd &= ~E1000_EECD_DI;
@@ -3275,14 +4733,14 @@ e1000_shift_in_ee_bits(struct e1000_hw *hw,
32754733 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
32764734 data = 0;
32774735
3278- for(i = 0; i < count; i++) {
4736+ for (i = 0; i < count; i++) {
32794737 data = data << 1;
32804738 e1000_raise_ee_clk(hw, &eecd);
32814739
32824740 eecd = E1000_READ_REG(hw, EECD);
32834741
32844742 eecd &= ~(E1000_EECD_DI);
3285- if(eecd & E1000_EECD_DO)
4743+ if (eecd & E1000_EECD_DO)
32864744 data |= 1;
32874745
32884746 e1000_lower_ee_clk(hw, &eecd);
@@ -3307,24 +4765,29 @@ e1000_acquire_eeprom(struct e1000_hw *hw)
33074765
33084766 DEBUGFUNC("e1000_acquire_eeprom");
33094767
4768+ if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
4769+ return -E1000_ERR_SWFW_SYNC;
33104770 eecd = E1000_READ_REG(hw, EECD);
33114771
3312- /* Request EEPROM Access */
3313- if(hw->mac_type > e1000_82544) {
3314- eecd |= E1000_EECD_REQ;
3315- E1000_WRITE_REG(hw, EECD, eecd);
3316- eecd = E1000_READ_REG(hw, EECD);
3317- while((!(eecd & E1000_EECD_GNT)) &&
3318- (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
3319- i++;
3320- udelay(5);
3321- eecd = E1000_READ_REG(hw, EECD);
3322- }
3323- if(!(eecd & E1000_EECD_GNT)) {
3324- eecd &= ~E1000_EECD_REQ;
4772+ if (hw->mac_type != e1000_82573) {
4773+ /* Request EEPROM Access */
4774+ if (hw->mac_type > e1000_82544) {
4775+ eecd |= E1000_EECD_REQ;
33254776 E1000_WRITE_REG(hw, EECD, eecd);
3326- DEBUGOUT("Could not acquire EEPROM grant\n");
3327- return -E1000_ERR_EEPROM;
4777+ eecd = E1000_READ_REG(hw, EECD);
4778+ while ((!(eecd & E1000_EECD_GNT)) &&
4779+ (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
4780+ i++;
4781+ usec_delay(5);
4782+ eecd = E1000_READ_REG(hw, EECD);
4783+ }
4784+ if (!(eecd & E1000_EECD_GNT)) {
4785+ eecd &= ~E1000_EECD_REQ;
4786+ E1000_WRITE_REG(hw, EECD, eecd);
4787+ DEBUGOUT("Could not acquire EEPROM grant\n");
4788+ e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4789+ return -E1000_ERR_EEPROM;
4790+ }
33284791 }
33294792 }
33304793
@@ -3342,7 +4805,7 @@ e1000_acquire_eeprom(struct e1000_hw *hw)
33424805 /* Clear SK and CS */
33434806 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
33444807 E1000_WRITE_REG(hw, EECD, eecd);
3345- udelay(1);
4808+ usec_delay(1);
33464809 }
33474810
33484811 return E1000_SUCCESS;
@@ -3361,39 +4824,39 @@ e1000_standby_eeprom(struct e1000_hw *hw)
33614824
33624825 eecd = E1000_READ_REG(hw, EECD);
33634826
3364- if(eeprom->type == e1000_eeprom_microwire) {
4827+ if (eeprom->type == e1000_eeprom_microwire) {
33654828 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
33664829 E1000_WRITE_REG(hw, EECD, eecd);
33674830 E1000_WRITE_FLUSH(hw);
3368- udelay(eeprom->delay_usec);
4831+ usec_delay(eeprom->delay_usec);
33694832
33704833 /* Clock high */
33714834 eecd |= E1000_EECD_SK;
33724835 E1000_WRITE_REG(hw, EECD, eecd);
33734836 E1000_WRITE_FLUSH(hw);
3374- udelay(eeprom->delay_usec);
4837+ usec_delay(eeprom->delay_usec);
33754838
33764839 /* Select EEPROM */
33774840 eecd |= E1000_EECD_CS;
33784841 E1000_WRITE_REG(hw, EECD, eecd);
33794842 E1000_WRITE_FLUSH(hw);
3380- udelay(eeprom->delay_usec);
4843+ usec_delay(eeprom->delay_usec);
33814844
33824845 /* Clock low */
33834846 eecd &= ~E1000_EECD_SK;
33844847 E1000_WRITE_REG(hw, EECD, eecd);
33854848 E1000_WRITE_FLUSH(hw);
3386- udelay(eeprom->delay_usec);
3387- } else if(eeprom->type == e1000_eeprom_spi) {
4849+ usec_delay(eeprom->delay_usec);
4850+ } else if (eeprom->type == e1000_eeprom_spi) {
33884851 /* Toggle CS to flush commands */
33894852 eecd |= E1000_EECD_CS;
33904853 E1000_WRITE_REG(hw, EECD, eecd);
33914854 E1000_WRITE_FLUSH(hw);
3392- udelay(eeprom->delay_usec);
4855+ usec_delay(eeprom->delay_usec);
33934856 eecd &= ~E1000_EECD_CS;
33944857 E1000_WRITE_REG(hw, EECD, eecd);
33954858 E1000_WRITE_FLUSH(hw);
3396- udelay(eeprom->delay_usec);
4859+ usec_delay(eeprom->delay_usec);
33974860 }
33984861 }
33994862
@@ -3417,8 +4880,8 @@ e1000_release_eeprom(struct e1000_hw *hw)
34174880
34184881 E1000_WRITE_REG(hw, EECD, eecd);
34194882
3420- udelay(hw->eeprom.delay_usec);
3421- } else if(hw->eeprom.type == e1000_eeprom_microwire) {
4883+ usec_delay(hw->eeprom.delay_usec);
4884+ } else if (hw->eeprom.type == e1000_eeprom_microwire) {
34224885 /* cleanup eeprom */
34234886
34244887 /* CS on Microwire is active-high */
@@ -3430,20 +4893,22 @@ e1000_release_eeprom(struct e1000_hw *hw)
34304893 eecd |= E1000_EECD_SK;
34314894 E1000_WRITE_REG(hw, EECD, eecd);
34324895 E1000_WRITE_FLUSH(hw);
3433- udelay(hw->eeprom.delay_usec);
4896+ usec_delay(hw->eeprom.delay_usec);
34344897
34354898 /* Falling edge of clock */
34364899 eecd &= ~E1000_EECD_SK;
34374900 E1000_WRITE_REG(hw, EECD, eecd);
34384901 E1000_WRITE_FLUSH(hw);
3439- udelay(hw->eeprom.delay_usec);
4902+ usec_delay(hw->eeprom.delay_usec);
34404903 }
34414904
34424905 /* Stop requesting EEPROM access */
3443- if(hw->mac_type > e1000_82544) {
4906+ if (hw->mac_type > e1000_82544) {
34444907 eecd &= ~E1000_EECD_REQ;
34454908 E1000_WRITE_REG(hw, EECD, eecd);
34464909 }
4910+
4911+ e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
34474912 }
34484913
34494914 /******************************************************************************
@@ -3451,7 +4916,7 @@ e1000_release_eeprom(struct e1000_hw *hw)
34514916 *
34524917 * hw - Struct containing variables accessed by shared code
34534918 *****************************************************************************/
3454-int32_t
4919+static int32_t
34554920 e1000_spi_eeprom_ready(struct e1000_hw *hw)
34564921 {
34574922 uint16_t retry_count = 0;
@@ -3472,16 +4937,16 @@ e1000_spi_eeprom_ready(struct e1000_hw *hw)
34724937 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
34734938 break;
34744939
3475- udelay(5);
4940+ usec_delay(5);
34764941 retry_count += 5;
34774942
34784943 e1000_standby_eeprom(hw);
3479- } while(retry_count < EEPROM_MAX_RETRY_SPI);
4944+ } while (retry_count < EEPROM_MAX_RETRY_SPI);
34804945
34814946 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
34824947 * only 0-5mSec on 5V devices)
34834948 */
3484- if(retry_count >= EEPROM_MAX_RETRY_SPI) {
4949+ if (retry_count >= EEPROM_MAX_RETRY_SPI) {
34854950 DEBUGOUT("SPI EEPROM Status error\n");
34864951 return -E1000_ERR_EEPROM;
34874952 }
@@ -3507,24 +4972,46 @@ e1000_read_eeprom(struct e1000_hw *hw,
35074972 uint32_t i = 0;
35084973
35094974 DEBUGFUNC("e1000_read_eeprom");
4975+
4976+ /* If eeprom is not yet detected, do so now */
4977+ if (eeprom->word_size == 0)
4978+ e1000_init_eeprom_params(hw);
4979+
35104980 /* A check for invalid values: offset too large, too many words, and not
35114981 * enough words.
35124982 */
3513- if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
4983+ if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
35144984 (words == 0)) {
3515- DEBUGOUT("\"words\" parameter out of bounds\n");
4985+ DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size);
35164986 return -E1000_ERR_EEPROM;
35174987 }
35184988
3519- /* Prepare the EEPROM for reading */
3520- if(e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3521- return -E1000_ERR_EEPROM;
4989+ /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
4990+ * directly. In this case, we need to acquire the EEPROM so that
4991+ * FW or other port software does not interrupt.
4992+ */
4993+ if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
4994+ hw->eeprom.use_eerd == FALSE) {
4995+ /* Prepare the EEPROM for bit-bang reading */
4996+ if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4997+ return -E1000_ERR_EEPROM;
4998+ }
4999+
5000+ /* Eerd register EEPROM access requires no eeprom aquire/release */
5001+ if (eeprom->use_eerd == TRUE)
5002+ return e1000_read_eeprom_eerd(hw, offset, words, data);
35225003
3523- if(eeprom->type == e1000_eeprom_spi) {
5004+ /* ICH EEPROM access is done via the ICH flash controller */
5005+ if (eeprom->type == e1000_eeprom_ich8)
5006+ return e1000_read_eeprom_ich8(hw, offset, words, data);
5007+
5008+ /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
5009+ * acquired the EEPROM at this point, so any returns should relase it */
5010+ if (eeprom->type == e1000_eeprom_spi) {
35245011 uint16_t word_in;
35255012 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
35265013
3527- if(e1000_spi_eeprom_ready(hw)) {
5014+ if (e1000_spi_eeprom_ready(hw)) {
35285015 e1000_release_eeprom(hw);
35295016 return -E1000_ERR_EEPROM;
35305017 }
@@ -3532,7 +5019,7 @@ e1000_read_eeprom(struct e1000_hw *hw,
35325019 e1000_standby_eeprom(hw);
35335020
35345021 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3535- if((eeprom->address_bits == 8) && (offset >= 128))
5022+ if ((eeprom->address_bits == 8) && (offset >= 128))
35365023 read_opcode |= EEPROM_A8_OPCODE_SPI;
35375024
35385025 /* Send the READ command (opcode + addr) */
@@ -3548,7 +5035,7 @@ e1000_read_eeprom(struct e1000_hw *hw,
35485035 word_in = e1000_shift_in_ee_bits(hw, 16);
35495036 data[i] = (word_in >> 8) | (word_in << 8);
35505037 }
3551- } else if(eeprom->type == e1000_eeprom_microwire) {
5038+ } else if (eeprom->type == e1000_eeprom_microwire) {
35525039 for (i = 0; i < words; i++) {
35535040 /* Send the READ command (opcode + addr) */
35545041 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
@@ -3569,6 +5056,140 @@ e1000_read_eeprom(struct e1000_hw *hw,
35695056 return E1000_SUCCESS;
35705057 }
35715058
5059+/******************************************************************************
5060+ * Reads a 16 bit word from the EEPROM using the EERD register.
5061+ *
5062+ * hw - Struct containing variables accessed by shared code
5063+ * offset - offset of word in the EEPROM to read
5064+ * data - word read from the EEPROM
5065+ * words - number of words to read
5066+ *****************************************************************************/
5067+static int32_t
5068+e1000_read_eeprom_eerd(struct e1000_hw *hw,
5069+ uint16_t offset,
5070+ uint16_t words,
5071+ uint16_t *data)
5072+{
5073+ uint32_t i, eerd = 0;
5074+ int32_t error = 0;
5075+
5076+ for (i = 0; i < words; i++) {
5077+ eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
5078+ E1000_EEPROM_RW_REG_START;
5079+
5080+ E1000_WRITE_REG(hw, EERD, eerd);
5081+ error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
5082+
5083+ if (error) {
5084+ break;
5085+ }
5086+ data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
5087+
5088+ }
5089+
5090+ return error;
5091+}
5092+
5093+/******************************************************************************
5094+ * Writes a 16 bit word from the EEPROM using the EEWR register.
5095+ *
5096+ * hw - Struct containing variables accessed by shared code
5097+ * offset - offset of word in the EEPROM to read
5098+ * data - word read from the EEPROM
5099+ * words - number of words to read
5100+ *****************************************************************************/
5101+static int32_t
5102+e1000_write_eeprom_eewr(struct e1000_hw *hw,
5103+ uint16_t offset,
5104+ uint16_t words,
5105+ uint16_t *data)
5106+{
5107+ uint32_t register_value = 0;
5108+ uint32_t i = 0;
5109+ int32_t error = 0;
5110+
5111+ if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
5112+ return -E1000_ERR_SWFW_SYNC;
5113+
5114+ for (i = 0; i < words; i++) {
5115+ register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
5116+ ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) |
5117+ E1000_EEPROM_RW_REG_START;
5118+
5119+ error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
5120+ if (error) {
5121+ break;
5122+ }
5123+
5124+ E1000_WRITE_REG(hw, EEWR, register_value);
5125+
5126+ error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
5127+
5128+ if (error) {
5129+ break;
5130+ }
5131+ }
5132+
5133+ e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
5134+ return error;
5135+}
5136+
5137+/******************************************************************************
5138+ * Polls the status bit (bit 1) of the EERD to determine when the read is done.
5139+ *
5140+ * hw - Struct containing variables accessed by shared code
5141+ *****************************************************************************/
5142+static int32_t
5143+e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
5144+{
5145+ uint32_t attempts = 100000;
5146+ uint32_t i, reg = 0;
5147+ int32_t done = E1000_ERR_EEPROM;
5148+
5149+ for (i = 0; i < attempts; i++) {
5150+ if (eerd == E1000_EEPROM_POLL_READ)
5151+ reg = E1000_READ_REG(hw, EERD);
5152+ else
5153+ reg = E1000_READ_REG(hw, EEWR);
5154+
5155+ if (reg & E1000_EEPROM_RW_REG_DONE) {
5156+ done = E1000_SUCCESS;
5157+ break;
5158+ }
5159+ usec_delay(5);
5160+ }
5161+
5162+ return done;
5163+}
5164+
5165+/***************************************************************************
5166+* Description: Determines if the onboard NVM is FLASH or EEPROM.
5167+*
5168+* hw - Struct containing variables accessed by shared code
5169+****************************************************************************/
5170+static boolean_t
5171+e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
5172+{
5173+ uint32_t eecd = 0;
5174+
5175+ DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
5176+
5177+ if (hw->is_ich == TRUE)
5178+ return FALSE;
5179+
5180+ if (hw->mac_type == e1000_82573) {
5181+ eecd = E1000_READ_REG(hw, EECD);
5182+
5183+ /* Isolate bits 15 & 16 */
5184+ eecd = ((eecd >> 15) & 0x03);
5185+
5186+ /* If both bits are set, device is Flash type */
5187+ if (eecd == 0x03) {
5188+ return FALSE;
5189+ }
5190+ }
5191+ return TRUE;
5192+}
35725193
35735194 /******************************************************************************
35745195 * Verifies that the EEPROM has a valid checksum
@@ -3587,15 +5208,49 @@ e1000_validate_eeprom_checksum(struct e1000_hw *hw)
35875208
35885209 DEBUGFUNC("e1000_validate_eeprom_checksum");
35895210
3590- for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
3591- if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5211+ if ((hw->mac_type == e1000_82573) &&
5212+ (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) {
5213+ /* Check bit 4 of word 10h. If it is 0, firmware is done updating
5214+ * 10h-12h. Checksum may need to be fixed. */
5215+ e1000_read_eeprom(hw, 0x10, 1, &eeprom_data);
5216+ if ((eeprom_data & 0x10) == 0) {
5217+ /* Read 0x23 and check bit 15. This bit is a 1 when the checksum
5218+ * has already been fixed. If the checksum is still wrong and this
5219+ * bit is a 1, we need to return bad checksum. Otherwise, we need
5220+ * to set this bit to a 1 and update the checksum. */
5221+ e1000_read_eeprom(hw, 0x23, 1, &eeprom_data);
5222+ if ((eeprom_data & 0x8000) == 0) {
5223+ eeprom_data |= 0x8000;
5224+ e1000_write_eeprom(hw, 0x23, 1, &eeprom_data);
5225+ e1000_update_eeprom_checksum(hw);
5226+ }
5227+ }
5228+ }
5229+
5230+ if (hw->is_ich == TRUE) {
5231+
5232+ /* Drivers must allocate the shadow ram structure for the
5233+ * EEPROM checksum to be updated. Otherwise, this bit as well
5234+ * as the checksum must both be set correctly for this
5235+ * validation to pass.
5236+ */
5237+ e1000_read_eeprom(hw, 0x19, 1, &eeprom_data);
5238+ if ((eeprom_data & 0x40) == 0) {
5239+ eeprom_data |= 0x40;
5240+ e1000_write_eeprom(hw, 0x19, 1, &eeprom_data);
5241+ e1000_update_eeprom_checksum(hw);
5242+ }
5243+ }
5244+
5245+ for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
5246+ if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
35925247 DEBUGOUT("EEPROM Read Error\n");
35935248 return -E1000_ERR_EEPROM;
35945249 }
35955250 checksum += eeprom_data;
35965251 }
35975252
3598- if(checksum == (uint16_t) EEPROM_SUM)
5253+ if (checksum == (uint16_t) EEPROM_SUM)
35995254 return E1000_SUCCESS;
36005255 else {
36015256 DEBUGOUT("EEPROM Checksum Invalid\n");
@@ -3614,22 +5269,33 @@ e1000_validate_eeprom_checksum(struct e1000_hw *hw)
36145269 int32_t
36155270 e1000_update_eeprom_checksum(struct e1000_hw *hw)
36165271 {
5272+ uint32_t ctrl_ext;
36175273 uint16_t checksum = 0;
36185274 uint16_t i, eeprom_data;
36195275
36205276 DEBUGFUNC("e1000_update_eeprom_checksum");
36215277
3622- for(i = 0; i < EEPROM_CHECKSUM_REG; i++) {
3623- if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5278+ for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
5279+ if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
36245280 DEBUGOUT("EEPROM Read Error\n");
36255281 return -E1000_ERR_EEPROM;
36265282 }
36275283 checksum += eeprom_data;
36285284 }
36295285 checksum = (uint16_t) EEPROM_SUM - checksum;
3630- if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
5286+ if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
36315287 DEBUGOUT("EEPROM Write Error\n");
36325288 return -E1000_ERR_EEPROM;
5289+ } else if (hw->eeprom.type == e1000_eeprom_flash) {
5290+ e1000_commit_shadow_ram(hw);
5291+ } else if (hw->eeprom.type == e1000_eeprom_ich8) {
5292+ e1000_commit_shadow_ram(hw);
5293+ /* Reload the EEPROM, or else modifications will not appear
5294+ * until after next adapter reset. */
5295+ ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5296+ ctrl_ext |= E1000_CTRL_EXT_EE_RST;
5297+ E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5298+ msec_delay(10);
36335299 }
36345300 return E1000_SUCCESS;
36355301 }
@@ -3656,20 +5322,31 @@ e1000_write_eeprom(struct e1000_hw *hw,
36565322
36575323 DEBUGFUNC("e1000_write_eeprom");
36585324
5325+ /* If eeprom is not yet detected, do so now */
5326+ if (eeprom->word_size == 0)
5327+ e1000_init_eeprom_params(hw);
5328+
36595329 /* A check for invalid values: offset too large, too many words, and not
36605330 * enough words.
36615331 */
3662- if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
5332+ if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
36635333 (words == 0)) {
36645334 DEBUGOUT("\"words\" parameter out of bounds\n");
36655335 return -E1000_ERR_EEPROM;
36665336 }
36675337
5338+ /* 82573 writes only through eewr */
5339+ if (eeprom->use_eewr == TRUE)
5340+ return e1000_write_eeprom_eewr(hw, offset, words, data);
5341+
5342+ if (eeprom->type == e1000_eeprom_ich8)
5343+ return e1000_write_eeprom_ich8(hw, offset, words, data);
5344+
36685345 /* Prepare the EEPROM for writing */
36695346 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
36705347 return -E1000_ERR_EEPROM;
36715348
3672- if(eeprom->type == e1000_eeprom_microwire) {
5349+ if (eeprom->type == e1000_eeprom_microwire) {
36735350 status = e1000_write_eeprom_microwire(hw, offset, words, data);
36745351 } else {
36755352 status = e1000_write_eeprom_spi(hw, offset, words, data);
@@ -3691,7 +5368,7 @@ e1000_write_eeprom(struct e1000_hw *hw,
36915368 * data - pointer to array of 8 bit words to be written to the EEPROM
36925369 *
36935370 *****************************************************************************/
3694-int32_t
5371+static int32_t
36955372 e1000_write_eeprom_spi(struct e1000_hw *hw,
36965373 uint16_t offset,
36975374 uint16_t words,
@@ -3705,7 +5382,7 @@ e1000_write_eeprom_spi(struct e1000_hw *hw,
37055382 while (widx < words) {
37065383 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
37075384
3708- if(e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
5385+ if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
37095386
37105387 e1000_standby_eeprom(hw);
37115388
@@ -3716,7 +5393,7 @@ e1000_write_eeprom_spi(struct e1000_hw *hw,
37165393 e1000_standby_eeprom(hw);
37175394
37185395 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3719- if((eeprom->address_bits == 8) && (offset >= 128))
5396+ if ((eeprom->address_bits == 8) && (offset >= 128))
37205397 write_opcode |= EEPROM_A8_OPCODE_SPI;
37215398
37225399 /* Send the Write command (8-bit opcode + addr) */
@@ -3738,7 +5415,7 @@ e1000_write_eeprom_spi(struct e1000_hw *hw,
37385415 * operation, while the smaller eeproms are capable of an 8-byte
37395416 * PAGE WRITE operation. Break the inner loop to pass new address
37405417 */
3741- if((((offset + widx)*2) % eeprom->page_size) == 0) {
5418+ if ((((offset + widx)*2) % eeprom->page_size) == 0) {
37425419 e1000_standby_eeprom(hw);
37435420 break;
37445421 }
@@ -3757,7 +5434,7 @@ e1000_write_eeprom_spi(struct e1000_hw *hw,
37575434 * data - pointer to array of 16 bit words to be written to the EEPROM
37585435 *
37595436 *****************************************************************************/
3760-int32_t
5437+static int32_t
37615438 e1000_write_eeprom_microwire(struct e1000_hw *hw,
37625439 uint16_t offset,
37635440 uint16_t words,
@@ -3804,12 +5481,12 @@ e1000_write_eeprom_microwire(struct e1000_hw *hw,
38045481 * signal that the command has been completed by raising the DO signal.
38055482 * If DO does not go high in 10 milliseconds, then error out.
38065483 */
3807- for(i = 0; i < 200; i++) {
5484+ for (i = 0; i < 200; i++) {
38085485 eecd = E1000_READ_REG(hw, EECD);
3809- if(eecd & E1000_EECD_DO) break;
3810- udelay(50);
5486+ if (eecd & E1000_EECD_DO) break;
5487+ usec_delay(50);
38115488 }
3812- if(i == 200) {
5489+ if (i == 200) {
38135490 DEBUGOUT("EEPROM Write did not complete\n");
38145491 return -E1000_ERR_EEPROM;
38155492 }
@@ -3835,37 +5512,171 @@ e1000_write_eeprom_microwire(struct e1000_hw *hw,
38355512 }
38365513
38375514 /******************************************************************************
3838- * Reads the adapter's part number from the EEPROM
5515+ * Flushes the cached eeprom to NVM. This is done by saving the modified values
5516+ * in the eeprom cache and the non modified values in the currently active bank
5517+ * to the new bank.
38395518 *
38405519 * hw - Struct containing variables accessed by shared code
3841- * part_num - Adapter's part number
5520+ * offset - offset of word in the EEPROM to read
5521+ * data - word read from the EEPROM
5522+ * words - number of words to read
38425523 *****************************************************************************/
3843-int32_t
3844-e1000_read_part_num(struct e1000_hw *hw,
3845- uint32_t *part_num)
5524+static int32_t
5525+e1000_commit_shadow_ram(struct e1000_hw *hw)
38465526 {
3847- uint16_t offset = EEPROM_PBA_BYTE_1;
3848- uint16_t eeprom_data;
5527+ uint32_t attempts = 100000;
5528+ uint32_t eecd = 0;
5529+ uint32_t flop = 0;
5530+ uint32_t i = 0;
5531+ int32_t error = E1000_SUCCESS;
5532+ uint32_t old_bank_offset = 0;
5533+ uint32_t new_bank_offset = 0;
5534+ uint8_t low_byte = 0;
5535+ uint8_t high_byte = 0;
5536+ boolean_t sector_write_failed = FALSE;
5537+
5538+ if (hw->mac_type == e1000_82573) {
5539+ /* The flop register will be used to determine if flash type is STM */
5540+ flop = E1000_READ_REG(hw, FLOP);
5541+ for (i=0; i < attempts; i++) {
5542+ eecd = E1000_READ_REG(hw, EECD);
5543+ if ((eecd & E1000_EECD_FLUPD) == 0) {
5544+ break;
5545+ }
5546+ usec_delay(5);
5547+ }
38495548
3850- DEBUGFUNC("e1000_read_part_num");
5549+ if (i == attempts) {
5550+ return -E1000_ERR_EEPROM;
5551+ }
38515552
3852- /* Get word 0 from EEPROM */
3853- if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
3854- DEBUGOUT("EEPROM Read Error\n");
3855- return -E1000_ERR_EEPROM;
5553+ /* If STM opcode located in bits 15:8 of flop, reset firmware */
5554+ if ((flop & 0xFF00) == E1000_STM_OPCODE) {
5555+ E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET);
5556+ }
5557+
5558+ /* Perform the flash update */
5559+ E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD);
5560+
5561+ for (i=0; i < attempts; i++) {
5562+ eecd = E1000_READ_REG(hw, EECD);
5563+ if ((eecd & E1000_EECD_FLUPD) == 0) {
5564+ break;
5565+ }
5566+ usec_delay(5);
5567+ }
5568+
5569+ if (i == attempts) {
5570+ return -E1000_ERR_EEPROM;
5571+ }
38565572 }
3857- /* Save word 0 in upper half of part_num */
3858- *part_num = (uint32_t) (eeprom_data << 16);
38595573
3860- /* Get word 1 from EEPROM */
3861- if(e1000_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) {
3862- DEBUGOUT("EEPROM Read Error\n");
3863- return -E1000_ERR_EEPROM;
5574+ if ((hw->is_ich == TRUE) && hw->eeprom_shadow_ram != NULL) {
5575+ /* We're writing to the opposite bank so if we're on bank 1,
5576+ * write to bank 0 etc. We also need to erase the segment that
5577+ * is going to be written */
5578+ if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) {
5579+ new_bank_offset = hw->flash_bank_size * 2;
5580+ old_bank_offset = 0;
5581+ e1000_erase_ich8_4k_segment(hw, 1);
5582+ } else {
5583+ old_bank_offset = hw->flash_bank_size * 2;
5584+ new_bank_offset = 0;
5585+ e1000_erase_ich8_4k_segment(hw, 0);
5586+ }
5587+
5588+ sector_write_failed = FALSE;
5589+ /* Loop for every byte in the shadow RAM,
5590+ * which is in units of words. */
5591+ for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5592+ /* Determine whether to write the value stored
5593+ * in the other NVM bank or a modified value stored
5594+ * in the shadow RAM */
5595+ if (hw->eeprom_shadow_ram[i].modified == TRUE) {
5596+ low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word;
5597+ usec_delay(100);
5598+ error = e1000_verify_write_ich8_byte(hw,
5599+ (i << 1) + new_bank_offset, low_byte);
5600+
5601+ if (error != E1000_SUCCESS)
5602+ sector_write_failed = TRUE;
5603+ else {
5604+ high_byte =
5605+ (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
5606+ usec_delay(100);
5607+ }
5608+ } else {
5609+ e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5610+ &low_byte);
5611+ usec_delay(100);
5612+ error = e1000_verify_write_ich8_byte(hw,
5613+ (i << 1) + new_bank_offset, low_byte);
5614+
5615+ if (error != E1000_SUCCESS)
5616+ sector_write_failed = TRUE;
5617+ else {
5618+ e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5619+ &high_byte);
5620+ usec_delay(100);
5621+ }
5622+ }
5623+
5624+ /* If the write of the low byte was successful, go ahread and
5625+ * write the high byte while checking to make sure that if it
5626+ * is the signature byte, then it is handled properly */
5627+ if (sector_write_failed == FALSE) {
5628+ /* If the word is 0x13, then make sure the signature bits
5629+ * (15:14) are 11b until the commit has completed.
5630+ * This will allow us to write 10b which indicates the
5631+ * signature is valid. We want to do this after the write
5632+ * has completed so that we don't mark the segment valid
5633+ * while the write is still in progress */
5634+ if (i == E1000_ICH_NVM_SIG_WORD)
5635+ high_byte = E1000_ICH_NVM_SIG_MASK | high_byte;
5636+
5637+ error = e1000_verify_write_ich8_byte(hw,
5638+ (i << 1) + new_bank_offset + 1, high_byte);
5639+ if (error != E1000_SUCCESS)
5640+ sector_write_failed = TRUE;
5641+
5642+ } else {
5643+ /* If the write failed then break from the loop and
5644+ * return an error */
5645+ break;
5646+ }
5647+ }
5648+
5649+ /* Don't bother writing the segment valid bits if sector
5650+ * programming failed. */
5651+ if (sector_write_failed == FALSE) {
5652+ /* Finally validate the new segment by setting bit 15:14
5653+ * to 10b in word 0x13 , this can be done without an
5654+ * erase as well since these bits are 11 to start with
5655+ * and we need to change bit 14 to 0b */
5656+ e1000_read_ich8_byte(hw,
5657+ E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5658+ &high_byte);
5659+ high_byte &= 0xBF;
5660+ error = e1000_verify_write_ich8_byte(hw,
5661+ E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte);
5662+ /* And invalidate the previously valid segment by setting
5663+ * its signature word (0x13) high_byte to 0b. This can be
5664+ * done without an erase because flash erase sets all bits
5665+ * to 1's. We can write 1's to 0's without an erase */
5666+ if (error == E1000_SUCCESS) {
5667+ error = e1000_verify_write_ich8_byte(hw,
5668+ E1000_ICH_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0);
5669+ }
5670+
5671+ /* Clear the now not used entry in the cache */
5672+ for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5673+ hw->eeprom_shadow_ram[i].modified = FALSE;
5674+ hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
5675+ }
5676+ }
38645677 }
3865- /* Save word 1 in lower half of part_num */
3866- *part_num |= eeprom_data;
38675678
3868- return E1000_SUCCESS;
5679+ return error;
38695680 }
38705681
38715682 /******************************************************************************
@@ -3882,20 +5693,29 @@ e1000_read_mac_addr(struct e1000_hw * hw)
38825693
38835694 DEBUGFUNC("e1000_read_mac_addr");
38845695
3885- for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
5696+ for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
38865697 offset = i >> 1;
3887- if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
5698+ if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
38885699 DEBUGOUT("EEPROM Read Error\n");
38895700 return -E1000_ERR_EEPROM;
38905701 }
38915702 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
38925703 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
38935704 }
3894- if(((hw->mac_type == e1000_82546) || (hw->mac_type == e1000_82546_rev_3)) &&
3895- (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1))
5705+
5706+ switch (hw->mac_type) {
5707+ default:
5708+ break;
5709+ case e1000_82546:
5710+ case e1000_82546_rev_3:
5711+ case e1000_82571:
5712+ case e1000_80003es2lan:
5713+ if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
38965714 hw->perm_mac_addr[5] ^= 0x01;
5715+ break;
5716+ }
38975717
3898- for(i = 0; i < NODE_ADDRESS_SIZE; i++)
5718+ for (i = 0; i < NODE_ADDRESS_SIZE; i++)
38995719 hw->mac_addr[i] = hw->perm_mac_addr[i];
39005720 return E1000_SUCCESS;
39015721 }
@@ -3909,10 +5729,11 @@ e1000_read_mac_addr(struct e1000_hw * hw)
39095729 * of the receive addresss registers. Clears the multicast table. Assumes
39105730 * the receiver is in reset when the routine is called.
39115731 *****************************************************************************/
3912-void
5732+static void
39135733 e1000_init_rx_addrs(struct e1000_hw *hw)
39145734 {
39155735 uint32_t i;
5736+ uint32_t rar_num;
39165737
39175738 DEBUGFUNC("e1000_init_rx_addrs");
39185739
@@ -3921,86 +5742,24 @@ e1000_init_rx_addrs(struct e1000_hw *hw)
39215742
39225743 e1000_rar_set(hw, hw->mac_addr, 0);
39235744
3924- /* Zero out the other 15 receive addresses. */
3925- DEBUGOUT("Clearing RAR[1-15]\n");
3926- for(i = 1; i < E1000_RAR_ENTRIES; i++) {
3927- E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
3928- E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
3929- }
3930-}
3931-
3932-/******************************************************************************
3933- * Updates the MAC's list of multicast addresses.
3934- *
3935- * hw - Struct containing variables accessed by shared code
3936- * mc_addr_list - the list of new multicast addresses
3937- * mc_addr_count - number of addresses
3938- * pad - number of bytes between addresses in the list
3939- * rar_used_count - offset where to start adding mc addresses into the RAR's
3940- *
3941- * The given list replaces any existing list. Clears the last 15 receive
3942- * address registers and the multicast table. Uses receive address registers
3943- * for the first 15 multicast addresses, and hashes the rest into the
3944- * multicast table.
3945- *****************************************************************************/
3946-void
3947-e1000_mc_addr_list_update(struct e1000_hw *hw,
3948- uint8_t *mc_addr_list,
3949- uint32_t mc_addr_count,
3950- uint32_t pad,
3951- uint32_t rar_used_count)
3952-{
3953- uint32_t hash_value;
3954- uint32_t i;
3955-
3956- DEBUGFUNC("e1000_mc_addr_list_update");
5745+ rar_num = E1000_RAR_ENTRIES;
39575746
3958- /* Set the new number of MC addresses that we are being requested to use. */
3959- hw->num_mc_addrs = mc_addr_count;
5747+ /* Reserve a spot for the Locally Administered Address to work around
5748+ * an 82571 issue in which a reset on one port will reload the MAC on
5749+ * the other port. */
5750+ if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
5751+ rar_num -= 1;
5752+ if (hw->mac_type == e1000_ich8lan)
5753+ rar_num = E1000_RAR_ENTRIES_ICH8LAN;
39605754
3961- /* Clear RAR[1-15] */
3962- DEBUGOUT(" Clearing RAR[1-15]\n");
3963- for(i = rar_used_count; i < E1000_RAR_ENTRIES; i++) {
5755+ /* Zero out the other 15 receive addresses. */
5756+ DEBUGOUT("Clearing RAR[1-15]\n");
5757+ for (i = 1; i < rar_num; i++) {
39645758 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5759+ E1000_WRITE_FLUSH(hw);
39655760 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5761+ E1000_WRITE_FLUSH(hw);
39665762 }
3967-
3968- /* Clear the MTA */
3969- DEBUGOUT(" Clearing MTA\n");
3970- for(i = 0; i < E1000_NUM_MTA_REGISTERS; i++) {
3971- E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
3972- }
3973-
3974- /* Add the new addresses */
3975- for(i = 0; i < mc_addr_count; i++) {
3976- DEBUGOUT(" Adding the multicast addresses:\n");
3977- DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
3978- mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
3979- mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1],
3980- mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2],
3981- mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3],
3982- mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4],
3983- mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]);
3984-
3985- hash_value = e1000_hash_mc_addr(hw,
3986- mc_addr_list +
3987- (i * (ETH_LENGTH_OF_ADDRESS + pad)));
3988-
3989- DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
3990-
3991- /* Place this multicast address in the RAR if there is room, *
3992- * else put it in the MTA
3993- */
3994- if(rar_used_count < E1000_RAR_ENTRIES) {
3995- e1000_rar_set(hw,
3996- mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)),
3997- rar_used_count);
3998- rar_used_count++;
3999- } else {
4000- e1000_mta_set(hw, hash_value);
4001- }
4002- }
4003- DEBUGOUT("MC Update Complete\n");
40045763 }
40055764
40065765 /******************************************************************************
@@ -4024,24 +5783,47 @@ e1000_hash_mc_addr(struct e1000_hw *hw,
40245783 * LSB MSB
40255784 */
40265785 case 0:
4027- /* [47:36] i.e. 0x563 for above example address */
4028- hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5786+ if (hw->is_ich == TRUE) {
5787+ /* [47:38] i.e. 0x158 for above example address */
5788+ hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2));
5789+ } else {
5790+ /* [47:36] i.e. 0x563 for above example address */
5791+ hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5792+ }
40295793 break;
40305794 case 1:
4031- /* [46:35] i.e. 0xAC6 for above example address */
4032- hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
5795+ if (hw->is_ich == TRUE) {
5796+ /* [46:37] i.e. 0x2B1 for above example address */
5797+ hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3));
5798+ } else {
5799+ /* [46:35] i.e. 0xAC6 for above example address */
5800+ hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
5801+ }
40335802 break;
40345803 case 2:
4035- /* [45:34] i.e. 0x5D8 for above example address */
4036- hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5804+ if (hw->is_ich == TRUE) {
5805+ /*[45:36] i.e. 0x163 for above example address */
5806+ hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5807+ } else {
5808+ /* [45:34] i.e. 0x5D8 for above example address */
5809+ hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5810+ }
40375811 break;
40385812 case 3:
4039- /* [43:32] i.e. 0x634 for above example address */
4040- hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
5813+ if (hw->is_ich == TRUE) {
5814+ /* [43:34] i.e. 0x18D for above example address */
5815+ hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5816+ } else {
5817+ /* [43:32] i.e. 0x634 for above example address */
5818+ hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
5819+ }
40415820 break;
40425821 }
40435822
40445823 hash_value &= 0xFFF;
5824+ if (hw->is_ich == TRUE)
5825+ hash_value &= 0x3FF;
5826+
40455827 return hash_value;
40465828 }
40475829
@@ -4068,6 +5850,9 @@ e1000_mta_set(struct e1000_hw *hw,
40685850 * register are determined by the lower 5 bits of the value.
40695851 */
40705852 hash_reg = (hash_value >> 5) & 0x7F;
5853+ if (hw->is_ich == TRUE)
5854+ hash_reg &= 0x1F;
5855+
40715856 hash_bit = hash_value & 0x1F;
40725857
40735858 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
@@ -4078,12 +5863,15 @@ e1000_mta_set(struct e1000_hw *hw,
40785863 * in the MTA, save off the previous entry before writing and
40795864 * restore the old value after writing.
40805865 */
4081- if((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
5866+ if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
40825867 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
40835868 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5869+ E1000_WRITE_FLUSH(hw);
40845870 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
5871+ E1000_WRITE_FLUSH(hw);
40855872 } else {
40865873 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5874+ E1000_WRITE_FLUSH(hw);
40875875 }
40885876 }
40895877
@@ -4107,11 +5895,42 @@ e1000_rar_set(struct e1000_hw *hw,
41075895 rar_low = ((uint32_t) addr[0] |
41085896 ((uint32_t) addr[1] << 8) |
41095897 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
5898+ rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8));
41105899
4111- rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8) | E1000_RAH_AV);
5900+ /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
5901+ * unit hang.
5902+ *
5903+ * Description:
5904+ * If there are any Rx frames queued up or otherwise present in the HW
5905+ * before RSS is enabled, and then we enable RSS, the HW Rx unit will
5906+ * hang. To work around this issue, we have to disable receives and
5907+ * flush out all Rx frames before we enable RSS. To do so, we modify we
5908+ * redirect all Rx traffic to manageability and then reset the HW.
5909+ * This flushes away Rx frames, and (since the redirections to
5910+ * manageability persists across resets) keeps new ones from coming in
5911+ * while we work. Then, we clear the Address Valid AV bit for all MAC
5912+ * addresses and undo the re-direction to manageability.
5913+ * Now, frames are coming in again, but the MAC won't accept them, so
5914+ * far so good. We now proceed to initialize RSS (if necessary) and
5915+ * configure the Rx unit. Last, we re-enable the AV bits and continue
5916+ * on our merry way.
5917+ */
5918+ switch (hw->mac_type) {
5919+ case e1000_82571:
5920+ case e1000_82572:
5921+ case e1000_80003es2lan:
5922+ if (hw->leave_av_bit_off == TRUE)
5923+ break;
5924+ default:
5925+ /* Indicate to hardware the Address is Valid. */
5926+ rar_high |= E1000_RAH_AV;
5927+ break;
5928+ }
41125929
41135930 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
5931+ E1000_WRITE_FLUSH(hw);
41145932 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
5933+ E1000_WRITE_FLUSH(hw);
41155934 }
41165935
41175936 /******************************************************************************
@@ -4128,12 +5947,18 @@ e1000_write_vfta(struct e1000_hw *hw,
41285947 {
41295948 uint32_t temp;
41305949
4131- if((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
5950+ if (hw->is_ich == TRUE)
5951+ return;
5952+
5953+ if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
41325954 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
41335955 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5956+ E1000_WRITE_FLUSH(hw);
41345957 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
5958+ E1000_WRITE_FLUSH(hw);
41355959 } else {
41365960 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5961+ E1000_WRITE_FLUSH(hw);
41375962 }
41385963 }
41395964
@@ -4142,13 +5967,38 @@ e1000_write_vfta(struct e1000_hw *hw,
41425967 *
41435968 * hw - Struct containing variables accessed by shared code
41445969 *****************************************************************************/
4145-void
5970+static void
41465971 e1000_clear_vfta(struct e1000_hw *hw)
41475972 {
41485973 uint32_t offset;
4149-
4150- for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
4151- E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
5974+ uint32_t vfta_value = 0;
5975+ uint32_t vfta_offset = 0;
5976+ uint32_t vfta_bit_in_reg = 0;
5977+
5978+ if (hw->is_ich == TRUE)
5979+ return;
5980+
5981+ if (hw->mac_type == e1000_82573) {
5982+ if (hw->mng_cookie.vlan_id != 0) {
5983+ /* The VFTA is a 4096b bit-field, each identifying a single VLAN