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common_source_project-fm7: Commit

Common Source Code Project for Qt (a.k.a for FM-7).


Commit MetaInfo

Revisioncc9f25ca1f420c751ea6f33f4edef7ac5e7079fb (tree)
Zeit2023-03-06 20:15:18
AutorK.Ohta <whatisthis.sowhat@gmai...>
CommiterK.Ohta

Log Message

[VM][Z80][PC9801][DISPLAY] Merge upstream 2022-09-30 .

[VM][Z80] Split Z80::check_interrupt() .

Ändern Zusammenfassung

Diff

--- a/source/history.txt
+++ b/source/history.txt
@@ -1,3 +1,10 @@
1+9/30/2022
2+
3+[VM/Z80] fix for DI,EI,EI,DI case
4+
5+[PC9801/DISPLAY] fix scroll register
6+
7+
18 9/11/2022
29
310 [VM/SCSI_DEV] fix delay to raise REQ signal after ACK is raised
--- a/source/src/vm/common_vm/CMakeLists.txt
+++ b/source/src/vm/common_vm/CMakeLists.txt
@@ -1,6 +1,6 @@
11 message("* vm/common_vm")
22
3-SET(THIS_LIB_VERSION 7.7.0)
3+SET(THIS_LIB_VERSION 7.7.1)
44
55 #include(cotire)
66 set(s_vm_common_vm_srcs
--- a/source/src/vm/pc9801/display.cpp
+++ b/source/src/vm/pc9801/display.cpp
@@ -1742,9 +1742,6 @@ void DISPLAY::draw_chr_screen()
17421742 // if(ytop >= (_height << 4)) break;
17431743 }
17441744
1745- uint32_t *addr = &gdc_addr[0][0];
1746-// uint32_t *addr2 = addr + 160 * (sur + sdr);
1747- uint32_t *addr2 = addr + 80 * (sur + sdr);
17481745
17491746 uint32_t cursor_addr = d_gdc_chr->cursor_addr(0x1fff);
17501747 int cursor_top = d_gdc_chr->cursor_top();
@@ -1761,6 +1758,9 @@ void DISPLAY::draw_chr_screen()
17611758 int xofs = modereg1[MODE1_COLUMN] ? (FONT_WIDTH * 2) : FONT_WIDTH;
17621759 int addrofs = modereg1[MODE1_COLUMN] ? 2 : 1;
17631760
1761+ uint32_t *addr = &gdc_addr[0][0];
1762+ uint32_t *addr2 = addr;
1763+
17641764 memset(screen_chr, 0, sizeof(screen_chr));
17651765
17661766 _width <<= 4;
@@ -1789,7 +1789,8 @@ void DISPLAY::draw_chr_screen()
17891789 uint8_t attr = tvram[(*addr) | 0x2000];
17901790 uint8_t color = (attr & ATTR_COL) ? (attr >> 5) : 8;
17911791 bool cursor = ((*addr) == cursor_addr);
1792- addr += addrofs;
1792+ addr += addrofs;
1793+ addr2 += addrofs;
17931794 if(kanji2nd) {
17941795 kanji2nd = 0;
17951796 offset = last + KANJI_2ND_OFS;
--- a/source/src/vm/z80.cpp
+++ b/source/src/vm/z80.cpp
@@ -143,17 +143,17 @@
143143 Z80_INLINE uint8_t Z80::RM8(uint32_t addr)
144144 {
145145 //#ifdef Z80_MEMORY_WAIT
146- UPDATE_EVENT_IN_OP(2);
146+ UPDATE_EVENT_IN_OP(1);
147147 if(has_memory_wait) {
148148 int wait_clock;
149149 uint8_t val = d_mem->read_data8w(addr, &wait_clock);
150150 icount -= wait_clock;
151- CLOCK_IN_OP(1 + wait_clock);
151+ CLOCK_IN_OP(2 + wait_clock);
152152 return val;
153153 } else {
154154 //#else
155155 uint8_t val = d_mem->read_data8(addr);
156- CLOCK_IN_OP(1);
156+ CLOCK_IN_OP(2);
157157 return val;
158158 }
159159 //#endif
@@ -162,16 +162,16 @@ Z80_INLINE uint8_t Z80::RM8(uint32_t addr)
162162 Z80_INLINE void Z80::WM8(uint32_t addr, uint8_t val)
163163 {
164164 //#ifdef Z80_MEMORY_WAIT
165- UPDATE_EVENT_IN_OP(2);
165+ UPDATE_EVENT_IN_OP(1);
166166 if(has_memory_wait) {
167167 int wait_clock;
168168 d_mem->write_data8w(addr, val, &wait_clock);
169169 icount -= wait_clock;
170- CLOCK_IN_OP(1 + wait_clock);
170+ CLOCK_IN_OP(2 + wait_clock);
171171 } else {
172172 //#else
173173 d_mem->write_data8(addr, val);
174- CLOCK_IN_OP(1);
174+ CLOCK_IN_OP(2);
175175 }
176176 //#endif
177177 }
@@ -195,11 +195,11 @@ Z80_INLINE uint8_t Z80::FETCHOP()
195195 R++;
196196
197197 // consider m1 cycle wait
198- UPDATE_EVENT_IN_OP(2);
198+ UPDATE_EVENT_IN_OP(1);
199199 int wait_clock;
200200 uint8_t val = d_mem->fetch_op(pctmp, &wait_clock);
201201 icount -= wait_clock;
202- CLOCK_IN_OP(2 + wait_clock);
202+ CLOCK_IN_OP(3 + wait_clock);
203203 return val;
204204 }
205205
@@ -220,17 +220,17 @@ Z80_INLINE uint32_t Z80::FETCH16()
220220 Z80_INLINE uint8_t Z80::IN8(uint32_t addr)
221221 {
222222 //#ifdef Z80_IO_WAIT
223- UPDATE_EVENT_IN_OP(3);
223+ UPDATE_EVENT_IN_OP(2);
224224 if(has_io_wait) {
225225 int wait_clock;
226226 uint8_t val = d_io->read_io8w(addr, &wait_clock);
227227 icount -= wait_clock;
228- CLOCK_IN_OP(1 + wait_clock);
228+ CLOCK_IN_OP(2 + wait_clock);
229229 return val;
230230 } else {
231231 //#else
232232 uint8_t val = d_io->read_io8(addr);
233- CLOCK_IN_OP(1);
233+ CLOCK_IN_OP(2);
234234 return val;
235235 }
236236 //#endif
@@ -239,11 +239,11 @@ Z80_INLINE uint8_t Z80::IN8(uint32_t addr)
239239 Z80_INLINE void Z80::OUT8(uint32_t addr, uint8_t val)
240240 {
241241 //#ifdef HAS_NSC800
242- UPDATE_EVENT_IN_OP(3);
242+ UPDATE_EVENT_IN_OP(2);
243243 if(has_nsc800) {
244244 if((addr & 0xff) == 0xbb) {
245245 icr = val;
246- CLOCK_IN_OP(1);
246+ CLOCK_IN_OP(2);
247247 return;
248248 }
249249 }
@@ -253,11 +253,11 @@ Z80_INLINE void Z80::OUT8(uint32_t addr, uint8_t val)
253253 int wait_clock;
254254 d_io->write_io8w(addr, val, &wait_clock);
255255 icount -= wait_clock;
256- CLOCK_IN_OP(1 + wait_clock);
256+ CLOCK_IN_OP(2 + wait_clock);
257257 } else {
258258 //#else
259259 d_io->write_io8(addr, val);
260- CLOCK_IN_OP(1);
260+ CLOCK_IN_OP(2);
261261 }
262262 //#endif
263263 }
@@ -1909,7 +1909,7 @@ void Z80::OP(uint8_t code)
19091909 case 0xf0: RET_COND(!(F & SF), 0xf0); break; /* RET P */
19101910 case 0xf1: POP(af); break; /* POP AF */
19111911 case 0xf2: JP_COND(!(F & SF)); break; /* JP P,a */
1912- case 0xf3: iff1 = iff2 = 0; break; /* DI */
1912+ case 0xf3: iff1 = iff2 = 0; after_di = true; break; /* DI */
19131913 case 0xf4: CALL_COND(!(F & SF), 0xf4); break; /* CALL P,a */
19141914 case 0xf5: PUSH(af); break; /* PUSH AF */
19151915 case 0xf6: OR(FETCH8()); break; /* OR n */
@@ -2107,7 +2107,7 @@ void Z80::special_reset(int num)
21072107 ea = 0;
21082108
21092109 im = iff1 = iff2 = icr = 0;
2110- after_halt = after_ei = false;
2110+ after_halt = after_di = after_ei = false;
21112111 after_ldair = false;
21122112 intr_req_bit = intr_pend_bit = 0;
21132113 }
@@ -2381,7 +2381,7 @@ void Z80::run_one_opecode()
23812381 // rune one opecode
23822382 bool prev_after_ei = after_ei;
23832383
2384- after_halt = after_ei = false;
2384+ after_halt = after_di = after_ei = false;
23852385 after_ldair = false;
23862386
23872387 bool now_debugging = false;
@@ -2413,11 +2413,12 @@ void Z80::run_one_opecode()
24132413 }
24142414 }
24152415 //#endif
2416- if(prev_after_ei) {
2417- d_pic->notify_intr_ei();
2418- check_interrupt();
2419- after_ei = false;
2420- } else if(!after_ei) {
2416+ if(!after_ei) {
2417+ // not just after EI is done
2418+ if(prev_after_ei && !after_di) {
2419+ // EI and any instruction (ex. RET, not DI/EI) are done
2420+ d_pic->notify_intr_ei();
2421+ }
24212422 check_interrupt();
24222423 }
24232424 if(now_debugging) {
@@ -2441,11 +2442,12 @@ void Z80::run_one_opecode()
24412442 }
24422443 }
24432444 //#endif
2444- if(prev_after_ei) {
2445- d_pic->notify_intr_ei();
2446- check_interrupt();
2447- after_ei = false;
2448- } else if(!after_ei) {
2445+ if(!after_ei) {
2446+ // not just after EI is done
2447+ if(prev_after_ei && !after_di) {
2448+ // EI and any instruction (ex. RET, not DI/EI) are done
2449+ d_pic->notify_intr_ei();
2450+ }
24492451 check_interrupt();
24502452 }
24512453 //#ifdef USE_DEBUGGER
@@ -2453,10 +2455,92 @@ void Z80::run_one_opecode()
24532455 //#endif
24542456 }
24552457
2458+void Z80::check_interrupt_standard()
2459+{
2460+ if(iff1) { // Standard Z80.
2461+ // interrupt
2462+ LEAVE_HALT();
2463+
2464+ uint32_t vector = d_pic->get_intr_ack();
2465+ if(im == 0) {
2466+ // mode 0 (support NOP/JMP/CALL/RST only)
2467+ switch(vector & 0xff) {
2468+ case 0x00: break; // NOP
2469+ case 0xc3: PCD = vector >> 8; break; // JMP
2470+ case 0xcd: PUSH(pc); PCD = vector >> 8; break; // CALL
2471+ case 0xc7: PUSH(pc); PCD = 0x0000; break; // RST 00H
2472+ case 0xcf: PUSH(pc); PCD = 0x0008; break; // RST 08H
2473+ case 0xd7: PUSH(pc); PCD = 0x0010; break; // RST 10H
2474+ case 0xdf: PUSH(pc); PCD = 0x0018; break; // RST 18H
2475+ case 0xe7: PUSH(pc); PCD = 0x0020; break; // RST 20H
2476+ case 0xef: PUSH(pc); PCD = 0x0028; break; // RST 28H
2477+ case 0xf7: PUSH(pc); PCD = 0x0030; break; // RST 30H
2478+ case 0xff: PUSH(pc); PCD = 0x0038; break; // RST 38H
2479+ }
2480+ icount -= cc_op[vector & 0xff] + cc_ex[0xff];
2481+ } else if(im == 1) {
2482+ // mode 1
2483+ PUSH(pc);
2484+ PCD = 0x0038;
2485+ icount -= cc_op[0xff] + cc_ex[0xff];
2486+ } else {
2487+ // mode 2
2488+ PUSH(pc);
2489+ RM16((vector & 0xff) | (I << 8), &pc);
2490+ icount -= cc_op[0xcd] + cc_ex[0xff];
2491+ }
2492+ iff1 = iff2 = 0;
2493+ intr_req_bit = 0;
2494+ WZ = PCD;
2495+ } else {
2496+ intr_req_bit &= intr_pend_bit;
2497+ }
2498+}
2499+
2500+void Z80::check_interrupt_nsc800()
2501+{
2502+ if(iff1) { // NSC800
2503+ if((intr_req_bit & 8) && (icr & 8)) {
2504+ // RSTA
2505+ LEAVE_HALT();
2506+ PUSH(pc);
2507+ PCD = WZ = 0x003c;
2508+ icount -= cc_op[0xff] + cc_ex[0xff];
2509+ iff1 = iff2 = 0;
2510+ intr_req_bit &= ~8;
2511+ } else if((intr_req_bit & 4) && (icr & 4)) {
2512+ // RSTB
2513+ LEAVE_HALT();
2514+ PUSH(pc);
2515+ PCD = WZ = 0x0034;
2516+ icount -= cc_op[0xff] + cc_ex[0xff];
2517+ iff1 = iff2 = 0;
2518+ intr_req_bit &= ~4;
2519+ } else if((intr_req_bit & 2) && (icr & 2)) {
2520+ // RSTC
2521+ LEAVE_HALT();
2522+ PUSH(pc);
2523+ PCD = WZ = 0x002c;
2524+ icount -= cc_op[0xff] + cc_ex[0xff];
2525+ iff1 = iff2 = 0;
2526+ intr_req_bit &= ~2;
2527+ } else if((intr_req_bit & 1) && (icr & 1)) {
2528+ // INTR
2529+ LEAVE_HALT();
2530+ PUSH(pc);
2531+ PCD = WZ = d_pic->get_intr_ack() & 0xffff;
2532+ icount -= cc_op[0xcd] + cc_ex[0xff];
2533+ iff1 = iff2 = 0;
2534+ intr_req_bit &= ~1;
2535+ }
2536+ }
2537+}
2538+
24562539 void Z80::check_interrupt()
24572540 {
24582541 // check interrupt
24592542 if(intr_req_bit) {
2543+ // Processing NMI is commonly both Z80 and NSC800 .
24602544 if(intr_req_bit & NMI_REQ_BIT) {
24612545 // nmi
24622546 LEAVE_HALT();
@@ -2465,87 +2549,11 @@ void Z80::check_interrupt()
24652549 icount -= 11;
24662550 iff1 = 0;
24672551 intr_req_bit &= ~NMI_REQ_BIT;
2468-//#ifdef HAS_NSC800
24692552 } else if(has_nsc800) {
2470- if((intr_req_bit & 1) && (icr & 1)) {
2471- // INTR
2472- LEAVE_HALT();
2473- PUSH(pc);
2474- if(d_pic != NULL) { // OK?
2475- PCD = WZ = d_pic->get_intr_ack() & 0xffff;
2476- } else {
2477- PCD = WZ = (PCD & 0xff00) | 0xcd;
2478- }
2479- icount -= cc_op[0xcd] + cc_ex[0xff];
2480- iff1 = iff2 = 0;
2481- intr_req_bit &= ~1;
2482- } else if((intr_req_bit & 8) && (icr & 8)) {
2483- // RSTA
2484- LEAVE_HALT();
2485- PUSH(pc);
2486- PCD = WZ = 0x003c;
2487- icount -= cc_op[0xff] + cc_ex[0xff];
2488- iff1 = iff2 = 0;
2489- intr_req_bit &= ~8;
2490- } else if((intr_req_bit & 4) && (icr & 4)) {
2491- // RSTB
2492- LEAVE_HALT();
2493- PUSH(pc);
2494- PCD = WZ = 0x0034;
2495- icount -= cc_op[0xff] + cc_ex[0xff];
2496- iff1 = iff2 = 0;
2497- intr_req_bit &= ~4;
2498- } else if((intr_req_bit & 2) && (icr & 2)) {
2499- // RSTC
2500- LEAVE_HALT();
2501- PUSH(pc);
2502- PCD = WZ = 0x002c;
2503- icount -= cc_op[0xff] + cc_ex[0xff];
2504- iff1 = iff2 = 0;
2505- intr_req_bit &= ~2;
2506- }
2507- } else { // Normal Z80
2508- if(iff1) {
2509- // interrupt
2510- LEAVE_HALT();
2511-
2512- uint32_t vector = 0xcd;
2513- if(d_pic != NULL) vector = d_pic->get_intr_ack();
2514- if(im == 0) {
2515- // mode 0 (support NOP/JMP/CALL/RST only)
2516- switch(vector & 0xff) {
2517- case 0x00: break; // NOP
2518- case 0xc3: PCD = vector >> 8; break; // JMP
2519- case 0xcd: PUSH(pc); PCD = vector >> 8; break; // CALL
2520- case 0xc7: PUSH(pc); PCD = 0x0000; break; // RST 00H
2521- case 0xcf: PUSH(pc); PCD = 0x0008; break; // RST 08H
2522- case 0xd7: PUSH(pc); PCD = 0x0010; break; // RST 10H
2523- case 0xdf: PUSH(pc); PCD = 0x0018; break; // RST 18H
2524- case 0xe7: PUSH(pc); PCD = 0x0020; break; // RST 20H
2525- case 0xef: PUSH(pc); PCD = 0x0028; break; // RST 28H
2526- case 0xf7: PUSH(pc); PCD = 0x0030; break; // RST 30H
2527- case 0xff: PUSH(pc); PCD = 0x0038; break; // RST 38H
2528- }
2529- icount -= cc_op[vector & 0xff] + cc_ex[0xff];
2530- } else if(im == 1) {
2531- // mode 1
2532- PUSH(pc);
2533- PCD = 0x0038;
2534- icount -= cc_op[0xff] + cc_ex[0xff];
2535- } else {
2536- // mode 2
2537- PUSH(pc);
2538- RM16((vector & 0xff) | (I << 8), &pc);
2539- icount -= cc_op[0xcd] + cc_ex[0xff];
2540- }
2541- iff1 = iff2 = 0;
2542- intr_req_bit = 0;
2543- WZ = PCD;
2544- } else {
2545- intr_req_bit &= intr_pend_bit;
2546-//#endif
2547- }
2548-//#else
2553+ // Another processing is different both Z80 and NSC800 .
2554+ check_interrupt_nsc800();
2555+ } else {
2556+ check_interrupt_standard();
25492557 }
25502558 }
25512559 }
@@ -4085,7 +4093,7 @@ int Z80::debug_dasm_with_userdata(uint32_t pc, _TCHAR *buffer, size_t buffer_len
40854093 return z80_dasm_main(pc, buffer, buffer_len, d_debugger->first_symbol);
40864094 }
40874095
4088-#define STATE_VERSION 5
4096+#define STATE_VERSION 6
40894097
40904098 bool Z80::process_state(FILEIO* state_fio, bool loading)
40914099 {
@@ -4126,6 +4134,7 @@ bool Z80::process_state(FILEIO* state_fio, bool loading)
41264134 state_fio->StateValue(iff1);
41274135 state_fio->StateValue(iff2);
41284136 state_fio->StateValue(icr);
4137+ state_fio->StateValue(after_di);
41294138 state_fio->StateValue(after_ei);
41304139 state_fio->StateValue(after_ldair);
41314140 state_fio->StateValue(intr_req_bit);
--- a/source/src/vm/z80.h
+++ b/source/src/vm/z80.h
@@ -79,7 +79,7 @@ protected:
7979
8080 bool busreq, wait, after_halt;
8181 uint8_t im, iff1, iff2, icr;
82- bool after_ei, after_ldair;
82+ bool after_di, after_ei, after_ldair;
8383 uint32_t intr_req_bit, intr_pend_bit;
8484
8585 Z80_INLINE uint8_t __FASTCALL RM8(uint32_t addr);
@@ -256,6 +256,8 @@ protected:
256256 int nsc800_rstc_count;
257257
258258 void check_interrupt();
259+ void check_interrupt_standard();
260+ void check_interrupt_nsc800();
259261
260262 public:
261263 Z80(VM_TEMPLATE* parent_vm, EMU_TEMPLATE* parent_emu) : DEVICE(parent_vm, parent_emu)
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