Revision | 14503 (tree) |
---|---|
Zeit | 2021-06-06 23:16:29 |
Autor | vrepetenko |
SUBGHZ abbreviation changed from RTR to SG, SPIR removed from SPIv2.
@@ -209,21 +209,16 @@ | ||
209 | 209 | /* |
210 | 210 | * SPI driver system settings. |
211 | 211 | */ |
212 | -#define STM32_SPI_USE_SPI1 FALSE | |
212 | +#define STM32_SPI_USE_SPI1 TRUE | |
213 | 213 | #define STM32_SPI_USE_SPI2 FALSE |
214 | -#define STM32_SPI_USE_SPIR TRUE | |
215 | 214 | #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) |
216 | 215 | #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) |
217 | 216 | #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) |
218 | 217 | #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) |
219 | -#define STM32_SPI_SPIR_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) | |
220 | -#define STM32_SPI_SPIR_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) | |
221 | 218 | #define STM32_SPI_SPI1_DMA_PRIORITY 1 |
222 | 219 | #define STM32_SPI_SPI2_DMA_PRIORITY 1 |
223 | -#define STM32_SPI_SPIR_DMA_PRIORITY 1 | |
224 | 220 | #define STM32_SPI_SPI1_IRQ_PRIORITY 10 |
225 | 221 | #define STM32_SPI_SPI2_IRQ_PRIORITY 10 |
226 | -#define STM32_SPI_SPIR_IRQ_PRIORITY 10 | |
227 | 222 | #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") |
228 | 223 | |
229 | 224 | /* |
@@ -45,9 +45,6 @@ | ||
45 | 45 | /* RNG attributes.*/ |
46 | 46 | #define STM32_HAS_RNG1 FALSE |
47 | 47 | |
48 | -/* SPI attributes. */ | |
49 | -#define STM32_HAS_SPIR FALSE | |
50 | - | |
51 | 48 | /*===========================================================================*/ |
52 | 49 | /* STM32F030x4, STM32F030x6, STM32F030x8, STM32F030xC. */ |
53 | 50 | /*===========================================================================*/ |
@@ -38,9 +38,6 @@ | ||
38 | 38 | /* Common. */ |
39 | 39 | /*===========================================================================*/ |
40 | 40 | |
41 | -/* SPI attributes. */ | |
42 | -#define STM32_HAS_SPIR FALSE | |
43 | - | |
44 | 41 | /*===========================================================================*/ |
45 | 42 | /* STM32F373xC. */ |
46 | 43 | /*===========================================================================*/ |
@@ -48,9 +48,6 @@ | ||
48 | 48 | /* RNG attributes.*/ |
49 | 49 | #define STM32_HAS_RNG1 TRUE |
50 | 50 | |
51 | -/* SPI attributes. */ | |
52 | -#define STM32_HAS_SPIR FALSE | |
53 | - | |
54 | 51 | /*===========================================================================*/ |
55 | 52 | /* STM32F303xC. */ |
56 | 53 | /*===========================================================================*/ |
@@ -78,9 +78,6 @@ | ||
78 | 78 | #define STM32_HAS_CRYP1 FALSE |
79 | 79 | #endif |
80 | 80 | |
81 | -/* SPI attributes. */ | |
82 | -#define STM32_HAS_SPIR FALSE | |
83 | - | |
84 | 81 | /*===========================================================================*/ |
85 | 82 | /* STM32F722xx, STM32F723xx, STM32F732xx, STM32F733xx. */ |
86 | 83 | /*===========================================================================*/ |
@@ -101,9 +101,6 @@ | ||
101 | 101 | #define STM32_RCC_HAS_PLLSAI1 FALSE |
102 | 102 | #define STM32_RCC_HAS_PLLSAI2 FALSE |
103 | 103 | |
104 | -/* SPI attributes. */ | |
105 | -#define STM32_HAS_SPIR FALSE | |
106 | - | |
107 | 104 | /*===========================================================================*/ |
108 | 105 | /* STM32G070xx. */ |
109 | 106 | /*===========================================================================*/ |
@@ -111,9 +111,6 @@ | ||
111 | 111 | #define STM32_RCC_HAS_PLLSAI1 FALSE |
112 | 112 | #define STM32_RCC_HAS_PLLSAI2 FALSE |
113 | 113 | |
114 | -/* SPI attributes. */ | |
115 | -#define STM32_HAS_SPIR FALSE | |
116 | - | |
117 | 114 | /*===========================================================================*/ |
118 | 115 | /* STM32G473xx, STM32G4843xx, STM32G474xx, STM32G484xx. */ |
119 | 116 | /*===========================================================================*/ |
@@ -71,9 +71,6 @@ | ||
71 | 71 | #define STM32_HAS_CRYP1 FALSE |
72 | 72 | #endif |
73 | 73 | |
74 | -/* SPI attributes. */ | |
75 | -#define STM32_HAS_SPIR FALSE | |
76 | - | |
77 | 74 | /*===========================================================================*/ |
78 | 75 | /* STM32L432xx. */ |
79 | 76 | /*===========================================================================*/ |
@@ -499,9 +496,7 @@ | ||
499 | 496 | #define STM32_HAS_TIM15 TRUE |
500 | 497 | #define STM32_TIM15_IS_32BITS FALSE |
501 | 498 | #define STM32_TIM15_CHANNELS 2/* SPI attributes. */ |
502 | -#define STM32_HAS_SPIR FALSE | |
503 | 499 | |
504 | - | |
505 | 500 | #define STM32_HAS_TIM16 TRUE |
506 | 501 | #define STM32_TIM16_IS_32BITS FALSE |
507 | 502 | #define STM32_TIM16_CHANNELS 2 |
@@ -98,9 +98,6 @@ | ||
98 | 98 | /* I2C attributes.*/ |
99 | 99 | #define STM32_I2C4_USE_BDMA FALSE |
100 | 100 | |
101 | -/* SPI attributes. */ | |
102 | -#define STM32_HAS_SPIR FALSE | |
103 | - | |
104 | 101 | /*===========================================================================*/ |
105 | 102 | /* STM32L4yyxx+. */ |
106 | 103 | /*===========================================================================*/ |
@@ -68,9 +68,6 @@ | ||
68 | 68 | #define STM32_HAS_HASH1 TRUE |
69 | 69 | #define STM32_HAS_CRYP1 TRUE |
70 | 70 | |
71 | -/* SPI attributes. */ | |
72 | -#define STM32_HAS_SPIR FALSE | |
73 | - | |
74 | 71 | /*===========================================================================*/ |
75 | 72 | /* STM32WB55xx. */ |
76 | 73 | /*===========================================================================*/ |
@@ -73,8 +73,8 @@ | ||
73 | 73 | #define STM32_DMAMUX1_TIM17_UP 38 |
74 | 74 | #define STM32_DMAMUX1_AES_IN 39 |
75 | 75 | #define STM32_DMAMUX1_AES_OUT 40 |
76 | -#define STM32_DMAMUX1_SPIR_RX 41 | |
77 | -#define STM32_DMAMUX1_SPIR_TX 42 | |
76 | +#define STM32_DMAMUX1_SGSPI_RX 41 | |
77 | +#define STM32_DMAMUX1_SGSPI_TX 42 | |
78 | 78 | /** @} */ |
79 | 79 | |
80 | 80 | /*===========================================================================*/ |
@@ -99,7 +99,7 @@ | ||
99 | 99 | #define STM32_EXTI10_15_HANDLER VectorE4 |
100 | 100 | #define STM32_EXTI16_34_HANDLER Vector44 /* PVD PVM3 */ |
101 | 101 | #define STM32_EXTI21_22_HANDLER Vector140 /* COMP1..2 */ |
102 | -#define STM32_EXTI45_HANDLER Vector108 /* RTR */ | |
102 | +#define STM32_EXTI45_HANDLER Vector108 /* SG */ | |
103 | 103 | |
104 | 104 | #define STM32_EXTI0_NUMBER 6 |
105 | 105 | #define STM32_EXTI1_NUMBER 7 |
@@ -166,19 +166,16 @@ | ||
166 | 166 | /* QUADSPI attributes.*/ |
167 | 167 | #define STM32_HAS_QUADSPI1 FALSE |
168 | 168 | |
169 | -/* Radio Transceiver (RTR) attributes.*/ | |
170 | -#define STM32_HAS_RTR TRUE | |
169 | +/* SUBGHZ attributes.*/ | |
170 | +#define STM32_HAS_SG TRUE | |
171 | 171 | #if defined(STM32WLE5xx) || defined(STM32WL55xx) || defined(__DOXYGEN__) |
172 | -#define STM32_RTR_HAS_LORA_MODEM TRUE | |
172 | +#define STM32_SG_HAS_LORA_MODEM TRUE | |
173 | 173 | #else |
174 | -#define STM32_RTR_HAS_LORA_MODEM FALSE | |
174 | +#define STM32_SG_HAS_LORA_MODEM FALSE | |
175 | 175 | #endif /* defined(STM32WLE5xx) || defined(STM32WL55xx) */ |
176 | -#define STM32_RTR_HAS_FSK_MODEM TRUE | |
177 | -#define STM32_RTR_HAS_MSK_MODEM TRUE | |
178 | -#define STM32_RTR_HAS_BPSK_MODEM TRUE | |
179 | -#define STM32_RTR_IRQ_EXTI 44 | |
180 | -#define STM32_RTR_BUSY_EXTI 45 | |
181 | -#define STM32_RTR_IRQ_HANDLER Vector108 | |
176 | +#define STM32_SG_HAS_FSK_MODEM TRUE | |
177 | +#define STM32_SG_HAS_MSK_MODEM TRUE | |
178 | +#define STM32_SG_HAS_BPSK_MODEM TRUE | |
182 | 179 | |
183 | 180 | /* RNG attributes.*/ |
184 | 181 | #define STM32_HAS_RNG1 TRUE |
@@ -237,9 +234,6 @@ | ||
237 | 234 | #define STM32_HAS_SPI2 TRUE |
238 | 235 | #define STM32_SPI2_SUPPORTS_I2S TRUE |
239 | 236 | |
240 | -#define STM32_HAS_SPIR TRUE | |
241 | -#define STM32_SPIR_SUPPORTS_I2S FALSE | |
242 | - | |
243 | 237 | #define STM32_HAS_SPI3 FALSE |
244 | 238 | #define STM32_HAS_SPI4 FALSE |
245 | 239 | #define STM32_HAS_SPI5 FALSE |
@@ -211,19 +211,14 @@ | ||
211 | 211 | */ |
212 | 212 | #define STM32_SPI_USE_SPI1 FALSE |
213 | 213 | #define STM32_SPI_USE_SPI2 FALSE |
214 | -#define STM32_SPI_USE_SPIR FALSE | |
215 | 214 | #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) |
216 | 215 | #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) |
217 | 216 | #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) |
218 | 217 | #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) |
219 | -#define STM32_SPI_SPIR_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) | |
220 | -#define STM32_SPI_SPIR_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) | |
221 | 218 | #define STM32_SPI_SPI1_DMA_PRIORITY 1 |
222 | 219 | #define STM32_SPI_SPI2_DMA_PRIORITY 1 |
223 | -#define STM32_SPI_SPIR_DMA_PRIORITY 1 | |
224 | 220 | #define STM32_SPI_SPI1_IRQ_PRIORITY 10 |
225 | 221 | #define STM32_SPI_SPI2_IRQ_PRIORITY 10 |
226 | -#define STM32_SPI_SPIR_IRQ_PRIORITY 10 | |
227 | 222 | #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") |
228 | 223 | |
229 | 224 | /* |