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chibios: Commit


Commit MetaInfo

Revision13863 (tree)
Zeit2020-09-20 18:35:17
Autorgdisirio

Log Message

Fixed bug #1124.

Ändern Zusammenfassung

Diff

--- branches/stable_19.1.x/os/hal/ports/STM32/STM32F4xx/stm32_registry.h (revision 13862)
+++ branches/stable_19.1.x/os/hal/ports/STM32/STM32F4xx/stm32_registry.h (revision 13863)
@@ -291,7 +291,8 @@
291291
292292 /* SPI attributes.*/
293293 #define STM32_HAS_SPI1 TRUE
294-#define STM32_SPI1_SUPPORTS_I2S FALSE
294+#define STM32_SPI1_SUPPORTS_I2S TRUE
295+#define STM32_SPI1_I2S_FULLDUPLEX TRUE
295296 #define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
296297 STM32_DMA_STREAM_ID_MSK(2, 2))
297298 #define STM32_SPI1_RX_DMA_CHN 0x00000303
@@ -665,7 +666,8 @@
665666
666667 /* SPI attributes.*/
667668 #define STM32_HAS_SPI1 TRUE
668-#define STM32_SPI1_SUPPORTS_I2S FALSE
669+#define STM32_SPI1_SUPPORTS_I2S TRUE
670+#define STM32_SPI1_I2S_FULLDUPLEX FALSE
669671 #define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
670672 STM32_DMA_STREAM_ID_MSK(2, 2))
671673 #define STM32_SPI1_RX_DMA_CHN 0x00000303
@@ -675,7 +677,7 @@
675677
676678 #define STM32_HAS_SPI2 TRUE
677679 #define STM32_SPI2_SUPPORTS_I2S TRUE
678-#define STM32_SPI2_I2S_FULLDUPLEX TRUE
680+#define STM32_SPI2_I2S_FULLDUPLEX FALSE
679681 #define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
680682 #define STM32_SPI2_RX_DMA_CHN 0x00000000
681683 #define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
@@ -683,7 +685,7 @@
683685
684686 #define STM32_HAS_SPI3 TRUE
685687 #define STM32_SPI3_SUPPORTS_I2S TRUE
686-#define STM32_SPI3_I2S_FULLDUPLEX TRUE
688+#define STM32_SPI3_I2S_FULLDUPLEX FALSE
687689 #define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
688690 STM32_DMA_STREAM_ID_MSK(1, 2))
689691 #define STM32_SPI3_RX_DMA_CHN 0x00000000
@@ -1389,7 +1391,7 @@
13891391 /* SPI attributes.*/
13901392 #define STM32_HAS_SPI1 TRUE
13911393 #define STM32_SPI1_SUPPORTS_I2S TRUE
1392-#define STM32_SPI1_I2S_FULLDUPLEX FALSE
1394+#define STM32_SPI1_I2S_FULLDUPLEX TRUE
13931395 #define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
13941396 STM32_DMA_STREAM_ID_MSK(2, 2))
13951397 #define STM32_SPI1_RX_DMA_CHN 0x00000303
@@ -1418,7 +1420,7 @@
14181420
14191421 #define STM32_HAS_SPI4 TRUE
14201422 #define STM32_SPI4_SUPPORTS_I2S TRUE
1421-#define STM32_SPI4_I2S_FULLDUPLEX FALSE
1423+#define STM32_SPI4_I2S_FULLDUPLEX TRUE
14221424 #define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
14231425 STM32_DMA_STREAM_ID_MSK(2, 3) |\
14241426 STM32_DMA_STREAM_ID_MSK(2, 4))
@@ -1429,7 +1431,7 @@
14291431
14301432 #define STM32_HAS_SPI5 TRUE
14311433 #define STM32_SPI5_SUPPORTS_I2S TRUE
1432-#define STM32_SPI5_I2S_FULLDUPLEX FALSE
1434+#define STM32_SPI5_I2S_FULLDUPLEX TRUE
14331435 #define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
14341436 STM32_DMA_STREAM_ID_MSK(2, 5))
14351437 #define STM32_SPI5_RX_DMA_CHN 0x00702000
@@ -1541,7 +1543,7 @@
15411543 #define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
15421544 #define STM32_UART5_RX_DMA_CHN 0x00000004
15431545 #define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
1544-#define STM32_UART5_TX_DMA_CHN 0x40000000
1546+#define STM32_UART5_TX_DMA_CHN 0x80000000
15451547
15461548 #define STM32_HAS_USART6 TRUE
15471549 #define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
@@ -1570,10 +1572,10 @@
15701572 #define STM32_UART9_TX_DMA_CHN 0x00000001
15711573
15721574 #define STM32_HAS_UART10 TRUE
1573-#define STM32_UART10_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 3)
1574-#define STM32_UART10_RX_DMA_CHN 0x00009000
1575-#define STM32_UART10_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 5)
1576-#define STM32_UART10_TX_DMA_CHN 0x00900000
1575+#define STM32_UART10_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 0)
1576+#define STM32_UART10_RX_DMA_CHN 0x00000005
1577+#define STM32_UART10_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
1578+#define STM32_UART10_TX_DMA_CHN 0x60000000
15771579
15781580 #define STM32_HAS_LPUART1 FALSE
15791581
@@ -1761,7 +1763,8 @@
17611763
17621764 /* SPI attributes.*/
17631765 #define STM32_HAS_SPI1 TRUE
1764-#define STM32_SPI1_SUPPORTS_I2S FALSE
1766+#define STM32_SPI1_SUPPORTS_I2S TRUE
1767+#define STM32_SPI1_I2S_FULLDUPLEX TRUE
17651768 #define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
17661769 STM32_DMA_STREAM_ID_MSK(2, 2))
17671770 #define STM32_SPI1_RX_DMA_CHN 0x00000303
@@ -1788,7 +1791,8 @@
17881791 #define STM32_SPI3_TX_DMA_CHN 0x00000000
17891792
17901793 #define STM32_HAS_SPI4 TRUE
1791-#define STM32_SPI4_SUPPORTS_I2S FALSE
1794+#define STM32_SPI4_SUPPORTS_I2S TRUE
1795+#define STM32_SPI4_I2S_FULLDUPLEX TRUE
17921796 #define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
17931797 STM32_DMA_STREAM_ID_MSK(2, 3) |\
17941798 STM32_DMA_STREAM_ID_MSK(2, 4))
@@ -1798,7 +1802,8 @@
17981802 #define STM32_SPI4_TX_DMA_CHN 0x00050040
17991803
18001804 #define STM32_HAS_SPI5 TRUE
1801-#define STM32_SPI5_SUPPORTS_I2S FALSE
1805+#define STM32_SPI5_SUPPORTS_I2S TRUE
1806+#define STM32_SPI5_I2S_FULLDUPLEX TRUE
18021807 #define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
18031808 STM32_DMA_STREAM_ID_MSK(2, 5))
18041809 #define STM32_SPI5_RX_DMA_CHN 0x00702000
@@ -2087,7 +2092,8 @@
20872092
20882093 /* SPI attributes.*/
20892094 #define STM32_HAS_SPI1 TRUE
2090-#define STM32_SPI1_SUPPORTS_I2S FALSE
2095+#define STM32_SPI1_SUPPORTS_I2S TRUE
2096+#define STM32_SPI1_I2S_FULLDUPLEX TRUE
20912097 #define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
20922098 STM32_DMA_STREAM_ID_MSK(2, 2))
20932099 #define STM32_SPI1_RX_DMA_CHN 0x00000303
@@ -2114,7 +2120,8 @@
21142120 #define STM32_SPI3_TX_DMA_CHN 0x00000000
21152121
21162122 #define STM32_HAS_SPI4 TRUE
2117-#define STM32_SPI4_SUPPORTS_I2S FALSE
2123+#define STM32_SPI4_SUPPORTS_I2S TRUE
2124+#define STM32_SPI4_I2S_FULLDUPLEX TRUE
21182125 #define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
21192126 STM32_DMA_STREAM_ID_MSK(2, 3))
21202127 #define STM32_SPI4_RX_DMA_CHN 0x00005004
@@ -2123,7 +2130,8 @@
21232130 #define STM32_SPI4_TX_DMA_CHN 0x00050040
21242131
21252132 #define STM32_HAS_SPI5 TRUE
2126-#define STM32_SPI5_SUPPORTS_I2S FALSE
2133+#define STM32_SPI5_SUPPORTS_I2S TRUE
2134+#define STM32_SPI5_I2S_FULLDUPLEX TRUE
21272135 #define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
21282136 STM32_DMA_STREAM_ID_MSK(2, 5))
21292137 #define STM32_SPI5_RX_DMA_CHN 0x00702000
@@ -2372,7 +2380,7 @@
23722380
23732381 #define STM32_HAS_I2C3 FALSE
23742382
2375-#define STM32_HAS_I2C4 FALSE
2383+#define STM32_HAS_I2C4 TRUE
23762384 #define STM32_I2C4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0)) |\
23772385 STM32_DMA_STREAM_ID_MSK(1, 3))
23782386 #define STM32_I2C4_RX_DMA_CHN 0x00002007
@@ -2388,7 +2396,8 @@
23882396
23892397 /* SPI attributes.*/
23902398 #define STM32_HAS_SPI1 TRUE
2391-#define STM32_SPI1_SUPPORTS_I2S FALSE
2399+#define STM32_SPI1_SUPPORTS_I2S TRUE
2400+#define STM32_SPI1_I2S_FULLDUPLEX TRUE
23922401 #define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
23932402 STM32_DMA_STREAM_ID_MSK(2, 2))
23942403 #define STM32_SPI1_RX_DMA_CHN 0x00000303
@@ -2406,6 +2415,7 @@
24062415
24072416 #define STM32_HAS_SPI5 TRUE
24082417 #define STM32_SPI5_SUPPORTS_I2S TRUE
2418+#define STM32_SPI5_I2S_FULLDUPLEX TRUE
24092419 #define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
24102420 STM32_DMA_STREAM_ID_MSK(2, 5))
24112421 #define STM32_SPI5_RX_DMA_CHN 0x00702000
--- branches/stable_19.1.x/readme.txt (revision 13862)
+++ branches/stable_19.1.x/readme.txt (revision 13863)
@@ -74,6 +74,7 @@
7474 *****************************************************************************
7575
7676 *** 19.1.5 ***
77+- FIX: Fixed I2S-related problems in STM32F4xx registry (bug #1124).
7778 - FIX: Fixed incorrect STM32 iWDG initialization in windowed mode (bug #1122).
7879 - FIX: Fixed ADCv1 compile problem (bug #1118).
7980 - FIX: Fixed missing STM32_I2C_BDMA_REQUIRED definition in I2Cv3 driver
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